ia64/xen-unstable

view linux-2.6-xen-sparse/include/asm-i386/mach-xen/asm/processor.h @ 8944:a05e56904e7e

linux-i386: Fix CONFIG_X86_NO_TSS and CONFIG_X86_SYSENTER.

Signed-off-by: Christian Limpach <Christian.Limpach@cl.cam.ac.uk>
author cl349@firebug.cl.cam.ac.uk
date Mon Feb 20 23:01:50 2006 +0000 (2006-02-20)
parents 16a91d8dd8ed
children 5d3c2cb42ec4
line source
1 /*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/page.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
17 #include <asm/msr.h>
18 #include <asm/system.h>
19 #include <linux/cache.h>
20 #include <linux/config.h>
21 #include <linux/threads.h>
22 #include <asm/percpu.h>
23 #include <xen/interface/physdev.h>
25 /* flag for disabling the tsc */
26 extern int tsc_disable;
28 struct desc_struct {
29 unsigned long a,b;
30 };
32 #define desc_empty(desc) \
33 (!((desc)->a | (desc)->b))
35 #define desc_equal(desc1, desc2) \
36 (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
37 /*
38 * Default implementation of macro that returns current
39 * instruction pointer ("program counter").
40 */
41 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
43 /*
44 * CPU type and hardware bug flags. Kept separately for each CPU.
45 * Members of this structure are referenced in head.S, so think twice
46 * before touching them. [mj]
47 */
49 struct cpuinfo_x86 {
50 __u8 x86; /* CPU family */
51 __u8 x86_vendor; /* CPU vendor */
52 __u8 x86_model;
53 __u8 x86_mask;
54 char wp_works_ok; /* It doesn't on 386's */
55 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
56 char hard_math;
57 char rfu;
58 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
59 unsigned long x86_capability[NCAPINTS];
60 char x86_vendor_id[16];
61 char x86_model_id[64];
62 int x86_cache_size; /* in KB - valid for CPUS which support this
63 call */
64 int x86_cache_alignment; /* In bytes */
65 char fdiv_bug;
66 char f00f_bug;
67 char coma_bug;
68 char pad0;
69 int x86_power;
70 unsigned long loops_per_jiffy;
71 unsigned char x86_max_cores; /* cpuid returned max cores value */
72 unsigned char booted_cores; /* number of cores as seen by OS */
73 unsigned char apicid;
74 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
76 #define X86_VENDOR_INTEL 0
77 #define X86_VENDOR_CYRIX 1
78 #define X86_VENDOR_AMD 2
79 #define X86_VENDOR_UMC 3
80 #define X86_VENDOR_NEXGEN 4
81 #define X86_VENDOR_CENTAUR 5
82 #define X86_VENDOR_RISE 6
83 #define X86_VENDOR_TRANSMETA 7
84 #define X86_VENDOR_NSC 8
85 #define X86_VENDOR_NUM 9
86 #define X86_VENDOR_UNKNOWN 0xff
88 /*
89 * capabilities of CPUs
90 */
92 extern struct cpuinfo_x86 boot_cpu_data;
93 extern struct cpuinfo_x86 new_cpu_data;
94 #ifndef CONFIG_X86_NO_TSS
95 extern struct tss_struct doublefault_tss;
96 DECLARE_PER_CPU(struct tss_struct, init_tss);
97 #endif
99 #ifdef CONFIG_SMP
100 extern struct cpuinfo_x86 cpu_data[];
101 #define current_cpu_data cpu_data[smp_processor_id()]
102 #else
103 #define cpu_data (&boot_cpu_data)
104 #define current_cpu_data boot_cpu_data
105 #endif
107 extern int phys_proc_id[NR_CPUS];
108 extern int cpu_core_id[NR_CPUS];
109 extern char ignore_fpu_irq;
111 extern void identify_cpu(struct cpuinfo_x86 *);
112 extern void print_cpu_info(struct cpuinfo_x86 *);
113 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
115 #ifdef CONFIG_X86_HT
116 extern void detect_ht(struct cpuinfo_x86 *c);
117 #else
118 static inline void detect_ht(struct cpuinfo_x86 *c) {}
119 #endif
121 /*
122 * EFLAGS bits
123 */
124 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
125 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
126 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
127 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
128 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
129 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
130 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
131 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
132 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
133 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
134 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
135 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
136 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
137 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
138 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
139 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
140 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
142 /*
143 * Generic CPUID function
144 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
145 * resulting in stale register contents being returned.
146 */
147 static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx, unsigned int *ecx, unsigned int *edx)
148 {
149 __asm__("cpuid"
150 : "=a" (*eax),
151 "=b" (*ebx),
152 "=c" (*ecx),
153 "=d" (*edx)
154 : "0" (op), "c"(0));
155 }
157 /* Some CPUID calls want 'count' to be placed in ecx */
158 static inline void cpuid_count(int op, int count, int *eax, int *ebx, int *ecx,
159 int *edx)
160 {
161 __asm__("cpuid"
162 : "=a" (*eax),
163 "=b" (*ebx),
164 "=c" (*ecx),
165 "=d" (*edx)
166 : "0" (op), "c" (count));
167 }
169 /*
170 * CPUID functions returning a single datum
171 */
172 static inline unsigned int cpuid_eax(unsigned int op)
173 {
174 unsigned int eax;
176 __asm__("cpuid"
177 : "=a" (eax)
178 : "0" (op)
179 : "bx", "cx", "dx");
180 return eax;
181 }
182 static inline unsigned int cpuid_ebx(unsigned int op)
183 {
184 unsigned int eax, ebx;
186 __asm__("cpuid"
187 : "=a" (eax), "=b" (ebx)
188 : "0" (op)
189 : "cx", "dx" );
190 return ebx;
191 }
192 static inline unsigned int cpuid_ecx(unsigned int op)
193 {
194 unsigned int eax, ecx;
196 __asm__("cpuid"
197 : "=a" (eax), "=c" (ecx)
198 : "0" (op)
199 : "bx", "dx" );
200 return ecx;
201 }
202 static inline unsigned int cpuid_edx(unsigned int op)
203 {
204 unsigned int eax, edx;
206 __asm__("cpuid"
207 : "=a" (eax), "=d" (edx)
208 : "0" (op)
209 : "bx", "cx");
210 return edx;
211 }
213 #define load_cr3(pgdir) write_cr3(__pa(pgdir))
215 /*
216 * Intel CPU features in CR4
217 */
218 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
219 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
220 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
221 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
222 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
223 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
224 #define X86_CR4_MCE 0x0040 /* Machine check enable */
225 #define X86_CR4_PGE 0x0080 /* enable global pages */
226 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
227 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
228 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
230 /*
231 * Save the cr4 feature set we're using (ie
232 * Pentium 4MB enable and PPro Global page
233 * enable), so that any CPU's that boot up
234 * after us can get the correct flags.
235 */
236 extern unsigned long mmu_cr4_features;
238 static inline void set_in_cr4 (unsigned long mask)
239 {
240 mmu_cr4_features |= mask;
241 switch (mask) {
242 case X86_CR4_OSFXSR:
243 case X86_CR4_OSXMMEXCPT:
244 break;
245 default:
246 do {
247 const char *msg = "Xen unsupported cr4 update\n";
248 (void)HYPERVISOR_console_io(
249 CONSOLEIO_write, __builtin_strlen(msg),
250 (char *)msg);
251 BUG();
252 } while (0);
253 }
254 }
256 static inline void clear_in_cr4 (unsigned long mask)
257 {
258 unsigned cr4;
259 mmu_cr4_features &= ~mask;
260 cr4 = read_cr4();
261 cr4 &= ~mask;
262 write_cr4(cr4);
263 }
265 /*
266 * NSC/Cyrix CPU configuration register indexes
267 */
269 #define CX86_PCR0 0x20
270 #define CX86_GCR 0xb8
271 #define CX86_CCR0 0xc0
272 #define CX86_CCR1 0xc1
273 #define CX86_CCR2 0xc2
274 #define CX86_CCR3 0xc3
275 #define CX86_CCR4 0xe8
276 #define CX86_CCR5 0xe9
277 #define CX86_CCR6 0xea
278 #define CX86_CCR7 0xeb
279 #define CX86_PCR1 0xf0
280 #define CX86_DIR0 0xfe
281 #define CX86_DIR1 0xff
282 #define CX86_ARR_BASE 0xc4
283 #define CX86_RCR_BASE 0xdc
285 /*
286 * NSC/Cyrix CPU indexed register access macros
287 */
289 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
291 #define setCx86(reg, data) do { \
292 outb((reg), 0x22); \
293 outb((data), 0x23); \
294 } while (0)
296 /* Stop speculative execution */
297 static inline void sync_core(void)
298 {
299 int tmp;
300 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
301 }
303 static inline void __monitor(const void *eax, unsigned long ecx,
304 unsigned long edx)
305 {
306 /* "monitor %eax,%ecx,%edx;" */
307 asm volatile(
308 ".byte 0x0f,0x01,0xc8;"
309 : :"a" (eax), "c" (ecx), "d"(edx));
310 }
312 static inline void __mwait(unsigned long eax, unsigned long ecx)
313 {
314 /* "mwait %eax,%ecx;" */
315 asm volatile(
316 ".byte 0x0f,0x01,0xc9;"
317 : :"a" (eax), "c" (ecx));
318 }
320 /* from system description table in BIOS. Mostly for MCA use, but
321 others may find it useful. */
322 extern unsigned int machine_id;
323 extern unsigned int machine_submodel_id;
324 extern unsigned int BIOS_revision;
325 extern unsigned int mca_pentium_flag;
327 /* Boot loader type from the setup header */
328 extern int bootloader_type;
330 /*
331 * User space process size: 3GB (default).
332 */
333 #define TASK_SIZE (PAGE_OFFSET)
335 /* This decides where the kernel will search for a free chunk of vm
336 * space during mmap's.
337 */
338 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
340 #define HAVE_ARCH_PICK_MMAP_LAYOUT
342 /*
343 * Size of io_bitmap.
344 */
345 #define IO_BITMAP_BITS 65536
346 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
347 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
348 #ifndef CONFIG_X86_NO_TSS
349 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
350 #endif
351 #define INVALID_IO_BITMAP_OFFSET 0x8000
352 #define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
354 struct i387_fsave_struct {
355 long cwd;
356 long swd;
357 long twd;
358 long fip;
359 long fcs;
360 long foo;
361 long fos;
362 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
363 long status; /* software status information */
364 };
366 struct i387_fxsave_struct {
367 unsigned short cwd;
368 unsigned short swd;
369 unsigned short twd;
370 unsigned short fop;
371 long fip;
372 long fcs;
373 long foo;
374 long fos;
375 long mxcsr;
376 long mxcsr_mask;
377 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
378 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
379 long padding[56];
380 } __attribute__ ((aligned (16)));
382 struct i387_soft_struct {
383 long cwd;
384 long swd;
385 long twd;
386 long fip;
387 long fcs;
388 long foo;
389 long fos;
390 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
391 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
392 struct info *info;
393 unsigned long entry_eip;
394 };
396 union i387_union {
397 struct i387_fsave_struct fsave;
398 struct i387_fxsave_struct fxsave;
399 struct i387_soft_struct soft;
400 };
402 typedef struct {
403 unsigned long seg;
404 } mm_segment_t;
406 struct thread_struct;
408 #ifndef CONFIG_X86_NO_TSS
409 struct tss_struct {
410 unsigned short back_link,__blh;
411 unsigned long esp0;
412 unsigned short ss0,__ss0h;
413 unsigned long esp1;
414 unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
415 unsigned long esp2;
416 unsigned short ss2,__ss2h;
417 unsigned long __cr3;
418 unsigned long eip;
419 unsigned long eflags;
420 unsigned long eax,ecx,edx,ebx;
421 unsigned long esp;
422 unsigned long ebp;
423 unsigned long esi;
424 unsigned long edi;
425 unsigned short es, __esh;
426 unsigned short cs, __csh;
427 unsigned short ss, __ssh;
428 unsigned short ds, __dsh;
429 unsigned short fs, __fsh;
430 unsigned short gs, __gsh;
431 unsigned short ldt, __ldth;
432 unsigned short trace, io_bitmap_base;
433 /*
434 * The extra 1 is there because the CPU will access an
435 * additional byte beyond the end of the IO permission
436 * bitmap. The extra byte must be all 1 bits, and must
437 * be within the limit.
438 */
439 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
440 /*
441 * Cache the current maximum and the last task that used the bitmap:
442 */
443 unsigned long io_bitmap_max;
444 struct thread_struct *io_bitmap_owner;
445 /*
446 * pads the TSS to be cacheline-aligned (size is 0x100)
447 */
448 unsigned long __cacheline_filler[35];
449 /*
450 * .. and then another 0x100 bytes for emergency kernel stack
451 */
452 unsigned long stack[64];
453 } __attribute__((packed));
454 #endif
456 #define ARCH_MIN_TASKALIGN 16
458 struct thread_struct {
459 /* cached TLS descriptors. */
460 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
461 unsigned long esp0;
462 unsigned long sysenter_cs;
463 unsigned long eip;
464 unsigned long esp;
465 unsigned long fs;
466 unsigned long gs;
467 /* Hardware debugging registers */
468 unsigned long debugreg[8]; /* %%db0-7 debug registers */
469 /* fault info */
470 unsigned long cr2, trap_no, error_code;
471 /* floating point info */
472 union i387_union i387;
473 /* virtual 86 mode info */
474 struct vm86_struct __user * vm86_info;
475 unsigned long screen_bitmap;
476 unsigned long v86flags, v86mask, saved_esp0;
477 unsigned int saved_fs, saved_gs;
478 /* IO permissions */
479 unsigned long *io_bitmap_ptr;
480 unsigned long iopl;
481 /* max allowed port in the bitmap, in bytes: */
482 unsigned long io_bitmap_max;
483 };
485 #define INIT_THREAD { \
486 .vm86_info = NULL, \
487 .sysenter_cs = __KERNEL_CS, \
488 .io_bitmap_ptr = NULL, \
489 }
491 #ifndef CONFIG_X86_NO_TSS
492 /*
493 * Note that the .io_bitmap member must be extra-big. This is because
494 * the CPU will access an additional byte beyond the end of the IO
495 * permission bitmap. The extra byte must be all 1 bits, and must
496 * be within the limit.
497 */
498 #define INIT_TSS { \
499 .esp0 = sizeof(init_stack) + (long)&init_stack, \
500 .ss0 = __KERNEL_DS, \
501 .ss1 = __KERNEL_CS, \
502 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
503 .io_bitmap = { [ 0 ... IO_BITMAP_LONGS] = ~0 }, \
504 }
506 static inline void __load_esp0(struct tss_struct *tss, struct thread_struct *thread)
507 {
508 tss->esp0 = thread->esp0;
509 #ifdef CONFIG_X86_SYSENTER
510 /* This can only happen when SEP is enabled, no need to test "SEP"arately */
511 if (unlikely(tss->ss1 != thread->sysenter_cs)) {
512 tss->ss1 = thread->sysenter_cs;
513 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
514 }
515 #endif
516 }
517 #define load_esp0(tss, thread) \
518 __load_esp0(tss, thread)
519 #else
520 #define load_esp0(tss, thread) \
521 HYPERVISOR_stack_switch(__KERNEL_DS, (thread)->esp0)
522 #endif
524 #define start_thread(regs, new_eip, new_esp) do { \
525 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
526 set_fs(USER_DS); \
527 regs->xds = __USER_DS; \
528 regs->xes = __USER_DS; \
529 regs->xss = __USER_DS; \
530 regs->xcs = __USER_CS; \
531 regs->eip = new_eip; \
532 regs->esp = new_esp; \
533 } while (0)
535 /*
536 * These special macros can be used to get or set a debugging register
537 */
538 #define get_debugreg(var, register) \
539 (var) = HYPERVISOR_get_debugreg((register))
540 #define set_debugreg(value, register) \
541 HYPERVISOR_set_debugreg((register), (value))
543 /*
544 * Set IOPL bits in EFLAGS from given mask
545 */
546 static inline void set_iopl_mask(unsigned mask)
547 {
548 physdev_op_t op;
550 /* Force the change at ring 0. */
551 op.cmd = PHYSDEVOP_SET_IOPL;
552 op.u.set_iopl.iopl = (mask == 0) ? 1 : (mask >> 12) & 3;
553 HYPERVISOR_physdev_op(&op);
554 }
556 /* Forward declaration, a strange C thing */
557 struct task_struct;
558 struct mm_struct;
560 /* Free all resources held by a thread. */
561 extern void release_thread(struct task_struct *);
563 /* Prepare to copy thread state - unlazy all lazy status */
564 extern void prepare_to_copy(struct task_struct *tsk);
566 /*
567 * create a kernel thread without removing it from tasklists
568 */
569 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
571 extern unsigned long thread_saved_pc(struct task_struct *tsk);
572 void show_trace(struct task_struct *task, unsigned long *stack);
574 unsigned long get_wchan(struct task_struct *p);
576 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
577 #define KSTK_TOP(info) \
578 ({ \
579 unsigned long *__ptr = (unsigned long *)(info); \
580 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
581 })
583 /*
584 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
585 * This is necessary to guarantee that the entire "struct pt_regs"
586 * is accessable even if the CPU haven't stored the SS/ESP registers
587 * on the stack (interrupt gate does not save these registers
588 * when switching to the same priv ring).
589 * Therefore beware: accessing the xss/esp fields of the
590 * "struct pt_regs" is possible, but they may contain the
591 * completely wrong values.
592 */
593 #define task_pt_regs(task) \
594 ({ \
595 struct pt_regs *__regs__; \
596 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
597 __regs__ - 1; \
598 })
600 #define KSTK_EIP(task) (task_pt_regs(task)->eip)
601 #define KSTK_ESP(task) (task_pt_regs(task)->esp)
604 struct microcode_header {
605 unsigned int hdrver;
606 unsigned int rev;
607 unsigned int date;
608 unsigned int sig;
609 unsigned int cksum;
610 unsigned int ldrver;
611 unsigned int pf;
612 unsigned int datasize;
613 unsigned int totalsize;
614 unsigned int reserved[3];
615 };
617 struct microcode {
618 struct microcode_header hdr;
619 unsigned int bits[0];
620 };
622 typedef struct microcode microcode_t;
623 typedef struct microcode_header microcode_header_t;
625 /* microcode format is extended from prescott processors */
626 struct extended_signature {
627 unsigned int sig;
628 unsigned int pf;
629 unsigned int cksum;
630 };
632 struct extended_sigtable {
633 unsigned int count;
634 unsigned int cksum;
635 unsigned int reserved[3];
636 struct extended_signature sigs[0];
637 };
638 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
639 #define MICROCODE_IOCFREE _IO('6',0)
641 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
642 static inline void rep_nop(void)
643 {
644 __asm__ __volatile__("rep;nop": : :"memory");
645 }
647 #define cpu_relax() rep_nop()
649 /* generic versions from gas */
650 #define GENERIC_NOP1 ".byte 0x90\n"
651 #define GENERIC_NOP2 ".byte 0x89,0xf6\n"
652 #define GENERIC_NOP3 ".byte 0x8d,0x76,0x00\n"
653 #define GENERIC_NOP4 ".byte 0x8d,0x74,0x26,0x00\n"
654 #define GENERIC_NOP5 GENERIC_NOP1 GENERIC_NOP4
655 #define GENERIC_NOP6 ".byte 0x8d,0xb6,0x00,0x00,0x00,0x00\n"
656 #define GENERIC_NOP7 ".byte 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00\n"
657 #define GENERIC_NOP8 GENERIC_NOP1 GENERIC_NOP7
659 /* Opteron nops */
660 #define K8_NOP1 GENERIC_NOP1
661 #define K8_NOP2 ".byte 0x66,0x90\n"
662 #define K8_NOP3 ".byte 0x66,0x66,0x90\n"
663 #define K8_NOP4 ".byte 0x66,0x66,0x66,0x90\n"
664 #define K8_NOP5 K8_NOP3 K8_NOP2
665 #define K8_NOP6 K8_NOP3 K8_NOP3
666 #define K8_NOP7 K8_NOP4 K8_NOP3
667 #define K8_NOP8 K8_NOP4 K8_NOP4
669 /* K7 nops */
670 /* uses eax dependencies (arbitary choice) */
671 #define K7_NOP1 GENERIC_NOP1
672 #define K7_NOP2 ".byte 0x8b,0xc0\n"
673 #define K7_NOP3 ".byte 0x8d,0x04,0x20\n"
674 #define K7_NOP4 ".byte 0x8d,0x44,0x20,0x00\n"
675 #define K7_NOP5 K7_NOP4 ASM_NOP1
676 #define K7_NOP6 ".byte 0x8d,0x80,0,0,0,0\n"
677 #define K7_NOP7 ".byte 0x8D,0x04,0x05,0,0,0,0\n"
678 #define K7_NOP8 K7_NOP7 ASM_NOP1
680 #ifdef CONFIG_MK8
681 #define ASM_NOP1 K8_NOP1
682 #define ASM_NOP2 K8_NOP2
683 #define ASM_NOP3 K8_NOP3
684 #define ASM_NOP4 K8_NOP4
685 #define ASM_NOP5 K8_NOP5
686 #define ASM_NOP6 K8_NOP6
687 #define ASM_NOP7 K8_NOP7
688 #define ASM_NOP8 K8_NOP8
689 #elif defined(CONFIG_MK7)
690 #define ASM_NOP1 K7_NOP1
691 #define ASM_NOP2 K7_NOP2
692 #define ASM_NOP3 K7_NOP3
693 #define ASM_NOP4 K7_NOP4
694 #define ASM_NOP5 K7_NOP5
695 #define ASM_NOP6 K7_NOP6
696 #define ASM_NOP7 K7_NOP7
697 #define ASM_NOP8 K7_NOP8
698 #else
699 #define ASM_NOP1 GENERIC_NOP1
700 #define ASM_NOP2 GENERIC_NOP2
701 #define ASM_NOP3 GENERIC_NOP3
702 #define ASM_NOP4 GENERIC_NOP4
703 #define ASM_NOP5 GENERIC_NOP5
704 #define ASM_NOP6 GENERIC_NOP6
705 #define ASM_NOP7 GENERIC_NOP7
706 #define ASM_NOP8 GENERIC_NOP8
707 #endif
709 #define ASM_NOP_MAX 8
711 /* Prefetch instructions for Pentium III and AMD Athlon */
712 /* It's not worth to care about 3dnow! prefetches for the K6
713 because they are microcoded there and very slow.
714 However we don't do prefetches for pre XP Athlons currently
715 That should be fixed. */
716 #define ARCH_HAS_PREFETCH
717 static inline void prefetch(const void *x)
718 {
719 alternative_input(ASM_NOP4,
720 "prefetchnta (%1)",
721 X86_FEATURE_XMM,
722 "r" (x));
723 }
725 #define ARCH_HAS_PREFETCH
726 #define ARCH_HAS_PREFETCHW
727 #define ARCH_HAS_SPINLOCK_PREFETCH
729 /* 3dnow! prefetch to get an exclusive cache line. Useful for
730 spinlocks to avoid one state transition in the cache coherency protocol. */
731 static inline void prefetchw(const void *x)
732 {
733 alternative_input(ASM_NOP4,
734 "prefetchw (%1)",
735 X86_FEATURE_3DNOW,
736 "r" (x));
737 }
738 #define spin_lock_prefetch(x) prefetchw(x)
740 extern void select_idle_routine(const struct cpuinfo_x86 *c);
742 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
744 extern unsigned long boot_option_idle_override;
745 extern void enable_sep_cpu(void);
746 extern int sysenter_setup(void);
748 #ifdef CONFIG_MTRR
749 extern void mtrr_ap_init(void);
750 extern void mtrr_bp_init(void);
751 #else
752 #define mtrr_ap_init() do {} while (0)
753 #define mtrr_bp_init() do {} while (0)
754 #endif
756 #ifdef CONFIG_X86_MCE
757 extern void mcheck_init(struct cpuinfo_x86 *c);
758 #else
759 #define mcheck_init(c) do {} while(0)
760 #endif
762 #endif /* __ASM_I386_PROCESSOR_H */