ia64/xen-unstable

view linux-2.6-xen-sparse/arch/i386/kernel/cpu/common-xen.c @ 8944:a05e56904e7e

linux-i386: Fix CONFIG_X86_NO_TSS and CONFIG_X86_SYSENTER.

Signed-off-by: Christian Limpach <Christian.Limpach@cl.cam.ac.uk>
author cl349@firebug.cl.cam.ac.uk
date Mon Feb 20 23:01:50 2006 +0000 (2006-02-20)
parents 16a91d8dd8ed
children f06f8c9a13d1
line source
1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
4 #include <linux/smp.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <asm/semaphore.h>
8 #include <asm/processor.h>
9 #include <asm/i387.h>
10 #include <asm/msr.h>
11 #include <asm/io.h>
12 #include <asm/mmu_context.h>
13 #ifdef CONFIG_X86_LOCAL_APIC
14 #include <asm/mpspec.h>
15 #include <asm/apic.h>
16 #include <mach_apic.h>
17 #endif
18 #include <asm/hypervisor.h>
20 #include "cpu.h"
22 #ifndef CONFIG_XEN
23 DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
24 EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack);
25 #endif
27 static int cachesize_override __devinitdata = -1;
28 static int disable_x86_fxsr __devinitdata = 0;
29 static int disable_x86_serial_nr __devinitdata = 1;
31 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
33 extern void machine_specific_modify_cpu_capabilities(struct cpuinfo_x86 *c);
35 extern int disable_pse;
37 static void default_init(struct cpuinfo_x86 * c)
38 {
39 /* Not much we can do here... */
40 /* Check if at least it has cpuid */
41 if (c->cpuid_level == -1) {
42 /* No cpuid. It must be an ancient CPU */
43 if (c->x86 == 4)
44 strcpy(c->x86_model_id, "486");
45 else if (c->x86 == 3)
46 strcpy(c->x86_model_id, "386");
47 }
48 }
50 static struct cpu_dev default_cpu = {
51 .c_init = default_init,
52 .c_vendor = "Unknown",
53 };
54 static struct cpu_dev * this_cpu = &default_cpu;
56 static int __init cachesize_setup(char *str)
57 {
58 get_option (&str, &cachesize_override);
59 return 1;
60 }
61 __setup("cachesize=", cachesize_setup);
63 int __devinit get_model_name(struct cpuinfo_x86 *c)
64 {
65 unsigned int *v;
66 char *p, *q;
68 if (cpuid_eax(0x80000000) < 0x80000004)
69 return 0;
71 v = (unsigned int *) c->x86_model_id;
72 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
73 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
74 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
75 c->x86_model_id[48] = 0;
77 /* Intel chips right-justify this string for some dumb reason;
78 undo that brain damage */
79 p = q = &c->x86_model_id[0];
80 while ( *p == ' ' )
81 p++;
82 if ( p != q ) {
83 while ( *p )
84 *q++ = *p++;
85 while ( q <= &c->x86_model_id[48] )
86 *q++ = '\0'; /* Zero-pad the rest */
87 }
89 return 1;
90 }
93 void __devinit display_cacheinfo(struct cpuinfo_x86 *c)
94 {
95 unsigned int n, dummy, ecx, edx, l2size;
97 n = cpuid_eax(0x80000000);
99 if (n >= 0x80000005) {
100 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
101 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
102 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
103 c->x86_cache_size=(ecx>>24)+(edx>>24);
104 }
106 if (n < 0x80000006) /* Some chips just has a large L1. */
107 return;
109 ecx = cpuid_ecx(0x80000006);
110 l2size = ecx >> 16;
112 /* do processor-specific cache resizing */
113 if (this_cpu->c_size_cache)
114 l2size = this_cpu->c_size_cache(c,l2size);
116 /* Allow user to override all this if necessary. */
117 if (cachesize_override != -1)
118 l2size = cachesize_override;
120 if ( l2size == 0 )
121 return; /* Again, no L2 cache is possible */
123 c->x86_cache_size = l2size;
125 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
126 l2size, ecx & 0xFF);
127 }
129 /* Naming convention should be: <Name> [(<Codename>)] */
130 /* This table only is used unless init_<vendor>() below doesn't set it; */
131 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
133 /* Look up CPU names by table lookup. */
134 static char __devinit *table_lookup_model(struct cpuinfo_x86 *c)
135 {
136 struct cpu_model_info *info;
138 if ( c->x86_model >= 16 )
139 return NULL; /* Range check */
141 if (!this_cpu)
142 return NULL;
144 info = this_cpu->c_models;
146 while (info && info->family) {
147 if (info->family == c->x86)
148 return info->model_names[c->x86_model];
149 info++;
150 }
151 return NULL; /* Not found */
152 }
155 static void __devinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
156 {
157 char *v = c->x86_vendor_id;
158 int i;
159 static int printed;
161 for (i = 0; i < X86_VENDOR_NUM; i++) {
162 if (cpu_devs[i]) {
163 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
164 (cpu_devs[i]->c_ident[1] &&
165 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
166 c->x86_vendor = i;
167 if (!early)
168 this_cpu = cpu_devs[i];
169 return;
170 }
171 }
172 }
173 if (!printed) {
174 printed++;
175 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
176 printk(KERN_ERR "CPU: Your system may be unstable.\n");
177 }
178 c->x86_vendor = X86_VENDOR_UNKNOWN;
179 this_cpu = &default_cpu;
180 }
183 static int __init x86_fxsr_setup(char * s)
184 {
185 disable_x86_fxsr = 1;
186 return 1;
187 }
188 __setup("nofxsr", x86_fxsr_setup);
191 /* Standard macro to see if a specific flag is changeable */
192 static inline int flag_is_changeable_p(u32 flag)
193 {
194 u32 f1, f2;
196 asm("pushfl\n\t"
197 "pushfl\n\t"
198 "popl %0\n\t"
199 "movl %0,%1\n\t"
200 "xorl %2,%0\n\t"
201 "pushl %0\n\t"
202 "popfl\n\t"
203 "pushfl\n\t"
204 "popl %0\n\t"
205 "popfl\n\t"
206 : "=&r" (f1), "=&r" (f2)
207 : "ir" (flag));
209 return ((f1^f2) & flag) != 0;
210 }
213 /* Probe for the CPUID instruction */
214 static int __devinit have_cpuid_p(void)
215 {
216 return flag_is_changeable_p(X86_EFLAGS_ID);
217 }
219 /* Do minimum CPU detection early.
220 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
221 The others are not touched to avoid unwanted side effects.
223 WARNING: this function is only called on the BP. Don't add code here
224 that is supposed to run on all CPUs. */
225 static void __init early_cpu_detect(void)
226 {
227 struct cpuinfo_x86 *c = &boot_cpu_data;
229 c->x86_cache_alignment = 32;
231 if (!have_cpuid_p())
232 return;
234 /* Get vendor name */
235 cpuid(0x00000000, &c->cpuid_level,
236 (int *)&c->x86_vendor_id[0],
237 (int *)&c->x86_vendor_id[8],
238 (int *)&c->x86_vendor_id[4]);
240 get_cpu_vendor(c, 1);
242 c->x86 = 4;
243 if (c->cpuid_level >= 0x00000001) {
244 u32 junk, tfms, cap0, misc;
245 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
246 c->x86 = (tfms >> 8) & 15;
247 c->x86_model = (tfms >> 4) & 15;
248 if (c->x86 == 0xf)
249 c->x86 += (tfms >> 20) & 0xff;
250 if (c->x86 >= 0x6)
251 c->x86_model += ((tfms >> 16) & 0xF) << 4;
252 c->x86_mask = tfms & 15;
253 if (cap0 & (1<<19))
254 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
255 }
256 }
258 void __devinit generic_identify(struct cpuinfo_x86 * c)
259 {
260 u32 tfms, xlvl;
261 int junk;
263 if (have_cpuid_p()) {
264 /* Get vendor name */
265 cpuid(0x00000000, &c->cpuid_level,
266 (int *)&c->x86_vendor_id[0],
267 (int *)&c->x86_vendor_id[8],
268 (int *)&c->x86_vendor_id[4]);
270 get_cpu_vendor(c, 0);
271 /* Initialize the standard set of capabilities */
272 /* Note that the vendor-specific code below might override */
274 /* Intel-defined flags: level 0x00000001 */
275 if ( c->cpuid_level >= 0x00000001 ) {
276 u32 capability, excap;
277 cpuid(0x00000001, &tfms, &junk, &excap, &capability);
278 c->x86_capability[0] = capability;
279 c->x86_capability[4] = excap;
280 c->x86 = (tfms >> 8) & 15;
281 c->x86_model = (tfms >> 4) & 15;
282 if (c->x86 == 0xf) {
283 c->x86 += (tfms >> 20) & 0xff;
284 c->x86_model += ((tfms >> 16) & 0xF) << 4;
285 }
286 c->x86_mask = tfms & 15;
287 } else {
288 /* Have CPUID level 0 only - unheard of */
289 c->x86 = 4;
290 }
292 /* AMD-defined flags: level 0x80000001 */
293 xlvl = cpuid_eax(0x80000000);
294 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
295 if ( xlvl >= 0x80000001 ) {
296 c->x86_capability[1] = cpuid_edx(0x80000001);
297 c->x86_capability[6] = cpuid_ecx(0x80000001);
298 }
299 if ( xlvl >= 0x80000004 )
300 get_model_name(c); /* Default name */
301 }
302 }
304 early_intel_workaround(c);
306 #ifdef CONFIG_X86_HT
307 phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
308 #endif
309 }
311 static void __devinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
312 {
313 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
314 /* Disable processor serial number */
315 unsigned long lo,hi;
316 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
317 lo |= 0x200000;
318 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
319 printk(KERN_NOTICE "CPU serial number disabled.\n");
320 clear_bit(X86_FEATURE_PN, c->x86_capability);
322 /* Disabling the serial number may affect the cpuid level */
323 c->cpuid_level = cpuid_eax(0);
324 }
325 }
327 static int __init x86_serial_nr_setup(char *s)
328 {
329 disable_x86_serial_nr = 0;
330 return 1;
331 }
332 __setup("serialnumber", x86_serial_nr_setup);
336 /*
337 * This does the hard work of actually picking apart the CPU stuff...
338 */
339 void __devinit identify_cpu(struct cpuinfo_x86 *c)
340 {
341 int i;
343 c->loops_per_jiffy = loops_per_jiffy;
344 c->x86_cache_size = -1;
345 c->x86_vendor = X86_VENDOR_UNKNOWN;
346 c->cpuid_level = -1; /* CPUID not detected */
347 c->x86_model = c->x86_mask = 0; /* So far unknown... */
348 c->x86_vendor_id[0] = '\0'; /* Unset */
349 c->x86_model_id[0] = '\0'; /* Unset */
350 c->x86_max_cores = 1;
351 memset(&c->x86_capability, 0, sizeof c->x86_capability);
353 if (!have_cpuid_p()) {
354 /* First of all, decide if this is a 486 or higher */
355 /* It's a 486 if we can modify the AC flag */
356 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
357 c->x86 = 4;
358 else
359 c->x86 = 3;
360 }
362 generic_identify(c);
364 printk(KERN_DEBUG "CPU: After generic identify, caps:");
365 for (i = 0; i < NCAPINTS; i++)
366 printk(" %08lx", c->x86_capability[i]);
367 printk("\n");
369 if (this_cpu->c_identify) {
370 this_cpu->c_identify(c);
372 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
373 for (i = 0; i < NCAPINTS; i++)
374 printk(" %08lx", c->x86_capability[i]);
375 printk("\n");
376 }
378 /*
379 * Vendor-specific initialization. In this section we
380 * canonicalize the feature flags, meaning if there are
381 * features a certain CPU supports which CPUID doesn't
382 * tell us, CPUID claiming incorrect flags, or other bugs,
383 * we handle them here.
384 *
385 * At the end of this section, c->x86_capability better
386 * indicate the features this CPU genuinely supports!
387 */
388 if (this_cpu->c_init)
389 this_cpu->c_init(c);
391 /* Disable the PN if appropriate */
392 squash_the_stupid_serial_number(c);
394 /*
395 * The vendor-specific functions might have changed features. Now
396 * we do "generic changes."
397 */
399 /* TSC disabled? */
400 if ( tsc_disable )
401 clear_bit(X86_FEATURE_TSC, c->x86_capability);
403 /* FXSR disabled? */
404 if (disable_x86_fxsr) {
405 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
406 clear_bit(X86_FEATURE_XMM, c->x86_capability);
407 }
409 if (disable_pse)
410 clear_bit(X86_FEATURE_PSE, c->x86_capability);
412 /* If the model name is still unset, do table lookup. */
413 if ( !c->x86_model_id[0] ) {
414 char *p;
415 p = table_lookup_model(c);
416 if ( p )
417 strcpy(c->x86_model_id, p);
418 else
419 /* Last resort... */
420 sprintf(c->x86_model_id, "%02x/%02x",
421 c->x86_vendor, c->x86_model);
422 }
424 machine_specific_modify_cpu_capabilities(c);
426 /* Now the feature flags better reflect actual CPU features! */
428 printk(KERN_DEBUG "CPU: After all inits, caps:");
429 for (i = 0; i < NCAPINTS; i++)
430 printk(" %08lx", c->x86_capability[i]);
431 printk("\n");
433 /*
434 * On SMP, boot_cpu_data holds the common feature set between
435 * all CPUs; so make sure that we indicate which features are
436 * common between the CPUs. The first time this routine gets
437 * executed, c == &boot_cpu_data.
438 */
439 if ( c != &boot_cpu_data ) {
440 /* AND the already accumulated flags with these */
441 for ( i = 0 ; i < NCAPINTS ; i++ )
442 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
443 }
445 /* Init Machine Check Exception if available. */
446 mcheck_init(c);
448 if (c == &boot_cpu_data)
449 sysenter_setup();
450 enable_sep_cpu();
452 if (c == &boot_cpu_data)
453 mtrr_bp_init();
454 else
455 mtrr_ap_init();
456 }
458 #ifdef CONFIG_X86_HT
459 void __devinit detect_ht(struct cpuinfo_x86 *c)
460 {
461 u32 eax, ebx, ecx, edx;
462 int index_msb, core_bits;
463 int cpu = smp_processor_id();
465 cpuid(1, &eax, &ebx, &ecx, &edx);
467 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
469 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
470 return;
472 smp_num_siblings = (ebx & 0xff0000) >> 16;
474 if (smp_num_siblings == 1) {
475 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
476 } else if (smp_num_siblings > 1 ) {
478 if (smp_num_siblings > NR_CPUS) {
479 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
480 smp_num_siblings = 1;
481 return;
482 }
484 index_msb = get_count_order(smp_num_siblings);
485 phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
487 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
488 phys_proc_id[cpu]);
490 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
492 index_msb = get_count_order(smp_num_siblings) ;
494 core_bits = get_count_order(c->x86_max_cores);
496 cpu_core_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
497 ((1 << core_bits) - 1);
499 if (c->x86_max_cores > 1)
500 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
501 cpu_core_id[cpu]);
502 }
503 }
504 #endif
506 void __devinit print_cpu_info(struct cpuinfo_x86 *c)
507 {
508 char *vendor = NULL;
510 if (c->x86_vendor < X86_VENDOR_NUM)
511 vendor = this_cpu->c_vendor;
512 else if (c->cpuid_level >= 0)
513 vendor = c->x86_vendor_id;
515 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
516 printk("%s ", vendor);
518 if (!c->x86_model_id[0])
519 printk("%d86", c->x86);
520 else
521 printk("%s", c->x86_model_id);
523 if (c->x86_mask || c->cpuid_level >= 0)
524 printk(" stepping %02x\n", c->x86_mask);
525 else
526 printk("\n");
527 }
529 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
531 /* This is hacky. :)
532 * We're emulating future behavior.
533 * In the future, the cpu-specific init functions will be called implicitly
534 * via the magic of initcalls.
535 * They will insert themselves into the cpu_devs structure.
536 * Then, when cpu_init() is called, we can just iterate over that array.
537 */
539 extern int intel_cpu_init(void);
540 extern int cyrix_init_cpu(void);
541 extern int nsc_init_cpu(void);
542 extern int amd_init_cpu(void);
543 extern int centaur_init_cpu(void);
544 extern int transmeta_init_cpu(void);
545 extern int rise_init_cpu(void);
546 extern int nexgen_init_cpu(void);
547 extern int umc_init_cpu(void);
549 void __init early_cpu_init(void)
550 {
551 intel_cpu_init();
552 cyrix_init_cpu();
553 nsc_init_cpu();
554 amd_init_cpu();
555 centaur_init_cpu();
556 transmeta_init_cpu();
557 rise_init_cpu();
558 nexgen_init_cpu();
559 umc_init_cpu();
560 early_cpu_detect();
562 #ifdef CONFIG_DEBUG_PAGEALLOC
563 /* pse is not compatible with on-the-fly unmapping,
564 * disable it even if the cpus claim to support it.
565 */
566 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
567 disable_pse = 1;
568 #endif
569 }
571 void __cpuinit cpu_gdt_init(struct Xgt_desc_struct *gdt_descr)
572 {
573 unsigned long frames[16];
574 unsigned long va;
575 int f;
577 for (va = gdt_descr->address, f = 0;
578 va < gdt_descr->address + gdt_descr->size;
579 va += PAGE_SIZE, f++) {
580 frames[f] = virt_to_mfn(va);
581 make_lowmem_page_readonly(
582 (void *)va, XENFEAT_writable_descriptor_tables);
583 }
584 if (HYPERVISOR_set_gdt(frames, gdt_descr->size / 8))
585 BUG();
586 lgdt_finish();
587 }
589 /*
590 * cpu_init() initializes state that is per-CPU. Some data is already
591 * initialized (naturally) in the bootstrap process, such as the GDT
592 * and IDT. We reload them nevertheless, this function acts as a
593 * 'CPU state barrier', nothing should get across.
594 */
595 void __cpuinit cpu_init(void)
596 {
597 int cpu = smp_processor_id();
598 #ifndef CONFIG_X86_NO_TSS
599 struct tss_struct * t = &per_cpu(init_tss, cpu);
600 #endif
601 struct thread_struct *thread = &current->thread;
603 if (cpu_test_and_set(cpu, cpu_initialized)) {
604 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
605 for (;;) local_irq_enable();
606 }
607 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
609 if (cpu_has_vme || cpu_has_de)
610 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
611 if (tsc_disable && cpu_has_tsc) {
612 printk(KERN_NOTICE "Disabling TSC...\n");
613 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
614 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
615 set_in_cr4(X86_CR4_TSD);
616 }
618 cpu_gdt_init(&cpu_gdt_descr[cpu]);
620 /*
621 * Set up and load the per-CPU TSS and LDT
622 */
623 atomic_inc(&init_mm.mm_count);
624 current->active_mm = &init_mm;
625 if (current->mm)
626 BUG();
627 enter_lazy_tlb(&init_mm, current);
629 load_esp0(t, thread);
631 load_LDT(&init_mm.context);
633 #ifdef CONFIG_DOUBLEFAULT
634 /* Set up doublefault TSS pointer in the GDT */
635 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
636 #endif
638 /* Clear %fs and %gs. */
639 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
641 /* Clear all 6 debug registers: */
642 set_debugreg(0, 0);
643 set_debugreg(0, 1);
644 set_debugreg(0, 2);
645 set_debugreg(0, 3);
646 set_debugreg(0, 6);
647 set_debugreg(0, 7);
649 /*
650 * Force FPU initialization:
651 */
652 current_thread_info()->status = 0;
653 clear_used_math();
654 mxcsr_feature_mask_init();
655 }
657 #ifdef CONFIG_HOTPLUG_CPU
658 void __devinit cpu_uninit(void)
659 {
660 int cpu = raw_smp_processor_id();
661 cpu_clear(cpu, cpu_initialized);
663 /* lazy TLB state */
664 per_cpu(cpu_tlbstate, cpu).state = 0;
665 per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
666 }
667 #endif