ia64/xen-unstable

view xen/arch/x86/hvm/svm/svm.c @ 13915:a00b8d3800a8

[XEN] Snapshot PAE l3es when they are shadowed.
We don't update the shadows so we mustn't look at the guest l3es
or we'll be confused by them if they change.
Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
author Tim Deegan <Tim.Deegan@xensource.com>
date Wed Feb 14 14:46:18 2007 +0000 (2007-02-14)
parents 6daa91dc9247
children d5076a33cbb1
line source
1 /*
2 * svm.c: handling SVM architecture-related VM exits
3 * Copyright (c) 2004, Intel Corporation.
4 * Copyright (c) 2005, AMD Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 *
19 */
21 #include <xen/config.h>
22 #include <xen/init.h>
23 #include <xen/lib.h>
24 #include <xen/trace.h>
25 #include <xen/sched.h>
26 #include <xen/irq.h>
27 #include <xen/softirq.h>
28 #include <xen/hypercall.h>
29 #include <xen/domain_page.h>
30 #include <asm/current.h>
31 #include <asm/io.h>
32 #include <asm/paging.h>
33 #include <asm/p2m.h>
34 #include <asm/regs.h>
35 #include <asm/cpufeature.h>
36 #include <asm/processor.h>
37 #include <asm/types.h>
38 #include <asm/msr.h>
39 #include <asm/spinlock.h>
40 #include <asm/hvm/hvm.h>
41 #include <asm/hvm/support.h>
42 #include <asm/hvm/io.h>
43 #include <asm/hvm/svm/svm.h>
44 #include <asm/hvm/svm/vmcb.h>
45 #include <asm/hvm/svm/emulate.h>
46 #include <asm/hvm/svm/vmmcall.h>
47 #include <asm/hvm/svm/intr.h>
48 #include <asm/x86_emulate.h>
49 #include <public/sched.h>
50 #include <asm/hvm/vpt.h>
52 #define SVM_EXTRA_DEBUG
54 #define set_segment_register(name, value) \
55 __asm__ __volatile__ ( "movw %%ax ,%%" STR(name) "" : : "a" (value) )
57 /* External functions. We should move these to some suitable header file(s) */
59 extern int inst_copy_from_guest(unsigned char *buf, unsigned long guest_eip,
60 int inst_len);
61 extern asmlinkage void do_IRQ(struct cpu_user_regs *);
62 extern void svm_dump_inst(unsigned long eip);
63 extern int svm_dbg_on;
64 void svm_dump_regs(const char *from, struct cpu_user_regs *regs);
66 static int svm_do_vmmcall_reset_to_realmode(struct vcpu *v,
67 struct cpu_user_regs *regs);
69 /* va of hardware host save area */
70 static void *hsa[NR_CPUS] __read_mostly;
72 /* vmcb used for extended host state */
73 static void *root_vmcb[NR_CPUS] __read_mostly;
75 /* physical address of above for host VMSAVE/VMLOAD */
76 u64 root_vmcb_pa[NR_CPUS] __read_mostly;
78 static inline void svm_inject_exception(struct vcpu *v, int trap,
79 int ev, int error_code)
80 {
81 eventinj_t event;
82 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
84 event.bytes = 0;
85 event.fields.v = 1;
86 event.fields.type = EVENTTYPE_EXCEPTION;
87 event.fields.vector = trap;
88 event.fields.ev = ev;
89 event.fields.errorcode = error_code;
91 ASSERT(vmcb->eventinj.fields.v == 0);
93 vmcb->eventinj = event;
94 }
96 static void stop_svm(void)
97 {
98 u32 eax, edx;
99 int cpu = smp_processor_id();
101 /* We turn off the EFER_SVME bit. */
102 rdmsr(MSR_EFER, eax, edx);
103 eax &= ~EFER_SVME;
104 wrmsr(MSR_EFER, eax, edx);
106 /* release the HSA */
107 free_host_save_area(hsa[cpu]);
108 hsa[cpu] = NULL;
109 wrmsr(MSR_K8_VM_HSAVE_PA, 0, 0 );
111 /* free up the root vmcb */
112 free_vmcb(root_vmcb[cpu]);
113 root_vmcb[cpu] = NULL;
114 root_vmcb_pa[cpu] = 0;
115 }
117 static void svm_store_cpu_guest_regs(
118 struct vcpu *v, struct cpu_user_regs *regs, unsigned long *crs)
119 {
120 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
122 if ( regs != NULL )
123 {
124 regs->eip = vmcb->rip;
125 regs->esp = vmcb->rsp;
126 regs->eflags = vmcb->rflags;
127 regs->cs = vmcb->cs.sel;
128 regs->ds = vmcb->ds.sel;
129 regs->es = vmcb->es.sel;
130 regs->ss = vmcb->ss.sel;
131 regs->gs = vmcb->gs.sel;
132 regs->fs = vmcb->fs.sel;
133 }
135 if ( crs != NULL )
136 {
137 /* Returning the guest's regs */
138 crs[0] = v->arch.hvm_svm.cpu_shadow_cr0;
139 crs[2] = v->arch.hvm_svm.cpu_cr2;
140 crs[3] = v->arch.hvm_svm.cpu_cr3;
141 crs[4] = v->arch.hvm_svm.cpu_shadow_cr4;
142 }
143 }
145 static int svm_paging_enabled(struct vcpu *v)
146 {
147 unsigned long cr0;
149 cr0 = v->arch.hvm_svm.cpu_shadow_cr0;
151 return (cr0 & X86_CR0_PE) && (cr0 & X86_CR0_PG);
152 }
154 static int svm_pae_enabled(struct vcpu *v)
155 {
156 unsigned long cr4;
158 if(!svm_paging_enabled(v))
159 return 0;
161 cr4 = v->arch.hvm_svm.cpu_shadow_cr4;
163 return (cr4 & X86_CR4_PAE);
164 }
166 static int svm_long_mode_enabled(struct vcpu *v)
167 {
168 return test_bit(SVM_CPU_STATE_LMA_ENABLED, &v->arch.hvm_svm.cpu_state);
169 }
171 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
172 {
173 u64 msr_content = 0;
174 struct vcpu *v = current;
175 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
177 switch ((u32)regs->ecx)
178 {
179 case MSR_EFER:
180 msr_content = vmcb->efer;
181 msr_content &= ~EFER_SVME;
182 break;
184 #ifdef __x86_64__
185 case MSR_FS_BASE:
186 msr_content = vmcb->fs.base;
187 goto check_long_mode;
189 case MSR_GS_BASE:
190 msr_content = vmcb->gs.base;
191 goto check_long_mode;
193 case MSR_SHADOW_GS_BASE:
194 msr_content = vmcb->kerngsbase;
195 check_long_mode:
196 if ( !svm_long_mode_enabled(v) )
197 {
198 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
199 return 0;
200 }
201 break;
202 #endif
204 case MSR_STAR:
205 msr_content = vmcb->star;
206 break;
208 case MSR_LSTAR:
209 msr_content = vmcb->lstar;
210 break;
212 case MSR_CSTAR:
213 msr_content = vmcb->cstar;
214 break;
216 case MSR_SYSCALL_MASK:
217 msr_content = vmcb->sfmask;
218 break;
219 default:
220 return 0;
221 }
223 HVM_DBG_LOG(DBG_LEVEL_2, "msr_content: %"PRIx64"\n",
224 msr_content);
226 regs->eax = (u32)(msr_content >> 0);
227 regs->edx = (u32)(msr_content >> 32);
228 return 1;
229 }
231 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
232 {
233 u64 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
234 u32 ecx = regs->ecx;
235 struct vcpu *v = current;
236 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
238 HVM_DBG_LOG(DBG_LEVEL_1, "msr %x msr_content %"PRIx64"\n",
239 ecx, msr_content);
241 switch ( ecx )
242 {
243 case MSR_EFER:
244 /* offending reserved bit will cause #GP */
245 if ( msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE) )
246 {
247 gdprintk(XENLOG_WARNING, "Trying to set reserved bit in "
248 "EFER: %"PRIx64"\n", msr_content);
249 goto gp_fault;
250 }
252 #ifdef __x86_64__
253 /* LME: 0 -> 1 */
254 if ( msr_content & EFER_LME &&
255 !test_bit(SVM_CPU_STATE_LME_ENABLED, &v->arch.hvm_svm.cpu_state))
256 {
257 if ( svm_paging_enabled(v) ||
258 !test_bit(SVM_CPU_STATE_PAE_ENABLED,
259 &v->arch.hvm_svm.cpu_state) )
260 {
261 gdprintk(XENLOG_WARNING, "Trying to set LME bit when "
262 "in paging mode or PAE bit is not set\n");
263 goto gp_fault;
264 }
265 set_bit(SVM_CPU_STATE_LME_ENABLED, &v->arch.hvm_svm.cpu_state);
266 }
268 /* We have already recorded that we want LME, so it will be set
269 * next time CR0 gets updated. So we clear that bit and continue.
270 */
271 if ((msr_content ^ vmcb->efer) & EFER_LME)
272 msr_content &= ~EFER_LME;
273 /* No update for LME/LMA since it have no effect */
274 #endif
275 vmcb->efer = msr_content | EFER_SVME;
276 break;
278 #ifdef __x86_64__
279 case MSR_FS_BASE:
280 case MSR_GS_BASE:
281 case MSR_SHADOW_GS_BASE:
282 if ( !svm_long_mode_enabled(v) )
283 goto gp_fault;
285 if ( !is_canonical_address(msr_content) )
286 goto uncanonical_address;
288 if ( ecx == MSR_FS_BASE )
289 vmcb->fs.base = msr_content;
290 else if ( ecx == MSR_GS_BASE )
291 vmcb->gs.base = msr_content;
292 else
293 vmcb->kerngsbase = msr_content;
294 break;
295 #endif
297 case MSR_STAR:
298 vmcb->star = msr_content;
299 break;
301 case MSR_LSTAR:
302 case MSR_CSTAR:
303 if ( !is_canonical_address(msr_content) )
304 goto uncanonical_address;
306 if ( ecx == MSR_LSTAR )
307 vmcb->lstar = msr_content;
308 else
309 vmcb->cstar = msr_content;
310 break;
312 case MSR_SYSCALL_MASK:
313 vmcb->sfmask = msr_content;
314 break;
316 default:
317 return 0;
318 }
320 return 1;
322 uncanonical_address:
323 HVM_DBG_LOG(DBG_LEVEL_1, "Not cano address of msr write %x\n", ecx);
324 gp_fault:
325 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
326 return 0;
327 }
330 #define loaddebug(_v,_reg) \
331 __asm__ __volatile__ ("mov %0,%%db" #_reg : : "r" ((_v)->debugreg[_reg]))
332 #define savedebug(_v,_reg) \
333 __asm__ __volatile__ ("mov %%db" #_reg ",%0" : : "r" ((_v)->debugreg[_reg]))
335 static inline void svm_save_dr(struct vcpu *v)
336 {
337 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
339 if ( !v->arch.hvm_vcpu.flag_dr_dirty )
340 return;
342 /* Clear the DR dirty flag and re-enable intercepts for DR accesses. */
343 v->arch.hvm_vcpu.flag_dr_dirty = 0;
344 v->arch.hvm_svm.vmcb->dr_intercepts = DR_INTERCEPT_ALL_WRITES;
346 savedebug(&v->arch.guest_context, 0);
347 savedebug(&v->arch.guest_context, 1);
348 savedebug(&v->arch.guest_context, 2);
349 savedebug(&v->arch.guest_context, 3);
350 v->arch.guest_context.debugreg[6] = vmcb->dr6;
351 v->arch.guest_context.debugreg[7] = vmcb->dr7;
352 }
355 static inline void __restore_debug_registers(struct vcpu *v)
356 {
357 loaddebug(&v->arch.guest_context, 0);
358 loaddebug(&v->arch.guest_context, 1);
359 loaddebug(&v->arch.guest_context, 2);
360 loaddebug(&v->arch.guest_context, 3);
361 /* DR6 and DR7 are loaded from the VMCB. */
362 }
365 int svm_vmcs_save(struct vcpu *v, struct hvm_hw_cpu *c)
366 {
367 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
369 c->eip = vmcb->rip;
371 #ifdef HVM_DEBUG_SUSPEND
372 printk("%s: eip=0x%"PRIx64".\n",
373 __func__,
374 inst_len, c->eip);
375 #endif
377 c->esp = vmcb->rsp;
378 c->eflags = vmcb->rflags;
380 c->cr0 = v->arch.hvm_svm.cpu_shadow_cr0;
381 c->cr3 = v->arch.hvm_svm.cpu_cr3;
382 c->cr4 = v->arch.hvm_svm.cpu_shadow_cr4;
384 #ifdef HVM_DEBUG_SUSPEND
385 printk("%s: cr3=0x%"PRIx64", cr0=0x%"PRIx64", cr4=0x%"PRIx64".\n",
386 __func__,
387 c->cr3,
388 c->cr0,
389 c->cr4);
390 #endif
392 c->idtr_limit = vmcb->idtr.limit;
393 c->idtr_base = vmcb->idtr.base;
395 c->gdtr_limit = vmcb->gdtr.limit;
396 c->gdtr_base = vmcb->gdtr.base;
398 c->cs_sel = vmcb->cs.sel;
399 c->cs_limit = vmcb->cs.limit;
400 c->cs_base = vmcb->cs.base;
401 c->cs_arbytes = vmcb->cs.attr.bytes;
403 c->ds_sel = vmcb->ds.sel;
404 c->ds_limit = vmcb->ds.limit;
405 c->ds_base = vmcb->ds.base;
406 c->ds_arbytes = vmcb->ds.attr.bytes;
408 c->es_sel = vmcb->es.sel;
409 c->es_limit = vmcb->es.limit;
410 c->es_base = vmcb->es.base;
411 c->es_arbytes = vmcb->es.attr.bytes;
413 c->ss_sel = vmcb->ss.sel;
414 c->ss_limit = vmcb->ss.limit;
415 c->ss_base = vmcb->ss.base;
416 c->ss_arbytes = vmcb->ss.attr.bytes;
418 c->fs_sel = vmcb->fs.sel;
419 c->fs_limit = vmcb->fs.limit;
420 c->fs_base = vmcb->fs.base;
421 c->fs_arbytes = vmcb->fs.attr.bytes;
423 c->gs_sel = vmcb->gs.sel;
424 c->gs_limit = vmcb->gs.limit;
425 c->gs_base = vmcb->gs.base;
426 c->gs_arbytes = vmcb->gs.attr.bytes;
428 c->tr_sel = vmcb->tr.sel;
429 c->tr_limit = vmcb->tr.limit;
430 c->tr_base = vmcb->tr.base;
431 c->tr_arbytes = vmcb->tr.attr.bytes;
433 c->ldtr_sel = vmcb->ldtr.sel;
434 c->ldtr_limit = vmcb->ldtr.limit;
435 c->ldtr_base = vmcb->ldtr.base;
436 c->ldtr_arbytes = vmcb->ldtr.attr.bytes;
438 c->sysenter_cs = vmcb->sysenter_cs;
439 c->sysenter_esp = vmcb->sysenter_esp;
440 c->sysenter_eip = vmcb->sysenter_eip;
442 return 1;
443 }
446 int svm_vmcb_restore(struct vcpu *v, struct hvm_hw_cpu *c)
447 {
448 unsigned long mfn, old_base_mfn;
449 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
451 vmcb->rip = c->eip;
452 vmcb->rsp = c->esp;
453 vmcb->rflags = c->eflags;
455 v->arch.hvm_svm.cpu_shadow_cr0 = c->cr0;
457 #ifdef HVM_DEBUG_SUSPEND
458 printk("%s: cr3=0x%"PRIx64", cr0=0x%"PRIx64", cr4=0x%"PRIx64".\n",
459 __func__,
460 c->cr3,
461 c->cr0,
462 c->cr4);
463 #endif
465 if (!svm_paging_enabled(v)) {
466 printk("%s: paging not enabled.", __func__);
467 goto skip_cr3;
468 }
470 if (c->cr3 == v->arch.hvm_svm.cpu_cr3) {
471 /*
472 * This is simple TLB flush, implying the guest has
473 * removed some translation or changed page attributes.
474 * We simply invalidate the shadow.
475 */
476 mfn = gmfn_to_mfn(v->domain, c->cr3 >> PAGE_SHIFT);
477 if (mfn != pagetable_get_pfn(v->arch.guest_table)) {
478 goto bad_cr3;
479 }
480 } else {
481 /*
482 * If different, make a shadow. Check if the PDBR is valid
483 * first.
484 */
485 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 c->cr3 = %"PRIx64"", c->cr3);
486 /* current!=vcpu as not called by arch_vmx_do_launch */
487 mfn = gmfn_to_mfn(v->domain, c->cr3 >> PAGE_SHIFT);
488 if( !mfn_valid(mfn) || !get_page(mfn_to_page(mfn), v->domain)) {
489 goto bad_cr3;
490 }
491 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
492 v->arch.guest_table = pagetable_from_pfn(mfn);
493 if (old_base_mfn)
494 put_page(mfn_to_page(old_base_mfn));
495 v->arch.hvm_svm.cpu_cr3 = c->cr3;
496 }
498 skip_cr3:
499 #if defined(__x86_64__) && 0
500 if (vmx_long_mode_enabled(v)) {
501 unsigned long vm_entry_value;
502 vm_entry_value = __vmread(VM_ENTRY_CONTROLS);
503 vm_entry_value |= VM_ENTRY_IA32E_MODE;
504 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
505 }
506 #endif
508 vmcb->cr4 = c->cr4 | SVM_CR4_HOST_MASK;
509 v->arch.hvm_svm.cpu_shadow_cr4 = c->cr4;
511 vmcb->idtr.limit = c->idtr_limit;
512 vmcb->idtr.base = c->idtr_base;
514 vmcb->gdtr.limit = c->gdtr_limit;
515 vmcb->gdtr.base = c->gdtr_base;
517 vmcb->cs.sel = c->cs_sel;
518 vmcb->cs.limit = c->cs_limit;
519 vmcb->cs.base = c->cs_base;
520 vmcb->cs.attr.bytes = c->cs_arbytes;
522 vmcb->ds.sel = c->ds_sel;
523 vmcb->ds.limit = c->ds_limit;
524 vmcb->ds.base = c->ds_base;
525 vmcb->ds.attr.bytes = c->ds_arbytes;
527 vmcb->es.sel = c->es_sel;
528 vmcb->es.limit = c->es_limit;
529 vmcb->es.base = c->es_base;
530 vmcb->es.attr.bytes = c->es_arbytes;
532 vmcb->ss.sel = c->ss_sel;
533 vmcb->ss.limit = c->ss_limit;
534 vmcb->ss.base = c->ss_base;
535 vmcb->ss.attr.bytes = c->ss_arbytes;
537 vmcb->fs.sel = c->fs_sel;
538 vmcb->fs.limit = c->fs_limit;
539 vmcb->fs.base = c->fs_base;
540 vmcb->fs.attr.bytes = c->fs_arbytes;
542 vmcb->gs.sel = c->gs_sel;
543 vmcb->gs.limit = c->gs_limit;
544 vmcb->gs.base = c->gs_base;
545 vmcb->gs.attr.bytes = c->gs_arbytes;
547 vmcb->tr.sel = c->tr_sel;
548 vmcb->tr.limit = c->tr_limit;
549 vmcb->tr.base = c->tr_base;
550 vmcb->tr.attr.bytes = c->tr_arbytes;
552 vmcb->ldtr.sel = c->ldtr_sel;
553 vmcb->ldtr.limit = c->ldtr_limit;
554 vmcb->ldtr.base = c->ldtr_base;
555 vmcb->ldtr.attr.bytes = c->ldtr_arbytes;
557 vmcb->sysenter_cs = c->sysenter_cs;
558 vmcb->sysenter_esp = c->sysenter_esp;
559 vmcb->sysenter_eip = c->sysenter_eip;
561 paging_update_paging_modes(v);
562 return 0;
564 bad_cr3:
565 gdprintk(XENLOG_ERR, "Invalid CR3 value=0x%"PRIx64"", c->cr3);
566 return -EINVAL;
567 }
570 void svm_save_cpu_state(struct vcpu *v, struct hvm_hw_cpu *data)
571 {
572 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
574 data->shadow_gs = vmcb->kerngsbase;
575 /* MSR_LSTAR, MSR_STAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_EFER */
576 data->msr_items[0] = vmcb->lstar;
577 data->msr_items[1] = vmcb->star;
578 data->msr_items[2] = vmcb->cstar;
579 data->msr_items[3] = vmcb->sfmask;
580 data->msr_items[4] = vmcb->efer;
582 data->tsc = hvm_get_guest_time(v);
584 // dump_msr_state(guest_state);
585 }
588 void svm_load_cpu_state(struct vcpu *v, struct hvm_hw_cpu *data)
589 {
590 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
592 vmcb->kerngsbase = data->shadow_gs;
593 /* MSR_LSTAR, MSR_STAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_EFER */
594 vmcb->lstar = data->msr_items[0];
595 vmcb->star = data->msr_items[1];
596 vmcb->cstar = data->msr_items[2];
597 vmcb->sfmask = data->msr_items[3];
598 vmcb->efer = data->msr_items[4];
600 hvm_set_guest_time(v, data->tsc);
602 // dump_msr_state(guest_state);
603 }
605 void svm_save_vmcb_ctxt(struct vcpu *v, struct hvm_hw_cpu *ctxt)
606 {
607 svm_save_cpu_state(v, ctxt);
608 svm_vmcs_save(v, ctxt);
609 }
611 int svm_load_vmcb_ctxt(struct vcpu *v, struct hvm_hw_cpu *ctxt)
612 {
613 svm_load_cpu_state(v, ctxt);
614 if (svm_vmcb_restore(v, ctxt)) {
615 printk("svm_vmcb restore failed!\n");
616 domain_crash(v->domain);
617 return -EINVAL;
618 }
620 return 0;
621 }
624 static inline void svm_restore_dr(struct vcpu *v)
625 {
626 if ( unlikely(v->arch.guest_context.debugreg[7] & 0xFF) )
627 __restore_debug_registers(v);
628 }
631 static int svm_realmode(struct vcpu *v)
632 {
633 unsigned long cr0 = v->arch.hvm_svm.cpu_shadow_cr0;
634 unsigned long eflags = v->arch.hvm_svm.vmcb->rflags;
636 return (eflags & X86_EFLAGS_VM) || !(cr0 & X86_CR0_PE);
637 }
639 static int svm_guest_x86_mode(struct vcpu *v)
640 {
641 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
643 if ( (vmcb->efer & EFER_LMA) && vmcb->cs.attr.fields.l )
644 return 8;
646 if ( svm_realmode(v) )
647 return 2;
649 return (vmcb->cs.attr.fields.db ? 4 : 2);
650 }
652 void svm_update_host_cr3(struct vcpu *v)
653 {
654 /* SVM doesn't have a HOST_CR3 equivalent to update. */
655 }
657 void svm_update_guest_cr3(struct vcpu *v)
658 {
659 v->arch.hvm_svm.vmcb->cr3 = v->arch.hvm_vcpu.hw_cr3;
660 }
662 static void svm_update_vtpr(struct vcpu *v, unsigned long value)
663 {
664 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
666 vmcb->vintr.fields.tpr = value & 0x0f;
667 }
669 unsigned long svm_get_ctrl_reg(struct vcpu *v, unsigned int num)
670 {
671 switch ( num )
672 {
673 case 0:
674 return v->arch.hvm_svm.cpu_shadow_cr0;
675 case 2:
676 return v->arch.hvm_svm.cpu_cr2;
677 case 3:
678 return v->arch.hvm_svm.cpu_cr3;
679 case 4:
680 return v->arch.hvm_svm.cpu_shadow_cr4;
681 default:
682 BUG();
683 }
684 return 0; /* dummy */
685 }
687 static unsigned long svm_get_segment_base(struct vcpu *v, enum x86_segment seg)
688 {
689 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
690 int long_mode = 0;
692 #ifdef __x86_64__
693 long_mode = vmcb->cs.attr.fields.l && (vmcb->efer & EFER_LMA);
694 #endif
695 switch ( seg )
696 {
697 case x86_seg_cs: return long_mode ? 0 : vmcb->cs.base;
698 case x86_seg_ds: return long_mode ? 0 : vmcb->ds.base;
699 case x86_seg_es: return long_mode ? 0 : vmcb->es.base;
700 case x86_seg_fs: return vmcb->fs.base;
701 case x86_seg_gs: return vmcb->gs.base;
702 case x86_seg_ss: return long_mode ? 0 : vmcb->ss.base;
703 case x86_seg_tr: return vmcb->tr.base;
704 case x86_seg_gdtr: return vmcb->gdtr.base;
705 case x86_seg_idtr: return vmcb->idtr.base;
706 case x86_seg_ldtr: return vmcb->ldtr.base;
707 }
708 BUG();
709 return 0;
710 }
712 static void svm_get_segment_register(struct vcpu *v, enum x86_segment seg,
713 struct segment_register *reg)
714 {
715 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
716 switch ( seg )
717 {
718 case x86_seg_cs: memcpy(reg, &vmcb->cs, sizeof(*reg)); break;
719 case x86_seg_ds: memcpy(reg, &vmcb->ds, sizeof(*reg)); break;
720 case x86_seg_es: memcpy(reg, &vmcb->es, sizeof(*reg)); break;
721 case x86_seg_fs: memcpy(reg, &vmcb->fs, sizeof(*reg)); break;
722 case x86_seg_gs: memcpy(reg, &vmcb->gs, sizeof(*reg)); break;
723 case x86_seg_ss: memcpy(reg, &vmcb->ss, sizeof(*reg)); break;
724 case x86_seg_tr: memcpy(reg, &vmcb->tr, sizeof(*reg)); break;
725 case x86_seg_gdtr: memcpy(reg, &vmcb->gdtr, sizeof(*reg)); break;
726 case x86_seg_idtr: memcpy(reg, &vmcb->idtr, sizeof(*reg)); break;
727 case x86_seg_ldtr: memcpy(reg, &vmcb->ldtr, sizeof(*reg)); break;
728 default: BUG();
729 }
730 }
732 /* Make sure that xen intercepts any FP accesses from current */
733 static void svm_stts(struct vcpu *v)
734 {
735 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
737 /*
738 * If the guest does not have TS enabled then we must cause and handle an
739 * exception on first use of the FPU. If the guest *does* have TS enabled
740 * then this is not necessary: no FPU activity can occur until the guest
741 * clears CR0.TS, and we will initialise the FPU when that happens.
742 */
743 if ( !(v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_TS) )
744 {
745 v->arch.hvm_svm.vmcb->exception_intercepts |= EXCEPTION_BITMAP_NM;
746 vmcb->cr0 |= X86_CR0_TS;
747 }
748 }
751 static void svm_set_tsc_offset(struct vcpu *v, u64 offset)
752 {
753 v->arch.hvm_svm.vmcb->tsc_offset = offset;
754 }
757 static void svm_init_ap_context(
758 struct vcpu_guest_context *ctxt, int vcpuid, int trampoline_vector)
759 {
760 memset(ctxt, 0, sizeof(*ctxt));
762 /*
763 * We execute the trampoline code in real mode. The trampoline vector
764 * passed to us is page alligned and is the physicall frame number for
765 * the code. We will execute this code in real mode.
766 */
767 ctxt->user_regs.eip = 0x0;
768 ctxt->user_regs.cs = (trampoline_vector << 8);
769 }
771 static void svm_init_hypercall_page(struct domain *d, void *hypercall_page)
772 {
773 char *p;
774 int i;
776 memset(hypercall_page, 0, PAGE_SIZE);
778 for ( i = 0; i < (PAGE_SIZE / 32); i++ )
779 {
780 p = (char *)(hypercall_page + (i * 32));
781 *(u8 *)(p + 0) = 0xb8; /* mov imm32, %eax */
782 *(u32 *)(p + 1) = i;
783 *(u8 *)(p + 5) = 0x0f; /* vmmcall */
784 *(u8 *)(p + 6) = 0x01;
785 *(u8 *)(p + 7) = 0xd9;
786 *(u8 *)(p + 8) = 0xc3; /* ret */
787 }
789 /* Don't support HYPERVISOR_iret at the moment */
790 *(u16 *)(hypercall_page + (__HYPERVISOR_iret * 32)) = 0x0b0f; /* ud2 */
791 }
794 int svm_dbg_on = 0;
796 static inline int svm_do_debugout(unsigned long exit_code)
797 {
798 int i;
800 static unsigned long counter = 0;
801 static unsigned long works[] =
802 {
803 VMEXIT_IOIO,
804 VMEXIT_HLT,
805 VMEXIT_CPUID,
806 VMEXIT_DR0_READ,
807 VMEXIT_DR1_READ,
808 VMEXIT_DR2_READ,
809 VMEXIT_DR3_READ,
810 VMEXIT_DR6_READ,
811 VMEXIT_DR7_READ,
812 VMEXIT_DR0_WRITE,
813 VMEXIT_DR1_WRITE,
814 VMEXIT_DR2_WRITE,
815 VMEXIT_DR3_WRITE,
816 VMEXIT_CR0_READ,
817 VMEXIT_CR0_WRITE,
818 VMEXIT_CR3_READ,
819 VMEXIT_CR4_READ,
820 VMEXIT_MSR,
821 VMEXIT_CR0_WRITE,
822 VMEXIT_CR3_WRITE,
823 VMEXIT_CR4_WRITE,
824 VMEXIT_EXCEPTION_PF,
825 VMEXIT_INTR,
826 VMEXIT_INVLPG,
827 VMEXIT_EXCEPTION_NM
828 };
831 #if 0
832 if (svm_dbg_on && exit_code != 0x7B)
833 return 1;
834 #endif
836 counter++;
838 #if 0
839 if ((exit_code == 0x4E
840 || exit_code == VMEXIT_CR0_READ
841 || exit_code == VMEXIT_CR0_WRITE)
842 && counter < 200000)
843 return 0;
845 if ((exit_code == 0x4E) && counter < 500000)
846 return 0;
847 #endif
849 for (i = 0; i < sizeof(works) / sizeof(works[0]); i++)
850 if (exit_code == works[i])
851 return 0;
853 return 1;
854 }
856 static void save_svm_cpu_user_regs(struct vcpu *v, struct cpu_user_regs *ctxt)
857 {
858 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
860 ASSERT(vmcb);
862 ctxt->eax = vmcb->rax;
863 ctxt->ss = vmcb->ss.sel;
864 ctxt->esp = vmcb->rsp;
865 ctxt->eflags = vmcb->rflags;
866 ctxt->cs = vmcb->cs.sel;
867 ctxt->eip = vmcb->rip;
869 ctxt->gs = vmcb->gs.sel;
870 ctxt->fs = vmcb->fs.sel;
871 ctxt->es = vmcb->es.sel;
872 ctxt->ds = vmcb->ds.sel;
873 }
875 static void svm_store_cpu_user_regs(struct cpu_user_regs *regs, struct vcpu *v)
876 {
877 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
879 regs->eip = vmcb->rip;
880 regs->esp = vmcb->rsp;
881 regs->eflags = vmcb->rflags;
882 regs->cs = vmcb->cs.sel;
883 regs->ds = vmcb->ds.sel;
884 regs->es = vmcb->es.sel;
885 regs->ss = vmcb->ss.sel;
886 }
888 /* XXX Use svm_load_cpu_guest_regs instead */
889 static void svm_load_cpu_user_regs(struct vcpu *v, struct cpu_user_regs *regs)
890 {
891 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
892 u32 *intercepts = &v->arch.hvm_svm.vmcb->exception_intercepts;
894 /* Write the guest register value into VMCB */
895 vmcb->rax = regs->eax;
896 vmcb->ss.sel = regs->ss;
897 vmcb->rsp = regs->esp;
898 vmcb->rflags = regs->eflags | 2UL;
899 vmcb->cs.sel = regs->cs;
900 vmcb->rip = regs->eip;
901 if (regs->eflags & EF_TF)
902 *intercepts |= EXCEPTION_BITMAP_DB;
903 else
904 *intercepts &= ~EXCEPTION_BITMAP_DB;
905 }
907 static void svm_load_cpu_guest_regs(
908 struct vcpu *v, struct cpu_user_regs *regs)
909 {
910 svm_load_cpu_user_regs(v, regs);
911 }
913 static void arch_svm_do_launch(struct vcpu *v)
914 {
915 svm_do_launch(v);
917 if ( v->vcpu_id != 0 )
918 {
919 cpu_user_regs_t *regs = &current->arch.guest_context.user_regs;
920 u16 cs_sel = regs->cs;
921 /*
922 * This is the launch of an AP; set state so that we begin executing
923 * the trampoline code in real-mode.
924 */
925 svm_do_vmmcall_reset_to_realmode(v, regs);
926 /* Adjust the state to execute the trampoline code.*/
927 v->arch.hvm_svm.vmcb->rip = 0;
928 v->arch.hvm_svm.vmcb->cs.sel= cs_sel;
929 v->arch.hvm_svm.vmcb->cs.base = (cs_sel << 4);
930 }
932 reset_stack_and_jump(svm_asm_do_launch);
933 }
935 static void svm_ctxt_switch_from(struct vcpu *v)
936 {
937 svm_save_dr(v);
938 }
940 static void svm_ctxt_switch_to(struct vcpu *v)
941 {
942 #ifdef __x86_64__
943 /*
944 * This is required, because VMRUN does consistency check
945 * and some of the DOM0 selectors are pointing to
946 * invalid GDT locations, and cause AMD processors
947 * to shutdown.
948 */
949 set_segment_register(ds, 0);
950 set_segment_register(es, 0);
951 set_segment_register(ss, 0);
952 #endif
953 svm_restore_dr(v);
954 }
956 static int svm_vcpu_initialise(struct vcpu *v)
957 {
958 int rc;
960 v->arch.schedule_tail = arch_svm_do_launch;
961 v->arch.ctxt_switch_from = svm_ctxt_switch_from;
962 v->arch.ctxt_switch_to = svm_ctxt_switch_to;
964 v->arch.hvm_svm.saved_irq_vector = -1;
966 if ( (rc = svm_create_vmcb(v)) != 0 )
967 {
968 dprintk(XENLOG_WARNING,
969 "Failed to create VMCB for vcpu %d: err=%d.\n",
970 v->vcpu_id, rc);
971 return rc;
972 }
974 return 0;
975 }
977 static void svm_vcpu_destroy(struct vcpu *v)
978 {
979 svm_destroy_vmcb(v);
980 }
982 static void svm_hvm_inject_exception(
983 unsigned int trapnr, int errcode, unsigned long cr2)
984 {
985 struct vcpu *v = current;
986 svm_inject_exception(v, trapnr, (errcode != -1), errcode);
987 if ( trapnr == TRAP_page_fault )
988 v->arch.hvm_svm.vmcb->cr2 = v->arch.hvm_svm.cpu_cr2 = cr2;
989 }
991 int start_svm(void)
992 {
993 u32 eax, ecx, edx;
994 u32 phys_hsa_lo, phys_hsa_hi;
995 u64 phys_hsa;
996 int cpu = smp_processor_id();
998 /* Xen does not fill x86_capability words except 0. */
999 ecx = cpuid_ecx(0x80000001);
1000 boot_cpu_data.x86_capability[5] = ecx;
1002 if (!(test_bit(X86_FEATURE_SVME, &boot_cpu_data.x86_capability)))
1003 return 0;
1005 /* check whether SVM feature is disabled in BIOS */
1006 rdmsr(MSR_K8_VM_CR, eax, edx);
1007 if ( eax & K8_VMCR_SVME_DISABLE )
1009 printk("AMD SVM Extension is disabled in BIOS.\n");
1010 return 0;
1013 if (!(hsa[cpu] = alloc_host_save_area()))
1014 return 0;
1016 rdmsr(MSR_EFER, eax, edx);
1017 eax |= EFER_SVME;
1018 wrmsr(MSR_EFER, eax, edx);
1019 printk("AMD SVM Extension is enabled for cpu %d.\n", cpu );
1021 /* Initialize the HSA for this core */
1022 phys_hsa = (u64) virt_to_maddr(hsa[cpu]);
1023 phys_hsa_lo = (u32) phys_hsa;
1024 phys_hsa_hi = (u32) (phys_hsa >> 32);
1025 wrmsr(MSR_K8_VM_HSAVE_PA, phys_hsa_lo, phys_hsa_hi);
1027 if (!(root_vmcb[cpu] = alloc_vmcb()))
1028 return 0;
1029 root_vmcb_pa[cpu] = virt_to_maddr(root_vmcb[cpu]);
1031 if (cpu == 0)
1032 setup_vmcb_dump();
1034 /* Setup HVM interfaces */
1035 hvm_funcs.disable = stop_svm;
1037 hvm_funcs.vcpu_initialise = svm_vcpu_initialise;
1038 hvm_funcs.vcpu_destroy = svm_vcpu_destroy;
1040 hvm_funcs.store_cpu_guest_regs = svm_store_cpu_guest_regs;
1041 hvm_funcs.load_cpu_guest_regs = svm_load_cpu_guest_regs;
1043 hvm_funcs.save_cpu_ctxt = svm_save_vmcb_ctxt;
1044 hvm_funcs.load_cpu_ctxt = svm_load_vmcb_ctxt;
1046 hvm_funcs.paging_enabled = svm_paging_enabled;
1047 hvm_funcs.long_mode_enabled = svm_long_mode_enabled;
1048 hvm_funcs.pae_enabled = svm_pae_enabled;
1049 hvm_funcs.guest_x86_mode = svm_guest_x86_mode;
1050 hvm_funcs.get_guest_ctrl_reg = svm_get_ctrl_reg;
1051 hvm_funcs.get_segment_base = svm_get_segment_base;
1052 hvm_funcs.get_segment_register = svm_get_segment_register;
1054 hvm_funcs.update_host_cr3 = svm_update_host_cr3;
1055 hvm_funcs.update_guest_cr3 = svm_update_guest_cr3;
1057 hvm_funcs.update_vtpr = svm_update_vtpr;
1059 hvm_funcs.stts = svm_stts;
1060 hvm_funcs.set_tsc_offset = svm_set_tsc_offset;
1062 hvm_funcs.inject_exception = svm_hvm_inject_exception;
1064 hvm_funcs.init_ap_context = svm_init_ap_context;
1065 hvm_funcs.init_hypercall_page = svm_init_hypercall_page;
1067 hvm_enable();
1069 return 1;
1072 void arch_svm_do_resume(struct vcpu *v)
1074 /* pinning VCPU to a different core? */
1075 if ( v->arch.hvm_svm.launch_core == smp_processor_id()) {
1076 hvm_do_resume( v );
1077 reset_stack_and_jump( svm_asm_do_resume );
1079 else {
1080 if (svm_dbg_on)
1081 printk("VCPU core pinned: %d to %d\n",
1082 v->arch.hvm_svm.launch_core, smp_processor_id() );
1083 v->arch.hvm_svm.launch_core = smp_processor_id();
1084 hvm_migrate_timers( v );
1085 hvm_do_resume( v );
1086 reset_stack_and_jump( svm_asm_do_resume );
1090 static int svm_do_page_fault(unsigned long va, struct cpu_user_regs *regs)
1092 HVM_DBG_LOG(DBG_LEVEL_VMMU,
1093 "svm_do_page_fault = 0x%lx, eip = %lx, error_code = %lx",
1094 va, (unsigned long)current->arch.hvm_svm.vmcb->rip,
1095 (unsigned long)regs->error_code);
1096 return paging_fault(va, regs);
1100 static void svm_do_no_device_fault(struct vmcb_struct *vmcb)
1102 struct vcpu *v = current;
1104 setup_fpu(v);
1105 vmcb->exception_intercepts &= ~EXCEPTION_BITMAP_NM;
1107 if ( !(v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_TS) )
1108 vmcb->cr0 &= ~X86_CR0_TS;
1112 static void svm_do_general_protection_fault(struct vcpu *v,
1113 struct cpu_user_regs *regs)
1115 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1116 unsigned long eip, error_code;
1118 ASSERT(vmcb);
1120 eip = vmcb->rip;
1121 error_code = vmcb->exitinfo1;
1123 if (vmcb->idtr.limit == 0) {
1124 printk("Huh? We got a GP Fault with an invalid IDTR!\n");
1125 svm_dump_vmcb(__func__, vmcb);
1126 svm_dump_regs(__func__, regs);
1127 svm_dump_inst(svm_rip2pointer(vmcb));
1128 domain_crash(v->domain);
1129 return;
1132 HVM_DBG_LOG(DBG_LEVEL_1,
1133 "svm_general_protection_fault: eip = %lx, erro_code = %lx",
1134 eip, error_code);
1136 HVM_DBG_LOG(DBG_LEVEL_1,
1137 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
1138 (unsigned long)regs->eax, (unsigned long)regs->ebx,
1139 (unsigned long)regs->ecx, (unsigned long)regs->edx,
1140 (unsigned long)regs->esi, (unsigned long)regs->edi);
1142 /* Reflect it back into the guest */
1143 svm_inject_exception(v, TRAP_gp_fault, 1, error_code);
1146 /* Reserved bits ECX: [31:14], [12:4], [2:1]*/
1147 #define SVM_VCPU_CPUID_L1_ECX_RESERVED 0xffffdff6
1148 /* Reserved bits EDX: [31:29], [27], [22:20], [18], [10] */
1149 #define SVM_VCPU_CPUID_L1_EDX_RESERVED 0xe8740400
1151 static void svm_vmexit_do_cpuid(struct vmcb_struct *vmcb,
1152 struct cpu_user_regs *regs)
1154 unsigned long input = regs->eax;
1155 unsigned int eax, ebx, ecx, edx;
1156 struct vcpu *v = current;
1157 int inst_len;
1159 ASSERT(vmcb);
1161 hvm_cpuid(input, &eax, &ebx, &ecx, &edx);
1163 if ( input == 0x00000001 )
1165 /* Clear out reserved bits. */
1166 ecx &= ~SVM_VCPU_CPUID_L1_ECX_RESERVED;
1167 edx &= ~SVM_VCPU_CPUID_L1_EDX_RESERVED;
1169 /* Guest should only see one logical processor.
1170 * See details on page 23 of AMD CPUID Specification.
1171 */
1172 clear_bit(X86_FEATURE_HT & 31, &edx); /* clear the hyperthread bit */
1173 ebx &= 0xFF00FFFF; /* clear the logical processor count when HTT=0 */
1174 ebx |= 0x00010000; /* set to 1 just for precaution */
1176 else if ( input == 0x80000001 )
1178 if ( vlapic_hw_disabled(vcpu_vlapic(v)) )
1179 clear_bit(X86_FEATURE_APIC & 31, &edx);
1181 #if CONFIG_PAGING_LEVELS >= 3
1182 if ( !v->domain->arch.hvm_domain.params[HVM_PARAM_PAE_ENABLED] )
1183 #endif
1184 clear_bit(X86_FEATURE_PAE & 31, &edx);
1186 clear_bit(X86_FEATURE_PSE36 & 31, &edx);
1188 /* Clear the Cmp_Legacy bit
1189 * This bit is supposed to be zero when HTT = 0.
1190 * See details on page 23 of AMD CPUID Specification.
1191 */
1192 clear_bit(X86_FEATURE_CMP_LEGACY & 31, &ecx);
1194 /* Make SVM feature invisible to the guest. */
1195 clear_bit(X86_FEATURE_SVME & 31, &ecx);
1197 /* So far, we do not support 3DNow for the guest. */
1198 clear_bit(X86_FEATURE_3DNOW & 31, &edx);
1199 clear_bit(X86_FEATURE_3DNOWEXT & 31, &edx);
1200 /* no FFXSR instructions feature. */
1201 clear_bit(X86_FEATURE_FFXSR & 31, &edx);
1203 else if ( input == 0x80000007 || input == 0x8000000A )
1205 /* Mask out features of power management and SVM extension. */
1206 eax = ebx = ecx = edx = 0;
1208 else if ( input == 0x80000008 )
1210 /* Make sure Number of CPU core is 1 when HTT=0 */
1211 ecx &= 0xFFFFFF00;
1214 regs->eax = (unsigned long)eax;
1215 regs->ebx = (unsigned long)ebx;
1216 regs->ecx = (unsigned long)ecx;
1217 regs->edx = (unsigned long)edx;
1219 inst_len = __get_instruction_length(vmcb, INSTR_CPUID, NULL);
1220 ASSERT(inst_len > 0);
1221 __update_guest_eip(vmcb, inst_len);
1224 static inline unsigned long *get_reg_p(unsigned int gpreg,
1225 struct cpu_user_regs *regs, struct vmcb_struct *vmcb)
1227 unsigned long *reg_p = NULL;
1228 switch (gpreg)
1230 case SVM_REG_EAX:
1231 reg_p = (unsigned long *)&regs->eax;
1232 break;
1233 case SVM_REG_EBX:
1234 reg_p = (unsigned long *)&regs->ebx;
1235 break;
1236 case SVM_REG_ECX:
1237 reg_p = (unsigned long *)&regs->ecx;
1238 break;
1239 case SVM_REG_EDX:
1240 reg_p = (unsigned long *)&regs->edx;
1241 break;
1242 case SVM_REG_EDI:
1243 reg_p = (unsigned long *)&regs->edi;
1244 break;
1245 case SVM_REG_ESI:
1246 reg_p = (unsigned long *)&regs->esi;
1247 break;
1248 case SVM_REG_EBP:
1249 reg_p = (unsigned long *)&regs->ebp;
1250 break;
1251 case SVM_REG_ESP:
1252 reg_p = (unsigned long *)&vmcb->rsp;
1253 break;
1254 #ifdef __x86_64__
1255 case SVM_REG_R8:
1256 reg_p = (unsigned long *)&regs->r8;
1257 break;
1258 case SVM_REG_R9:
1259 reg_p = (unsigned long *)&regs->r9;
1260 break;
1261 case SVM_REG_R10:
1262 reg_p = (unsigned long *)&regs->r10;
1263 break;
1264 case SVM_REG_R11:
1265 reg_p = (unsigned long *)&regs->r11;
1266 break;
1267 case SVM_REG_R12:
1268 reg_p = (unsigned long *)&regs->r12;
1269 break;
1270 case SVM_REG_R13:
1271 reg_p = (unsigned long *)&regs->r13;
1272 break;
1273 case SVM_REG_R14:
1274 reg_p = (unsigned long *)&regs->r14;
1275 break;
1276 case SVM_REG_R15:
1277 reg_p = (unsigned long *)&regs->r15;
1278 break;
1279 #endif
1280 default:
1281 BUG();
1284 return reg_p;
1288 static inline unsigned long get_reg(unsigned int gpreg,
1289 struct cpu_user_regs *regs, struct vmcb_struct *vmcb)
1291 unsigned long *gp;
1292 gp = get_reg_p(gpreg, regs, vmcb);
1293 return *gp;
1297 static inline void set_reg(unsigned int gpreg, unsigned long value,
1298 struct cpu_user_regs *regs, struct vmcb_struct *vmcb)
1300 unsigned long *gp;
1301 gp = get_reg_p(gpreg, regs, vmcb);
1302 *gp = value;
1306 static void svm_dr_access(struct vcpu *v, struct cpu_user_regs *regs)
1308 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1310 v->arch.hvm_vcpu.flag_dr_dirty = 1;
1312 __restore_debug_registers(v);
1314 /* allow the guest full access to the debug registers */
1315 vmcb->dr_intercepts = 0;
1319 static void svm_get_prefix_info(
1320 struct vmcb_struct *vmcb,
1321 unsigned int dir, svm_segment_register_t **seg, unsigned int *asize)
1323 unsigned char inst[MAX_INST_LEN];
1324 int i;
1326 memset(inst, 0, MAX_INST_LEN);
1327 if (inst_copy_from_guest(inst, svm_rip2pointer(vmcb), sizeof(inst))
1328 != MAX_INST_LEN)
1330 gdprintk(XENLOG_ERR, "get guest instruction failed\n");
1331 domain_crash(current->domain);
1332 return;
1335 for (i = 0; i < MAX_INST_LEN; i++)
1337 switch (inst[i])
1339 case 0xf3: /* REPZ */
1340 case 0xf2: /* REPNZ */
1341 case 0xf0: /* LOCK */
1342 case 0x66: /* data32 */
1343 #ifdef __x86_64__
1344 /* REX prefixes */
1345 case 0x40:
1346 case 0x41:
1347 case 0x42:
1348 case 0x43:
1349 case 0x44:
1350 case 0x45:
1351 case 0x46:
1352 case 0x47:
1354 case 0x48:
1355 case 0x49:
1356 case 0x4a:
1357 case 0x4b:
1358 case 0x4c:
1359 case 0x4d:
1360 case 0x4e:
1361 case 0x4f:
1362 #endif
1363 continue;
1364 case 0x67: /* addr32 */
1365 *asize ^= 48; /* Switch 16/32 bits */
1366 continue;
1367 case 0x2e: /* CS */
1368 *seg = &vmcb->cs;
1369 continue;
1370 case 0x36: /* SS */
1371 *seg = &vmcb->ss;
1372 continue;
1373 case 0x26: /* ES */
1374 *seg = &vmcb->es;
1375 continue;
1376 case 0x64: /* FS */
1377 *seg = &vmcb->fs;
1378 continue;
1379 case 0x65: /* GS */
1380 *seg = &vmcb->gs;
1381 continue;
1382 case 0x3e: /* DS */
1383 *seg = &vmcb->ds;
1384 continue;
1385 default:
1386 break;
1388 return;
1393 /* Get the address of INS/OUTS instruction */
1394 static inline int svm_get_io_address(
1395 struct vcpu *v, struct cpu_user_regs *regs,
1396 unsigned int size, ioio_info_t info,
1397 unsigned long *count, unsigned long *addr)
1399 unsigned long reg;
1400 unsigned int asize, isize;
1401 int long_mode = 0;
1402 svm_segment_register_t *seg = NULL;
1403 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1405 #ifdef __x86_64__
1406 /* If we're in long mode, we shouldn't check the segment presence & limit */
1407 long_mode = vmcb->cs.attr.fields.l && vmcb->efer & EFER_LMA;
1408 #endif
1410 /* d field of cs.attr is 1 for 32-bit, 0 for 16 or 64 bit.
1411 * l field combined with EFER_LMA says whether it's 16 or 64 bit.
1412 */
1413 asize = (long_mode)?64:((vmcb->cs.attr.fields.db)?32:16);
1416 /* The ins/outs instructions are single byte, so if we have got more
1417 * than one byte (+ maybe rep-prefix), we have some prefix so we need
1418 * to figure out what it is...
1419 */
1420 isize = vmcb->exitinfo2 - vmcb->rip;
1422 if (info.fields.rep)
1423 isize --;
1425 if (isize > 1)
1426 svm_get_prefix_info(vmcb, info.fields.type, &seg, &asize);
1428 if (info.fields.type == IOREQ_WRITE)
1430 reg = regs->esi;
1431 if (!seg) /* If no prefix, used DS. */
1432 seg = &vmcb->ds;
1433 if (!long_mode && (seg->attr.fields.type & 0xa) == 0x8) {
1434 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1435 return 0;
1438 else
1440 reg = regs->edi;
1441 seg = &vmcb->es; /* Note: This is ALWAYS ES. */
1442 if (!long_mode && (seg->attr.fields.type & 0xa) != 0x2) {
1443 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1444 return 0;
1448 /* If the segment isn't present, give GP fault! */
1449 if (!long_mode && !seg->attr.fields.p)
1451 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1452 return 0;
1455 if (asize == 16)
1457 *addr = (reg & 0xFFFF);
1458 *count = regs->ecx & 0xffff;
1460 else
1462 *addr = reg;
1463 *count = regs->ecx;
1465 if (!info.fields.rep)
1466 *count = 1;
1468 if (!long_mode)
1470 ASSERT(*addr == (u32)*addr);
1471 if ((u32)(*addr + size - 1) < (u32)*addr ||
1472 (seg->attr.fields.type & 0xc) != 0x4 ?
1473 *addr + size - 1 > seg->limit :
1474 *addr <= seg->limit)
1476 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1477 return 0;
1480 /* Check the limit for repeated instructions, as above we checked only
1481 the first instance. Truncate the count if a limit violation would
1482 occur. Note that the checking is not necessary for page granular
1483 segments as transfers crossing page boundaries will be broken up
1484 anyway. */
1485 if (!seg->attr.fields.g && *count > 1)
1487 if ((seg->attr.fields.type & 0xc) != 0x4)
1489 /* expand-up */
1490 if (!(regs->eflags & EF_DF))
1492 if (*addr + *count * size - 1 < *addr ||
1493 *addr + *count * size - 1 > seg->limit)
1494 *count = (seg->limit + 1UL - *addr) / size;
1496 else
1498 if (*count - 1 > *addr / size)
1499 *count = *addr / size + 1;
1502 else
1504 /* expand-down */
1505 if (!(regs->eflags & EF_DF))
1507 if (*count - 1 > -(s32)*addr / size)
1508 *count = -(s32)*addr / size + 1UL;
1510 else
1512 if (*addr < (*count - 1) * size ||
1513 *addr - (*count - 1) * size <= seg->limit)
1514 *count = (*addr - seg->limit - 1) / size + 1;
1517 ASSERT(*count);
1520 *addr += seg->base;
1522 #ifdef __x86_64__
1523 else
1525 if (seg == &vmcb->fs || seg == &vmcb->gs)
1526 *addr += seg->base;
1528 if (!is_canonical_address(*addr) ||
1529 !is_canonical_address(*addr + size - 1))
1531 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1532 return 0;
1534 if (*count > (1UL << 48) / size)
1535 *count = (1UL << 48) / size;
1536 if (!(regs->eflags & EF_DF))
1538 if (*addr + *count * size - 1 < *addr ||
1539 !is_canonical_address(*addr + *count * size - 1))
1540 *count = (*addr & ~((1UL << 48) - 1)) / size;
1542 else
1544 if ((*count - 1) * size > *addr ||
1545 !is_canonical_address(*addr + (*count - 1) * size))
1546 *count = (*addr & ~((1UL << 48) - 1)) / size + 1;
1548 ASSERT(*count);
1550 #endif
1552 return 1;
1556 static void svm_io_instruction(struct vcpu *v)
1558 struct cpu_user_regs *regs;
1559 struct hvm_io_op *pio_opp;
1560 unsigned int port;
1561 unsigned int size, dir, df;
1562 ioio_info_t info;
1563 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1565 ASSERT(vmcb);
1566 pio_opp = &current->arch.hvm_vcpu.io_op;
1567 pio_opp->instr = INSTR_PIO;
1568 pio_opp->flags = 0;
1570 regs = &pio_opp->io_context;
1572 /* Copy current guest state into io instruction state structure. */
1573 memcpy(regs, guest_cpu_user_regs(), HVM_CONTEXT_STACK_BYTES);
1574 hvm_store_cpu_guest_regs(v, regs, NULL);
1576 info.bytes = vmcb->exitinfo1;
1578 port = info.fields.port; /* port used to be addr */
1579 dir = info.fields.type; /* direction */
1580 df = regs->eflags & X86_EFLAGS_DF ? 1 : 0;
1582 if (info.fields.sz32)
1583 size = 4;
1584 else if (info.fields.sz16)
1585 size = 2;
1586 else
1587 size = 1;
1589 HVM_DBG_LOG(DBG_LEVEL_IO,
1590 "svm_io_instruction: port 0x%x eip=%x:%"PRIx64", "
1591 "exit_qualification = %"PRIx64,
1592 port, vmcb->cs.sel, vmcb->rip, info.bytes);
1594 /* string instruction */
1595 if (info.fields.str)
1597 unsigned long addr, count;
1598 int sign = regs->eflags & X86_EFLAGS_DF ? -1 : 1;
1600 if (!svm_get_io_address(v, regs, size, info, &count, &addr))
1602 /* We failed to get a valid address, so don't do the IO operation -
1603 * it would just get worse if we do! Hopefully the guest is handing
1604 * gp-faults...
1605 */
1606 return;
1609 /* "rep" prefix */
1610 if (info.fields.rep)
1612 pio_opp->flags |= REPZ;
1615 /*
1616 * Handle string pio instructions that cross pages or that
1617 * are unaligned. See the comments in hvm_platform.c/handle_mmio()
1618 */
1619 if ((addr & PAGE_MASK) != ((addr + size - 1) & PAGE_MASK))
1621 unsigned long value = 0;
1623 pio_opp->flags |= OVERLAP;
1624 pio_opp->addr = addr;
1626 if (dir == IOREQ_WRITE) /* OUTS */
1628 if (hvm_paging_enabled(current))
1629 (void)hvm_copy_from_guest_virt(&value, addr, size);
1630 else
1631 (void)hvm_copy_from_guest_phys(&value, addr, size);
1634 if (count == 1)
1635 regs->eip = vmcb->exitinfo2;
1637 send_pio_req(port, 1, size, value, dir, df, 0);
1639 else
1641 unsigned long last_addr = sign > 0 ? addr + count * size - 1
1642 : addr - (count - 1) * size;
1644 if ((addr & PAGE_MASK) != (last_addr & PAGE_MASK))
1646 if (sign > 0)
1647 count = (PAGE_SIZE - (addr & ~PAGE_MASK)) / size;
1648 else
1649 count = (addr & ~PAGE_MASK) / size + 1;
1651 else
1652 regs->eip = vmcb->exitinfo2;
1654 send_pio_req(port, count, size, addr, dir, df, 1);
1657 else
1659 /*
1660 * On SVM, the RIP of the intruction following the IN/OUT is saved in
1661 * ExitInfo2
1662 */
1663 regs->eip = vmcb->exitinfo2;
1665 if (port == 0xe9 && dir == IOREQ_WRITE && size == 1)
1666 hvm_print_line(v, regs->eax); /* guest debug output */
1668 send_pio_req(port, 1, size, regs->eax, dir, df, 0);
1672 static int svm_set_cr0(unsigned long value)
1674 struct vcpu *v = current;
1675 unsigned long mfn;
1676 int paging_enabled;
1677 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1678 unsigned long old_base_mfn;
1680 ASSERT(vmcb);
1682 /* We don't want to lose PG. ET is reserved and should be always be 1*/
1683 paging_enabled = svm_paging_enabled(v);
1684 value |= X86_CR0_ET;
1685 vmcb->cr0 = value | X86_CR0_PG | X86_CR0_WP;
1686 v->arch.hvm_svm.cpu_shadow_cr0 = value;
1688 /* TS cleared? Then initialise FPU now. */
1689 if ( !(value & X86_CR0_TS) )
1691 setup_fpu(v);
1692 vmcb->exception_intercepts &= ~EXCEPTION_BITMAP_NM;
1695 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR0 value = %lx\n", value);
1697 if ((value & X86_CR0_PE) && (value & X86_CR0_PG) && !paging_enabled)
1699 /* The guest CR3 must be pointing to the guest physical. */
1700 mfn = get_mfn_from_gpfn(v->arch.hvm_svm.cpu_cr3 >> PAGE_SHIFT);
1701 if ( !mfn_valid(mfn) || !get_page(mfn_to_page(mfn), v->domain))
1703 gdprintk(XENLOG_ERR, "Invalid CR3 value = %lx (mfn=%lx)\n",
1704 v->arch.hvm_svm.cpu_cr3, mfn);
1705 domain_crash(v->domain);
1706 return 0;
1709 #if defined(__x86_64__)
1710 if (test_bit(SVM_CPU_STATE_LME_ENABLED, &v->arch.hvm_svm.cpu_state)
1711 && !test_bit(SVM_CPU_STATE_PAE_ENABLED,
1712 &v->arch.hvm_svm.cpu_state))
1714 HVM_DBG_LOG(DBG_LEVEL_1, "Enable paging before PAE enable\n");
1715 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1718 if (test_bit(SVM_CPU_STATE_LME_ENABLED, &v->arch.hvm_svm.cpu_state))
1720 HVM_DBG_LOG(DBG_LEVEL_1, "Enable the Long mode\n");
1721 set_bit(SVM_CPU_STATE_LMA_ENABLED, &v->arch.hvm_svm.cpu_state);
1722 vmcb->efer |= EFER_LMA | EFER_LME;
1724 #endif /* __x86_64__ */
1726 /* Now arch.guest_table points to machine physical. */
1727 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1728 v->arch.guest_table = pagetable_from_pfn(mfn);
1729 if ( old_base_mfn )
1730 put_page(mfn_to_page(old_base_mfn));
1731 paging_update_paging_modes(v);
1733 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1734 (unsigned long) (mfn << PAGE_SHIFT));
1737 if ( !((value & X86_CR0_PE) && (value & X86_CR0_PG)) && paging_enabled )
1738 if ( v->arch.hvm_svm.cpu_cr3 ) {
1739 put_page(mfn_to_page(get_mfn_from_gpfn(
1740 v->arch.hvm_svm.cpu_cr3 >> PAGE_SHIFT)));
1741 v->arch.guest_table = pagetable_null();
1744 /*
1745 * SVM implements paged real-mode and when we return to real-mode
1746 * we revert back to the physical mappings that the domain builder
1747 * created.
1748 */
1749 if ((value & X86_CR0_PE) == 0) {
1750 if (value & X86_CR0_PG) {
1751 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1752 return 0;
1754 paging_update_paging_modes(v);
1756 else if ( (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PE )
1758 if ( svm_long_mode_enabled(v) )
1760 vmcb->efer &= ~EFER_LMA;
1761 clear_bit(SVM_CPU_STATE_LMA_ENABLED, &v->arch.hvm_svm.cpu_state);
1763 /* we should take care of this kind of situation */
1764 paging_update_paging_modes(v);
1767 return 1;
1770 /*
1771 * Read from control registers. CR0 and CR4 are read from the shadow.
1772 */
1773 static void mov_from_cr(int cr, int gp, struct cpu_user_regs *regs)
1775 unsigned long value = 0;
1776 struct vcpu *v = current;
1777 struct vlapic *vlapic = vcpu_vlapic(v);
1778 struct vmcb_struct *vmcb;
1780 vmcb = v->arch.hvm_svm.vmcb;
1781 ASSERT(vmcb);
1783 switch ( cr )
1785 case 0:
1786 value = v->arch.hvm_svm.cpu_shadow_cr0;
1787 if (svm_dbg_on)
1788 printk("CR0 read =%lx \n", value );
1789 break;
1790 case 2:
1791 value = vmcb->cr2;
1792 break;
1793 case 3:
1794 value = (unsigned long) v->arch.hvm_svm.cpu_cr3;
1795 if (svm_dbg_on)
1796 printk("CR3 read =%lx \n", value );
1797 break;
1798 case 4:
1799 value = (unsigned long) v->arch.hvm_svm.cpu_shadow_cr4;
1800 if (svm_dbg_on)
1801 printk("CR4 read=%lx\n", value);
1802 break;
1803 case 8:
1804 value = (unsigned long)vlapic_get_reg(vlapic, APIC_TASKPRI);
1805 value = (value & 0xF0) >> 4;
1806 break;
1808 default:
1809 domain_crash(v->domain);
1810 return;
1813 set_reg(gp, value, regs, vmcb);
1815 HVM_DBG_LOG(DBG_LEVEL_VMMU, "mov_from_cr: CR%d, value = %lx,", cr, value);
1819 static inline int svm_pgbit_test(struct vcpu *v)
1821 return v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_PG;
1825 /*
1826 * Write to control registers
1827 */
1828 static int mov_to_cr(int gpreg, int cr, struct cpu_user_regs *regs)
1830 unsigned long value, old_cr, old_base_mfn, mfn;
1831 struct vcpu *v = current;
1832 struct vlapic *vlapic = vcpu_vlapic(v);
1833 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1835 value = get_reg(gpreg, regs, vmcb);
1837 HVM_DBG_LOG(DBG_LEVEL_1, "mov_to_cr: CR%d, value = %lx,", cr, value);
1838 HVM_DBG_LOG(DBG_LEVEL_1, "current = %lx,", (unsigned long) current);
1840 switch (cr)
1842 case 0:
1843 if (svm_dbg_on)
1844 printk("CR0 write =%lx \n", value );
1845 return svm_set_cr0(value);
1847 case 3:
1848 if (svm_dbg_on)
1849 printk("CR3 write =%lx \n", value );
1850 /* If paging is not enabled yet, simply copy the value to CR3. */
1851 if (!svm_paging_enabled(v)) {
1852 v->arch.hvm_svm.cpu_cr3 = value;
1853 break;
1856 /* We make a new one if the shadow does not exist. */
1857 if (value == v->arch.hvm_svm.cpu_cr3)
1859 /*
1860 * This is simple TLB flush, implying the guest has
1861 * removed some translation or changed page attributes.
1862 * We simply invalidate the shadow.
1863 */
1864 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1865 if (mfn != pagetable_get_pfn(v->arch.guest_table))
1866 goto bad_cr3;
1867 paging_update_cr3(v);
1869 else
1871 /*
1872 * If different, make a shadow. Check if the PDBR is valid
1873 * first.
1874 */
1875 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 value = %lx", value);
1876 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1877 if ( !mfn_valid(mfn) || !get_page(mfn_to_page(mfn), v->domain))
1878 goto bad_cr3;
1880 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1881 v->arch.guest_table = pagetable_from_pfn(mfn);
1883 if (old_base_mfn)
1884 put_page(mfn_to_page(old_base_mfn));
1886 v->arch.hvm_svm.cpu_cr3 = value;
1887 update_cr3(v);
1888 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx", value);
1890 break;
1892 case 4: /* CR4 */
1893 if (svm_dbg_on)
1894 printk( "write cr4=%lx, cr0=%lx\n",
1895 value, v->arch.hvm_svm.cpu_shadow_cr0 );
1896 old_cr = v->arch.hvm_svm.cpu_shadow_cr4;
1897 if ( value & X86_CR4_PAE && !(old_cr & X86_CR4_PAE) )
1899 set_bit(SVM_CPU_STATE_PAE_ENABLED, &v->arch.hvm_svm.cpu_state);
1900 if ( svm_pgbit_test(v) )
1902 /* The guest is a 32-bit PAE guest. */
1903 #if CONFIG_PAGING_LEVELS >= 3
1904 unsigned long mfn, old_base_mfn;
1905 mfn = get_mfn_from_gpfn(v->arch.hvm_svm.cpu_cr3 >> PAGE_SHIFT);
1906 if ( !mfn_valid(mfn) ||
1907 !get_page(mfn_to_page(mfn), v->domain) )
1908 goto bad_cr3;
1910 /*
1911 * Now arch.guest_table points to machine physical.
1912 */
1914 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1915 v->arch.guest_table = pagetable_from_pfn(mfn);
1916 if ( old_base_mfn )
1917 put_page(mfn_to_page(old_base_mfn));
1918 paging_update_paging_modes(v);
1920 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1921 (unsigned long) (mfn << PAGE_SHIFT));
1923 HVM_DBG_LOG(DBG_LEVEL_VMMU,
1924 "Update CR3 value = %lx, mfn = %lx",
1925 v->arch.hvm_svm.cpu_cr3, mfn);
1926 #endif
1929 else if (value & X86_CR4_PAE) {
1930 set_bit(SVM_CPU_STATE_PAE_ENABLED, &v->arch.hvm_svm.cpu_state);
1931 } else {
1932 if (test_bit(SVM_CPU_STATE_LMA_ENABLED,
1933 &v->arch.hvm_svm.cpu_state)) {
1934 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1936 clear_bit(SVM_CPU_STATE_PAE_ENABLED, &v->arch.hvm_svm.cpu_state);
1939 v->arch.hvm_svm.cpu_shadow_cr4 = value;
1940 vmcb->cr4 = value | SVM_CR4_HOST_MASK;
1942 /*
1943 * Writing to CR4 to modify the PSE, PGE, or PAE flag invalidates
1944 * all TLB entries except global entries.
1945 */
1946 if ((old_cr ^ value) & (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE))
1947 paging_update_paging_modes(v);
1948 break;
1950 case 8:
1951 vlapic_set_reg(vlapic, APIC_TASKPRI, ((value & 0x0F) << 4));
1952 vmcb->vintr.fields.tpr = value & 0x0F;
1953 break;
1955 default:
1956 gdprintk(XENLOG_ERR, "invalid cr: %d\n", cr);
1957 domain_crash(v->domain);
1958 return 0;
1961 return 1;
1963 bad_cr3:
1964 gdprintk(XENLOG_ERR, "Invalid CR3\n");
1965 domain_crash(v->domain);
1966 return 0;
1970 #define ARR_SIZE(x) (sizeof(x) / sizeof(x[0]))
1973 static int svm_cr_access(struct vcpu *v, unsigned int cr, unsigned int type,
1974 struct cpu_user_regs *regs)
1976 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1977 int inst_len = 0;
1978 int index;
1979 unsigned int gpreg;
1980 unsigned long value;
1981 u8 buffer[MAX_INST_LEN];
1982 u8 prefix = 0;
1983 int result = 1;
1984 enum instruction_index list_a[] = {INSTR_MOV2CR, INSTR_CLTS, INSTR_LMSW};
1985 enum instruction_index list_b[] = {INSTR_MOVCR2, INSTR_SMSW};
1986 enum instruction_index match;
1988 ASSERT(vmcb);
1990 inst_copy_from_guest(buffer, svm_rip2pointer(vmcb), sizeof(buffer));
1992 /* get index to first actual instruction byte - as we will need to know
1993 where the prefix lives later on */
1994 index = skip_prefix_bytes(buffer, sizeof(buffer));
1996 if ( type == TYPE_MOV_TO_CR )
1998 inst_len = __get_instruction_length_from_list(
1999 vmcb, list_a, ARR_SIZE(list_a), &buffer[index], &match);
2001 else /* type == TYPE_MOV_FROM_CR */
2003 inst_len = __get_instruction_length_from_list(
2004 vmcb, list_b, ARR_SIZE(list_b), &buffer[index], &match);
2007 ASSERT(inst_len > 0);
2009 inst_len += index;
2011 /* Check for REX prefix - it's ALWAYS the last byte of any prefix bytes */
2012 if (index > 0 && (buffer[index-1] & 0xF0) == 0x40)
2013 prefix = buffer[index-1];
2015 HVM_DBG_LOG(DBG_LEVEL_1, "eip = %lx", (unsigned long) vmcb->rip);
2017 switch (match)
2019 case INSTR_MOV2CR:
2020 gpreg = decode_src_reg(prefix, buffer[index+2]);
2021 result = mov_to_cr(gpreg, cr, regs);
2022 break;
2024 case INSTR_MOVCR2:
2025 gpreg = decode_src_reg(prefix, buffer[index+2]);
2026 mov_from_cr(cr, gpreg, regs);
2027 break;
2029 case INSTR_CLTS:
2030 /* TS being cleared means that it's time to restore fpu state. */
2031 setup_fpu(current);
2032 vmcb->exception_intercepts &= ~EXCEPTION_BITMAP_NM;
2033 vmcb->cr0 &= ~X86_CR0_TS; /* clear TS */
2034 v->arch.hvm_svm.cpu_shadow_cr0 &= ~X86_CR0_TS; /* clear TS */
2035 break;
2037 case INSTR_LMSW:
2038 if (svm_dbg_on)
2039 svm_dump_inst(svm_rip2pointer(vmcb));
2041 gpreg = decode_src_reg(prefix, buffer[index+2]);
2042 value = get_reg(gpreg, regs, vmcb) & 0xF;
2044 if (svm_dbg_on)
2045 printk("CR0-LMSW value=%lx, reg=%d, inst_len=%d\n", value, gpreg,
2046 inst_len);
2048 value = (v->arch.hvm_svm.cpu_shadow_cr0 & ~0xF) | value;
2050 if (svm_dbg_on)
2051 printk("CR0-LMSW CR0 - New value=%lx\n", value);
2053 result = svm_set_cr0(value);
2054 break;
2056 case INSTR_SMSW:
2057 if (svm_dbg_on)
2058 svm_dump_inst(svm_rip2pointer(vmcb));
2059 value = v->arch.hvm_svm.cpu_shadow_cr0;
2060 gpreg = decode_src_reg(prefix, buffer[index+2]);
2061 set_reg(gpreg, value, regs, vmcb);
2063 if (svm_dbg_on)
2064 printk("CR0-SMSW value=%lx, reg=%d, inst_len=%d\n", value, gpreg,
2065 inst_len);
2066 break;
2068 default:
2069 BUG();
2072 ASSERT(inst_len);
2074 __update_guest_eip(vmcb, inst_len);
2076 return result;
2079 static inline void svm_do_msr_access(
2080 struct vcpu *v, struct cpu_user_regs *regs)
2082 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2083 int inst_len;
2084 u64 msr_content=0;
2085 u32 ecx = regs->ecx, eax, edx;
2087 ASSERT(vmcb);
2089 HVM_DBG_LOG(DBG_LEVEL_1, "ecx=%x, eax=%x, edx=%x, exitinfo = %lx",
2090 ecx, (u32)regs->eax, (u32)regs->edx,
2091 (unsigned long)vmcb->exitinfo1);
2093 /* is it a read? */
2094 if (vmcb->exitinfo1 == 0)
2096 switch (ecx) {
2097 case MSR_IA32_TIME_STAMP_COUNTER:
2098 msr_content = hvm_get_guest_time(v);
2099 break;
2100 case MSR_IA32_SYSENTER_CS:
2101 msr_content = vmcb->sysenter_cs;
2102 break;
2103 case MSR_IA32_SYSENTER_ESP:
2104 msr_content = vmcb->sysenter_esp;
2105 break;
2106 case MSR_IA32_SYSENTER_EIP:
2107 msr_content = vmcb->sysenter_eip;
2108 break;
2109 case MSR_IA32_APICBASE:
2110 msr_content = vcpu_vlapic(v)->hw.apic_base_msr;
2111 break;
2112 default:
2113 if (long_mode_do_msr_read(regs))
2114 goto done;
2116 if ( rdmsr_hypervisor_regs(ecx, &eax, &edx) ||
2117 rdmsr_safe(ecx, eax, edx) == 0 )
2119 regs->eax = eax;
2120 regs->edx = edx;
2121 goto done;
2123 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
2124 return;
2126 regs->eax = msr_content & 0xFFFFFFFF;
2127 regs->edx = msr_content >> 32;
2129 done:
2130 HVM_DBG_LOG(DBG_LEVEL_1, "returns: ecx=%x, eax=%lx, edx=%lx",
2131 ecx, (unsigned long)regs->eax, (unsigned long)regs->edx);
2133 inst_len = __get_instruction_length(vmcb, INSTR_RDMSR, NULL);
2135 else
2137 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
2139 switch (ecx)
2141 case MSR_IA32_TIME_STAMP_COUNTER:
2142 hvm_set_guest_time(v, msr_content);
2143 pt_reset(v);
2144 break;
2145 case MSR_IA32_SYSENTER_CS:
2146 vmcb->sysenter_cs = msr_content;
2147 break;
2148 case MSR_IA32_SYSENTER_ESP:
2149 vmcb->sysenter_esp = msr_content;
2150 break;
2151 case MSR_IA32_SYSENTER_EIP:
2152 vmcb->sysenter_eip = msr_content;
2153 break;
2154 case MSR_IA32_APICBASE:
2155 vlapic_msr_set(vcpu_vlapic(v), msr_content);
2156 break;
2157 default:
2158 if ( !long_mode_do_msr_write(regs) )
2159 wrmsr_hypervisor_regs(ecx, regs->eax, regs->edx);
2160 break;
2163 inst_len = __get_instruction_length(vmcb, INSTR_WRMSR, NULL);
2166 __update_guest_eip(vmcb, inst_len);
2170 static inline void svm_vmexit_do_hlt(struct vmcb_struct *vmcb)
2172 __update_guest_eip(vmcb, 1);
2174 /* Check for interrupt not handled or new interrupt. */
2175 if ( (vmcb->rflags & X86_EFLAGS_IF) &&
2176 (vmcb->vintr.fields.irq || cpu_has_pending_irq(current)) )
2177 return;
2179 hvm_hlt(vmcb->rflags);
2183 static void svm_vmexit_do_invd(struct vmcb_struct *vmcb)
2185 int inst_len;
2187 /* Invalidate the cache - we can't really do that safely - maybe we should
2188 * WBINVD, but I think it's just fine to completely ignore it - we should
2189 * have cache-snooping that solves it anyways. -- Mats P.
2190 */
2192 /* Tell the user that we did this - just in case someone runs some really
2193 * weird operating system and wants to know why it's not working...
2194 */
2195 printk("INVD instruction intercepted - ignored\n");
2197 inst_len = __get_instruction_length(vmcb, INSTR_INVD, NULL);
2198 __update_guest_eip(vmcb, inst_len);
2204 #ifdef XEN_DEBUGGER
2205 static void svm_debug_save_cpu_user_regs(struct vmcb_struct *vmcb,
2206 struct cpu_user_regs *regs)
2208 regs->eip = vmcb->rip;
2209 regs->esp = vmcb->rsp;
2210 regs->eflags = vmcb->rflags;
2212 regs->xcs = vmcb->cs.sel;
2213 regs->xds = vmcb->ds.sel;
2214 regs->xes = vmcb->es.sel;
2215 regs->xfs = vmcb->fs.sel;
2216 regs->xgs = vmcb->gs.sel;
2217 regs->xss = vmcb->ss.sel;
2221 static void svm_debug_restore_cpu_user_regs(struct cpu_user_regs *regs)
2223 vmcb->ss.sel = regs->xss;
2224 vmcb->rsp = regs->esp;
2225 vmcb->rflags = regs->eflags;
2226 vmcb->cs.sel = regs->xcs;
2227 vmcb->rip = regs->eip;
2229 vmcb->gs.sel = regs->xgs;
2230 vmcb->fs.sel = regs->xfs;
2231 vmcb->es.sel = regs->xes;
2232 vmcb->ds.sel = regs->xds;
2234 #endif
2237 void svm_handle_invlpg(const short invlpga, struct cpu_user_regs *regs)
2239 struct vcpu *v = current;
2240 u8 opcode[MAX_INST_LEN], prefix, length = MAX_INST_LEN;
2241 unsigned long g_vaddr;
2242 int inst_len;
2243 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2245 /*
2246 * Unknown how many bytes the invlpg instruction will take. Use the
2247 * maximum instruction length here
2248 */
2249 if (inst_copy_from_guest(opcode, svm_rip2pointer(vmcb), length) < length)
2251 gdprintk(XENLOG_ERR, "Error reading memory %d bytes\n", length);
2252 domain_crash(v->domain);
2253 return;
2256 if (invlpga)
2258 inst_len = __get_instruction_length(vmcb, INSTR_INVLPGA, opcode);
2259 ASSERT(inst_len > 0);
2260 __update_guest_eip(vmcb, inst_len);
2262 /*
2263 * The address is implicit on this instruction. At the moment, we don't
2264 * use ecx (ASID) to identify individual guests pages
2265 */
2266 g_vaddr = regs->eax;
2268 else
2270 /* What about multiple prefix codes? */
2271 prefix = (is_prefix(opcode[0])?opcode[0]:0);
2272 inst_len = __get_instruction_length(vmcb, INSTR_INVLPG, opcode);
2273 ASSERT(inst_len > 0);
2275 inst_len--;
2276 length -= inst_len;
2278 /*
2279 * Decode memory operand of the instruction including ModRM, SIB, and
2280 * displacement to get effective address and length in bytes. Assume
2281 * the system in either 32- or 64-bit mode.
2282 */
2283 g_vaddr = get_effective_addr_modrm64(vmcb, regs, prefix, inst_len,
2284 &opcode[inst_len], &length);
2286 inst_len += length;
2287 __update_guest_eip (vmcb, inst_len);
2290 paging_invlpg(v, g_vaddr);
2294 /*
2295 * Reset to realmode causes execution to start at 0xF000:0xFFF0 in
2296 * 16-bit realmode. Basically, this mimics a processor reset.
2298 * returns 0 on success, non-zero otherwise
2299 */
2300 static int svm_do_vmmcall_reset_to_realmode(struct vcpu *v,
2301 struct cpu_user_regs *regs)
2303 struct vmcb_struct *vmcb;
2305 ASSERT(v);
2306 ASSERT(regs);
2308 vmcb = v->arch.hvm_svm.vmcb;
2310 ASSERT(vmcb);
2312 /* clear the vmcb and user regs */
2313 memset(regs, 0, sizeof(struct cpu_user_regs));
2315 /* VMCB Control */
2316 vmcb->tsc_offset = 0;
2318 /* VMCB State */
2319 vmcb->cr0 = X86_CR0_ET | X86_CR0_PG | X86_CR0_WP;
2320 v->arch.hvm_svm.cpu_shadow_cr0 = X86_CR0_ET;
2322 vmcb->cr2 = 0;
2323 vmcb->efer = EFER_SVME;
2325 vmcb->cr4 = SVM_CR4_HOST_MASK;
2326 v->arch.hvm_svm.cpu_shadow_cr4 = 0;
2327 clear_bit(SVM_CPU_STATE_PAE_ENABLED, &v->arch.hvm_svm.cpu_state);
2329 /* This will jump to ROMBIOS */
2330 vmcb->rip = 0xFFF0;
2332 /* setup the segment registers and all their hidden states */
2333 vmcb->cs.sel = 0xF000;
2334 vmcb->cs.attr.bytes = 0x089b;
2335 vmcb->cs.limit = 0xffff;
2336 vmcb->cs.base = 0x000F0000;
2338 vmcb->ss.sel = 0x00;
2339 vmcb->ss.attr.bytes = 0x0893;
2340 vmcb->ss.limit = 0xffff;
2341 vmcb->ss.base = 0x00;
2343 vmcb->ds.sel = 0x00;
2344 vmcb->ds.attr.bytes = 0x0893;
2345 vmcb->ds.limit = 0xffff;
2346 vmcb->ds.base = 0x00;
2348 vmcb->es.sel = 0x00;
2349 vmcb->es.attr.bytes = 0x0893;
2350 vmcb->es.limit = 0xffff;
2351 vmcb->es.base = 0x00;
2353 vmcb->fs.sel = 0x00;
2354 vmcb->fs.attr.bytes = 0x0893;
2355 vmcb->fs.limit = 0xffff;
2356 vmcb->fs.base = 0x00;
2358 vmcb->gs.sel = 0x00;
2359 vmcb->gs.attr.bytes = 0x0893;
2360 vmcb->gs.limit = 0xffff;
2361 vmcb->gs.base = 0x00;
2363 vmcb->ldtr.sel = 0x00;
2364 vmcb->ldtr.attr.bytes = 0x0000;
2365 vmcb->ldtr.limit = 0x0;
2366 vmcb->ldtr.base = 0x00;
2368 vmcb->gdtr.sel = 0x00;
2369 vmcb->gdtr.attr.bytes = 0x0000;
2370 vmcb->gdtr.limit = 0x0;
2371 vmcb->gdtr.base = 0x00;
2373 vmcb->tr.sel = 0;
2374 vmcb->tr.attr.bytes = 0;
2375 vmcb->tr.limit = 0x0;
2376 vmcb->tr.base = 0;
2378 vmcb->idtr.sel = 0x00;
2379 vmcb->idtr.attr.bytes = 0x0000;
2380 vmcb->idtr.limit = 0x3ff;
2381 vmcb->idtr.base = 0x00;
2383 vmcb->rax = 0;
2384 vmcb->rsp = 0;
2386 return 0;
2390 /*
2391 * svm_do_vmmcall - SVM VMMCALL handler
2393 * returns 0 on success, non-zero otherwise
2394 */
2395 static int svm_do_vmmcall(struct vcpu *v, struct cpu_user_regs *regs)
2397 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2398 int inst_len;
2400 ASSERT(vmcb);
2401 ASSERT(regs);
2403 inst_len = __get_instruction_length(vmcb, INSTR_VMCALL, NULL);
2404 ASSERT(inst_len > 0);
2406 if ( regs->eax & 0x80000000 )
2408 /* VMMCALL sanity check */
2409 if ( vmcb->cpl > get_vmmcall_cpl(regs->edi) )
2411 printk("VMMCALL CPL check failed\n");
2412 return -1;
2415 /* handle the request */
2416 switch ( regs->eax )
2418 case VMMCALL_RESET_TO_REALMODE:
2419 if ( svm_do_vmmcall_reset_to_realmode(v, regs) )
2421 printk("svm_do_vmmcall_reset_to_realmode() failed\n");
2422 return -1;
2424 /* since we just reset the VMCB, return without adjusting
2425 * the eip */
2426 return 0;
2428 case VMMCALL_DEBUG:
2429 printk("DEBUG features not implemented yet\n");
2430 break;
2431 default:
2432 break;
2435 hvm_print_line(v, regs->eax); /* provides the current domain */
2437 else
2439 hvm_do_hypercall(regs);
2442 __update_guest_eip(vmcb, inst_len);
2443 return 0;
2447 void svm_dump_inst(unsigned long eip)
2449 u8 opcode[256];
2450 unsigned long ptr;
2451 int len;
2452 int i;
2454 ptr = eip & ~0xff;
2455 len = 0;
2457 if (hvm_copy_from_guest_virt(opcode, ptr, sizeof(opcode)) == 0)
2458 len = sizeof(opcode);
2460 printk("Code bytes around(len=%d) %lx:", len, eip);
2461 for (i = 0; i < len; i++)
2463 if ((i & 0x0f) == 0)
2464 printk("\n%08lx:", ptr+i);
2466 printk("%02x ", opcode[i]);
2469 printk("\n");
2473 void svm_dump_regs(const char *from, struct cpu_user_regs *regs)
2475 struct vcpu *v = current;
2476 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2477 unsigned long pt = v->arch.hvm_vcpu.hw_cr3;
2479 printk("%s: guest registers from %s:\n", __func__, from);
2480 #if defined (__x86_64__)
2481 printk("rax: %016lx rbx: %016lx rcx: %016lx\n",
2482 regs->rax, regs->rbx, regs->rcx);
2483 printk("rdx: %016lx rsi: %016lx rdi: %016lx\n",
2484 regs->rdx, regs->rsi, regs->rdi);
2485 printk("rbp: %016lx rsp: %016lx r8: %016lx\n",
2486 regs->rbp, regs->rsp, regs->r8);
2487 printk("r9: %016lx r10: %016lx r11: %016lx\n",
2488 regs->r9, regs->r10, regs->r11);
2489 printk("r12: %016lx r13: %016lx r14: %016lx\n",
2490 regs->r12, regs->r13, regs->r14);
2491 printk("r15: %016lx cr0: %016lx cr3: %016lx\n",
2492 regs->r15, v->arch.hvm_svm.cpu_shadow_cr0, vmcb->cr3);
2493 #else
2494 printk("eax: %08x, ebx: %08x, ecx: %08x, edx: %08x\n",
2495 regs->eax, regs->ebx, regs->ecx, regs->edx);
2496 printk("edi: %08x, esi: %08x, ebp: %08x, esp: %08x\n",
2497 regs->edi, regs->esi, regs->ebp, regs->esp);
2498 printk("%s: guest cr0: %lx\n", __func__,
2499 v->arch.hvm_svm.cpu_shadow_cr0);
2500 printk("guest CR3 = %llx\n", vmcb->cr3);
2501 #endif
2502 printk("%s: pt = %lx\n", __func__, pt);
2506 void svm_dump_host_regs(const char *from)
2508 struct vcpu *v = current;
2509 unsigned long pt = pt = pagetable_get_paddr(v->arch.monitor_table);
2510 unsigned long cr3, cr0;
2511 printk("Host registers at %s\n", from);
2513 __asm__ __volatile__ ("\tmov %%cr0,%0\n"
2514 "\tmov %%cr3,%1\n"
2515 : "=r" (cr0), "=r"(cr3));
2516 printk("%s: pt = %lx, cr3 = %lx, cr0 = %lx\n", __func__, pt, cr3, cr0);
2519 #ifdef SVM_EXTRA_DEBUG
2520 static char *exit_reasons[] = {
2521 [VMEXIT_CR0_READ] = "CR0_READ",
2522 [VMEXIT_CR1_READ] = "CR1_READ",
2523 [VMEXIT_CR2_READ] = "CR2_READ",
2524 [VMEXIT_CR3_READ] = "CR3_READ",
2525 [VMEXIT_CR4_READ] = "CR4_READ",
2526 [VMEXIT_CR5_READ] = "CR5_READ",
2527 [VMEXIT_CR6_READ] = "CR6_READ",
2528 [VMEXIT_CR7_READ] = "CR7_READ",
2529 [VMEXIT_CR8_READ] = "CR8_READ",
2530 [VMEXIT_CR9_READ] = "CR9_READ",
2531 [VMEXIT_CR10_READ] = "CR10_READ",
2532 [VMEXIT_CR11_READ] = "CR11_READ",
2533 [VMEXIT_CR12_READ] = "CR12_READ",
2534 [VMEXIT_CR13_READ] = "CR13_READ",
2535 [VMEXIT_CR14_READ] = "CR14_READ",
2536 [VMEXIT_CR15_READ] = "CR15_READ",
2537 [VMEXIT_CR0_WRITE] = "CR0_WRITE",
2538 [VMEXIT_CR1_WRITE] = "CR1_WRITE",
2539 [VMEXIT_CR2_WRITE] = "CR2_WRITE",
2540 [VMEXIT_CR3_WRITE] = "CR3_WRITE",
2541 [VMEXIT_CR4_WRITE] = "CR4_WRITE",
2542 [VMEXIT_CR5_WRITE] = "CR5_WRITE",
2543 [VMEXIT_CR6_WRITE] = "CR6_WRITE",
2544 [VMEXIT_CR7_WRITE] = "CR7_WRITE",
2545 [VMEXIT_CR8_WRITE] = "CR8_WRITE",
2546 [VMEXIT_CR9_WRITE] = "CR9_WRITE",
2547 [VMEXIT_CR10_WRITE] = "CR10_WRITE",
2548 [VMEXIT_CR11_WRITE] = "CR11_WRITE",
2549 [VMEXIT_CR12_WRITE] = "CR12_WRITE",
2550 [VMEXIT_CR13_WRITE] = "CR13_WRITE",
2551 [VMEXIT_CR14_WRITE] = "CR14_WRITE",
2552 [VMEXIT_CR15_WRITE] = "CR15_WRITE",
2553 [VMEXIT_DR0_READ] = "DR0_READ",
2554 [VMEXIT_DR1_READ] = "DR1_READ",
2555 [VMEXIT_DR2_READ] = "DR2_READ",
2556 [VMEXIT_DR3_READ] = "DR3_READ",
2557 [VMEXIT_DR4_READ] = "DR4_READ",
2558 [VMEXIT_DR5_READ] = "DR5_READ",
2559 [VMEXIT_DR6_READ] = "DR6_READ",
2560 [VMEXIT_DR7_READ] = "DR7_READ",
2561 [VMEXIT_DR8_READ] = "DR8_READ",
2562 [VMEXIT_DR9_READ] = "DR9_READ",
2563 [VMEXIT_DR10_READ] = "DR10_READ",
2564 [VMEXIT_DR11_READ] = "DR11_READ",
2565 [VMEXIT_DR12_READ] = "DR12_READ",
2566 [VMEXIT_DR13_READ] = "DR13_READ",
2567 [VMEXIT_DR14_READ] = "DR14_READ",
2568 [VMEXIT_DR15_READ] = "DR15_READ",
2569 [VMEXIT_DR0_WRITE] = "DR0_WRITE",
2570 [VMEXIT_DR1_WRITE] = "DR1_WRITE",
2571 [VMEXIT_DR2_WRITE] = "DR2_WRITE",
2572 [VMEXIT_DR3_WRITE] = "DR3_WRITE",
2573 [VMEXIT_DR4_WRITE] = "DR4_WRITE",
2574 [VMEXIT_DR5_WRITE] = "DR5_WRITE",
2575 [VMEXIT_DR6_WRITE] = "DR6_WRITE",
2576 [VMEXIT_DR7_WRITE] = "DR7_WRITE",
2577 [VMEXIT_DR8_WRITE] = "DR8_WRITE",
2578 [VMEXIT_DR9_WRITE] = "DR9_WRITE",
2579 [VMEXIT_DR10_WRITE] = "DR10_WRITE",
2580 [VMEXIT_DR11_WRITE] = "DR11_WRITE",
2581 [VMEXIT_DR12_WRITE] = "DR12_WRITE",
2582 [VMEXIT_DR13_WRITE] = "DR13_WRITE",
2583 [VMEXIT_DR14_WRITE] = "DR14_WRITE",
2584 [VMEXIT_DR15_WRITE] = "DR15_WRITE",
2585 [VMEXIT_EXCEPTION_DE] = "EXCEPTION_DE",
2586 [VMEXIT_EXCEPTION_DB] = "EXCEPTION_DB",
2587 [VMEXIT_EXCEPTION_NMI] = "EXCEPTION_NMI",
2588 [VMEXIT_EXCEPTION_BP] = "EXCEPTION_BP",
2589 [VMEXIT_EXCEPTION_OF] = "EXCEPTION_OF",
2590 [VMEXIT_EXCEPTION_BR] = "EXCEPTION_BR",
2591 [VMEXIT_EXCEPTION_UD] = "EXCEPTION_UD",
2592 [VMEXIT_EXCEPTION_NM] = "EXCEPTION_NM",
2593 [VMEXIT_EXCEPTION_DF] = "EXCEPTION_DF",
2594 [VMEXIT_EXCEPTION_09] = "EXCEPTION_09",
2595 [VMEXIT_EXCEPTION_TS] = "EXCEPTION_TS",
2596 [VMEXIT_EXCEPTION_NP] = "EXCEPTION_NP",
2597 [VMEXIT_EXCEPTION_SS] = "EXCEPTION_SS",
2598 [VMEXIT_EXCEPTION_GP] = "EXCEPTION_GP",
2599 [VMEXIT_EXCEPTION_PF] = "EXCEPTION_PF",
2600 [VMEXIT_EXCEPTION_15] = "EXCEPTION_15",
2601 [VMEXIT_EXCEPTION_MF] = "EXCEPTION_MF",
2602 [VMEXIT_EXCEPTION_AC] = "EXCEPTION_AC",
2603 [VMEXIT_EXCEPTION_MC] = "EXCEPTION_MC",
2604 [VMEXIT_EXCEPTION_XF] = "EXCEPTION_XF",
2605 [VMEXIT_INTR] = "INTR",
2606 [VMEXIT_NMI] = "NMI",
2607 [VMEXIT_SMI] = "SMI",
2608 [VMEXIT_INIT] = "INIT",
2609 [VMEXIT_VINTR] = "VINTR",
2610 [VMEXIT_CR0_SEL_WRITE] = "CR0_SEL_WRITE",
2611 [VMEXIT_IDTR_READ] = "IDTR_READ",
2612 [VMEXIT_GDTR_READ] = "GDTR_READ",
2613 [VMEXIT_LDTR_READ] = "LDTR_READ",
2614 [VMEXIT_TR_READ] = "TR_READ",
2615 [VMEXIT_IDTR_WRITE] = "IDTR_WRITE",
2616 [VMEXIT_GDTR_WRITE] = "GDTR_WRITE",
2617 [VMEXIT_LDTR_WRITE] = "LDTR_WRITE",
2618 [VMEXIT_TR_WRITE] = "TR_WRITE",
2619 [VMEXIT_RDTSC] = "RDTSC",
2620 [VMEXIT_RDPMC] = "RDPMC",
2621 [VMEXIT_PUSHF] = "PUSHF",
2622 [VMEXIT_POPF] = "POPF",
2623 [VMEXIT_CPUID] = "CPUID",
2624 [VMEXIT_RSM] = "RSM",
2625 [VMEXIT_IRET] = "IRET",
2626 [VMEXIT_SWINT] = "SWINT",
2627 [VMEXIT_INVD] = "INVD",
2628 [VMEXIT_PAUSE] = "PAUSE",
2629 [VMEXIT_HLT] = "HLT",
2630 [VMEXIT_INVLPG] = "INVLPG",
2631 [VMEXIT_INVLPGA] = "INVLPGA",
2632 [VMEXIT_IOIO] = "IOIO",
2633 [VMEXIT_MSR] = "MSR",
2634 [VMEXIT_TASK_SWITCH] = "TASK_SWITCH",
2635 [VMEXIT_FERR_FREEZE] = "FERR_FREEZE",
2636 [VMEXIT_SHUTDOWN] = "SHUTDOWN",
2637 [VMEXIT_VMRUN] = "VMRUN",
2638 [VMEXIT_VMMCALL] = "VMMCALL",
2639 [VMEXIT_VMLOAD] = "VMLOAD",
2640 [VMEXIT_VMSAVE] = "VMSAVE",
2641 [VMEXIT_STGI] = "STGI",
2642 [VMEXIT_CLGI] = "CLGI",
2643 [VMEXIT_SKINIT] = "SKINIT",
2644 [VMEXIT_RDTSCP] = "RDTSCP",
2645 [VMEXIT_ICEBP] = "ICEBP",
2646 [VMEXIT_NPF] = "NPF"
2647 };
2648 #endif /* SVM_EXTRA_DEBUG */
2650 #ifdef SVM_WALK_GUEST_PAGES
2651 void walk_shadow_and_guest_pt(unsigned long gva)
2653 l2_pgentry_t gpde;
2654 l2_pgentry_t spde;
2655 l1_pgentry_t gpte;
2656 l1_pgentry_t spte;
2657 struct vcpu *v = current;
2658 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2659 paddr_t gpa;
2661 gpa = paging_gva_to_gpa(current, gva);
2662 printk("gva = %lx, gpa=%"PRIpaddr", gCR3=%x\n", gva, gpa, (u32)vmcb->cr3);
2663 if( !svm_paging_enabled(v) || mmio_space(gpa) )
2664 return;
2666 /* let's dump the guest and shadow page info */
2668 __guest_get_l2e(v, gva, &gpde);
2669 printk( "G-PDE = %x, flags=%x\n", gpde.l2, l2e_get_flags(gpde) );
2670 __shadow_get_l2e( v, gva, &spde );
2671 printk( "S-PDE = %x, flags=%x\n", spde.l2, l2e_get_flags(spde) );
2673 if ( unlikely(!(l2e_get_flags(gpde) & _PAGE_PRESENT)) )
2674 return;
2676 spte = l1e_empty();
2678 /* This is actually overkill - we only need to ensure the hl2 is in-sync.*/
2679 shadow_sync_va(v, gva);
2681 gpte.l1 = 0;
2682 __copy_from_user(&gpte, &__linear_l1_table[ l1_linear_offset(gva) ],
2683 sizeof(gpte) );
2684 printk( "G-PTE = %x, flags=%x\n", gpte.l1, l1e_get_flags(gpte) );
2686 BUG(); // need to think about this, and convert usage of
2687 // phys_to_machine_mapping to use pagetable format...
2688 __copy_from_user( &spte, &phys_to_machine_mapping[ l1e_get_pfn( gpte ) ],
2689 sizeof(spte) );
2691 printk( "S-PTE = %x, flags=%x\n", spte.l1, l1e_get_flags(spte));
2693 #endif /* SVM_WALK_GUEST_PAGES */
2696 asmlinkage void svm_vmexit_handler(struct cpu_user_regs *regs)
2698 unsigned int exit_reason;
2699 unsigned long eip;
2700 struct vcpu *v = current;
2701 int error;
2702 int do_debug = 0;
2703 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2705 ASSERT(vmcb);
2707 exit_reason = vmcb->exitcode;
2708 save_svm_cpu_user_regs(v, regs);
2710 if (exit_reason == VMEXIT_INVALID)
2712 svm_dump_vmcb(__func__, vmcb);
2713 goto exit_and_crash;
2716 #ifdef SVM_EXTRA_DEBUG
2718 #if defined(__i386__)
2719 #define rip eip
2720 #endif
2722 static unsigned long intercepts_counter = 0;
2724 if (svm_dbg_on && exit_reason == VMEXIT_EXCEPTION_PF)
2726 if (svm_paging_enabled(v) &&
2727 !mmio_space(paging_gva_to_gpa(current, vmcb->exitinfo2)))
2729 printk("I%08ld,ExC=%s(%d),IP=%x:%"PRIx64","
2730 "I1=%"PRIx64",I2=%"PRIx64",INT=%"PRIx64", "
2731 "gpa=%"PRIx64"\n", intercepts_counter,
2732 exit_reasons[exit_reason], exit_reason, regs->cs,
2733 (u64)regs->rip,
2734 (u64)vmcb->exitinfo1,
2735 (u64)vmcb->exitinfo2,
2736 (u64)vmcb->exitintinfo.bytes,
2737 (u64)paging_gva_to_gpa(current, vmcb->exitinfo2));
2739 else
2741 printk("I%08ld,ExC=%s(%d),IP=%x:%"PRIx64","
2742 "I1=%"PRIx64",I2=%"PRIx64",INT=%"PRIx64"\n",
2743 intercepts_counter,
2744 exit_reasons[exit_reason], exit_reason, regs->cs,
2745 (u64)regs->rip,
2746 (u64)vmcb->exitinfo1,
2747 (u64)vmcb->exitinfo2,
2748 (u64)vmcb->exitintinfo.bytes );
2751 else if ( svm_dbg_on
2752 && exit_reason != VMEXIT_IOIO
2753 && exit_reason != VMEXIT_INTR)
2756 if (exit_reasons[exit_reason])
2758 printk("I%08ld,ExC=%s(%d),IP=%x:%"PRIx64","
2759 "I1=%"PRIx64",I2=%"PRIx64",INT=%"PRIx64"\n",
2760 intercepts_counter,
2761 exit_reasons[exit_reason], exit_reason, regs->cs,
2762 (u64)regs->rip,
2763 (u64)vmcb->exitinfo1,
2764 (u64)vmcb->exitinfo2,
2765 (u64)vmcb->exitintinfo.bytes);
2767 else
2769 printk("I%08ld,ExC=%d(0x%x),IP=%x:%"PRIx64","
2770 "I1=%"PRIx64",I2=%"PRIx64",INT=%"PRIx64"\n",
2771 intercepts_counter, exit_reason, exit_reason, regs->cs,
2772 (u64)regs->rip,
2773 (u64)vmcb->exitinfo1,
2774 (u64)vmcb->exitinfo2,
2775 (u64)vmcb->exitintinfo.bytes);
2779 #ifdef SVM_WALK_GUEST_PAGES
2780 if( exit_reason == VMEXIT_EXCEPTION_PF
2781 && ( ( vmcb->exitinfo2 == vmcb->rip )
2782 || vmcb->exitintinfo.bytes) )
2784 if ( svm_paging_enabled(v) &&
2785 !mmio_space(gva_to_gpa(vmcb->exitinfo2)) )
2786 walk_shadow_and_guest_pt(vmcb->exitinfo2);
2788 #endif
2790 intercepts_counter++;
2792 #if 0
2793 if (svm_dbg_on)
2794 do_debug = svm_do_debugout(exit_reason);
2795 #endif
2797 if (do_debug)
2799 printk("%s:+ guest_table = 0x%08x, monitor_table = 0x%08x, "
2800 "hw_cr3 = 0x%16lx\n",
2801 __func__,
2802 (int) v->arch.guest_table.pfn,
2803 (int) v->arch.monitor_table.pfn,
2804 (long unsigned int) v->arch.hvm_vcpu.hw_cr3);
2806 svm_dump_vmcb(__func__, vmcb);
2807 svm_dump_regs(__func__, regs);
2808 svm_dump_inst(svm_rip2pointer(vmcb));
2811 #if defined(__i386__)
2812 #undef rip
2813 #endif
2816 #endif /* SVM_EXTRA_DEBUG */
2819 perfc_incra(svmexits, exit_reason);
2820 eip = vmcb->rip;
2822 #ifdef SVM_EXTRA_DEBUG
2823 if (do_debug)
2825 printk("eip = %lx, exit_reason = %d (0x%x)\n",
2826 eip, exit_reason, exit_reason);
2828 #endif /* SVM_EXTRA_DEBUG */
2830 TRACE_3D(TRC_VMX_VMEXIT, v->domain->domain_id, eip, exit_reason);
2832 switch (exit_reason)
2834 case VMEXIT_EXCEPTION_DB:
2836 #ifdef XEN_DEBUGGER
2837 svm_debug_save_cpu_user_regs(regs);
2838 pdb_handle_exception(1, regs, 1);
2839 svm_debug_restore_cpu_user_regs(regs);
2840 #else
2841 svm_store_cpu_user_regs(regs, v);
2842 domain_pause_for_debugger();
2843 #endif
2845 break;
2847 case VMEXIT_INTR:
2848 case VMEXIT_NMI:
2849 case VMEXIT_SMI:
2850 /* Asynchronous events, handled when we STGI'd after the VMEXIT. */
2851 break;
2853 case VMEXIT_INIT:
2854 BUG(); /* unreachable */
2856 case VMEXIT_EXCEPTION_BP:
2857 #ifdef XEN_DEBUGGER
2858 svm_debug_save_cpu_user_regs(regs);
2859 pdb_handle_exception(3, regs, 1);
2860 svm_debug_restore_cpu_user_regs(regs);
2861 #else
2862 if ( test_bit(_DOMF_debugging, &v->domain->domain_flags) )
2863 domain_pause_for_debugger();
2864 else
2865 svm_inject_exception(v, TRAP_int3, 0, 0);
2866 #endif
2867 break;
2869 case VMEXIT_EXCEPTION_NM:
2870 svm_do_no_device_fault(vmcb);
2871 break;
2873 case VMEXIT_EXCEPTION_GP:
2874 /* This should probably not be trapped in the future */
2875 regs->error_code = vmcb->exitinfo1;
2876 svm_do_general_protection_fault(v, regs);
2877 break;
2879 case VMEXIT_EXCEPTION_PF:
2881 unsigned long va;
2882 va = vmcb->exitinfo2;
2883 regs->error_code = vmcb->exitinfo1;
2884 HVM_DBG_LOG(DBG_LEVEL_VMMU,
2885 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
2886 (unsigned long)regs->eax, (unsigned long)regs->ebx,
2887 (unsigned long)regs->ecx, (unsigned long)regs->edx,
2888 (unsigned long)regs->esi, (unsigned long)regs->edi);
2890 if (!(error = svm_do_page_fault(va, regs)))
2892 /* Inject #PG using Interruption-Information Fields */
2893 svm_inject_exception(v, TRAP_page_fault, 1, regs->error_code);
2895 v->arch.hvm_svm.cpu_cr2 = va;
2896 vmcb->cr2 = va;
2897 TRACE_3D(TRC_VMX_INTR, v->domain->domain_id,
2898 VMEXIT_EXCEPTION_PF, va);
2900 break;
2903 case VMEXIT_EXCEPTION_DF:
2904 /* Debug info to hopefully help debug WHY the guest double-faulted. */
2905 svm_dump_vmcb(__func__, vmcb);
2906 svm_dump_regs(__func__, regs);
2907 svm_dump_inst(svm_rip2pointer(vmcb));
2908 svm_inject_exception(v, TRAP_double_fault, 1, 0);
2909 break;
2911 case VMEXIT_VINTR:
2912 vmcb->vintr.fields.irq = 0;
2913 vmcb->general1_intercepts &= ~GENERAL1_INTERCEPT_VINTR;
2914 break;
2916 case VMEXIT_INVD:
2917 svm_vmexit_do_invd(vmcb);
2918 break;
2920 case VMEXIT_GDTR_WRITE:
2921 printk("WRITE to GDTR\n");
2922 break;
2924 case VMEXIT_TASK_SWITCH:
2925 goto exit_and_crash;
2927 case VMEXIT_CPUID:
2928 svm_vmexit_do_cpuid(vmcb, regs);
2929 break;
2931 case VMEXIT_HLT:
2932 svm_vmexit_do_hlt(vmcb);
2933 break;
2935 case VMEXIT_INVLPG:
2936 svm_handle_invlpg(0, regs);
2937 break;
2939 case VMEXIT_INVLPGA:
2940 svm_handle_invlpg(1, regs);
2941 break;
2943 case VMEXIT_VMMCALL:
2944 svm_do_vmmcall(v, regs);
2945 break;
2947 case VMEXIT_CR0_READ:
2948 svm_cr_access(v, 0, TYPE_MOV_FROM_CR, regs);
2949 break;
2951 case VMEXIT_CR2_READ:
2952 svm_cr_access(v, 2, TYPE_MOV_FROM_CR, regs);
2953 break;
2955 case VMEXIT_CR3_READ:
2956 svm_cr_access(v, 3, TYPE_MOV_FROM_CR, regs);
2957 break;
2959 case VMEXIT_CR4_READ:
2960 svm_cr_access(v, 4, TYPE_MOV_FROM_CR, regs);
2961 break;
2963 case VMEXIT_CR8_READ:
2964 svm_cr_access(v, 8, TYPE_MOV_FROM_CR, regs);
2965 break;
2967 case VMEXIT_CR0_WRITE:
2968 svm_cr_access(v, 0, TYPE_MOV_TO_CR, regs);
2969 break;
2971 case VMEXIT_CR2_WRITE:
2972 svm_cr_access(v, 2, TYPE_MOV_TO_CR, regs);
2973 break;
2975 case VMEXIT_CR3_WRITE:
2976 svm_cr_access(v, 3, TYPE_MOV_TO_CR, regs);
2977 local_flush_tlb();
2978 break;
2980 case VMEXIT_CR4_WRITE:
2981 svm_cr_access(v, 4, TYPE_MOV_TO_CR, regs);
2982 break;
2984 case VMEXIT_CR8_WRITE:
2985 svm_cr_access(v, 8, TYPE_MOV_TO_CR, regs);
2986 break;
2988 case VMEXIT_DR0_WRITE ... VMEXIT_DR7_WRITE:
2989 svm_dr_access(v, regs);
2990 break;
2992 case VMEXIT_IOIO:
2993 svm_io_instruction(v);
2994 break;
2996 case VMEXIT_MSR:
2997 svm_do_msr_access(v, regs);
2998 break;
3000 case VMEXIT_SHUTDOWN:
3001 hvm_triple_fault();
3002 break;
3004 default:
3005 exit_and_crash:
3006 gdprintk(XENLOG_ERR, "unexpected VMEXIT: exit reason = 0x%x, "
3007 "exitinfo1 = %"PRIx64", exitinfo2 = %"PRIx64"\n",
3008 exit_reason,
3009 (u64)vmcb->exitinfo1, (u64)vmcb->exitinfo2);
3010 domain_crash(v->domain);
3011 break;
3014 #ifdef SVM_EXTRA_DEBUG
3015 if (do_debug)
3017 printk("%s: Done switch on vmexit_code\n", __func__);
3018 svm_dump_regs(__func__, regs);
3021 if (do_debug)
3023 printk("vmexit_handler():- guest_table = 0x%08x, "
3024 "monitor_table = 0x%08x, hw_cr3 = 0x%16x\n",
3025 (int)v->arch.guest_table.pfn,
3026 (int)v->arch.monitor_table.pfn,
3027 (int)v->arch.hvm_vcpu.hw_cr3);
3028 printk("svm_vmexit_handler: Returning\n");
3030 #endif
3033 asmlinkage void svm_load_cr2(void)
3035 struct vcpu *v = current;
3037 local_irq_disable();
3038 asm volatile("mov %0,%%cr2": :"r" (v->arch.hvm_svm.cpu_cr2));
3041 /*
3042 * Local variables:
3043 * mode: C
3044 * c-set-style: "BSD"
3045 * c-basic-offset: 4
3046 * tab-width: 4
3047 * indent-tabs-mode: nil
3048 * End:
3049 */