ia64/xen-unstable

view xen/include/asm-x86/hvm/vmx/vmx.h @ 16468:9f61a0add5b6

x86_emulate: Emulate CPUID and HLT.
vmx realmode: Fix decode & emulate loop, add hooks for CPUID, HLT and
WBINVD. Also do not hook realmode entry off of vmentry failure any
more.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Mon Nov 26 15:32:54 2007 +0000 (2007-11-26)
parents 368bcf480772
children 11bfa26dd125
line source
1 /*
2 * vmx.h: VMX Architecture related definitions
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 #ifndef __ASM_X86_HVM_VMX_VMX_H__
20 #define __ASM_X86_HVM_VMX_VMX_H__
22 #include <xen/sched.h>
23 #include <asm/types.h>
24 #include <asm/regs.h>
25 #include <asm/processor.h>
26 #include <asm/hvm/vmx/vmcs.h>
27 #include <asm/i387.h>
28 #include <asm/hvm/trace.h>
30 void vmx_asm_vmexit_handler(struct cpu_user_regs);
31 void vmx_asm_do_vmentry(void);
32 void vmx_intr_assist(void);
33 void vmx_do_resume(struct vcpu *);
34 void set_guest_time(struct vcpu *v, u64 gtime);
35 void vmx_vlapic_msr_changed(struct vcpu *v);
36 void vmx_cpuid_intercept(
37 unsigned int *eax, unsigned int *ebx,
38 unsigned int *ecx, unsigned int *edx);
39 void vmx_wbinvd_intercept(void);
40 int vmx_realmode(struct cpu_user_regs *regs);
41 int vmx_realmode_io_complete(void);
43 /*
44 * Exit Reasons
45 */
46 #define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
48 #define EXIT_REASON_EXCEPTION_NMI 0
49 #define EXIT_REASON_EXTERNAL_INTERRUPT 1
50 #define EXIT_REASON_TRIPLE_FAULT 2
51 #define EXIT_REASON_INIT 3
52 #define EXIT_REASON_SIPI 4
53 #define EXIT_REASON_IO_SMI 5
54 #define EXIT_REASON_OTHER_SMI 6
55 #define EXIT_REASON_PENDING_VIRT_INTR 7
56 #define EXIT_REASON_PENDING_VIRT_NMI 8
57 #define EXIT_REASON_TASK_SWITCH 9
58 #define EXIT_REASON_CPUID 10
59 #define EXIT_REASON_HLT 12
60 #define EXIT_REASON_INVD 13
61 #define EXIT_REASON_INVLPG 14
62 #define EXIT_REASON_RDPMC 15
63 #define EXIT_REASON_RDTSC 16
64 #define EXIT_REASON_RSM 17
65 #define EXIT_REASON_VMCALL 18
66 #define EXIT_REASON_VMCLEAR 19
67 #define EXIT_REASON_VMLAUNCH 20
68 #define EXIT_REASON_VMPTRLD 21
69 #define EXIT_REASON_VMPTRST 22
70 #define EXIT_REASON_VMREAD 23
71 #define EXIT_REASON_VMRESUME 24
72 #define EXIT_REASON_VMWRITE 25
73 #define EXIT_REASON_VMXOFF 26
74 #define EXIT_REASON_VMXON 27
75 #define EXIT_REASON_CR_ACCESS 28
76 #define EXIT_REASON_DR_ACCESS 29
77 #define EXIT_REASON_IO_INSTRUCTION 30
78 #define EXIT_REASON_MSR_READ 31
79 #define EXIT_REASON_MSR_WRITE 32
80 #define EXIT_REASON_INVALID_GUEST_STATE 33
81 #define EXIT_REASON_MSR_LOADING 34
82 #define EXIT_REASON_MWAIT_INSTRUCTION 36
83 #define EXIT_REASON_MONITOR_INSTRUCTION 39
84 #define EXIT_REASON_PAUSE_INSTRUCTION 40
85 #define EXIT_REASON_MACHINE_CHECK 41
86 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
87 #define EXIT_REASON_APIC_ACCESS 44
88 #define EXIT_REASON_WBINVD 54
90 /*
91 * Interruption-information format
92 */
93 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
94 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
95 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
96 #define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x1000 /* 12 */
97 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
98 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
100 /*
101 * Exit Qualifications for MOV for Control Register Access
102 */
103 #define CONTROL_REG_ACCESS_NUM 0xf /* 3:0, number of control register */
104 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
105 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose register */
106 #define LMSW_SOURCE_DATA (0xFFFF << 16) /* 16:31 lmsw source */
107 #define REG_EAX (0 << 8)
108 #define REG_ECX (1 << 8)
109 #define REG_EDX (2 << 8)
110 #define REG_EBX (3 << 8)
111 #define REG_ESP (4 << 8)
112 #define REG_EBP (5 << 8)
113 #define REG_ESI (6 << 8)
114 #define REG_EDI (7 << 8)
115 #define REG_R8 (8 << 8)
116 #define REG_R9 (9 << 8)
117 #define REG_R10 (10 << 8)
118 #define REG_R11 (11 << 8)
119 #define REG_R12 (12 << 8)
120 #define REG_R13 (13 << 8)
121 #define REG_R14 (14 << 8)
122 #define REG_R15 (15 << 8)
124 /*
125 * Exit Qualifications for MOV for Debug Register Access
126 */
127 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug register */
128 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
129 #define TYPE_MOV_TO_DR (0 << 4)
130 #define TYPE_MOV_FROM_DR (1 << 4)
131 #define DEBUG_REG_ACCESS_REG 0xf00 /* 11:8, general purpose register */
133 /*
134 * Access Rights
135 */
136 #define X86_SEG_AR_SEG_TYPE 0xf /* 3:0, segment type */
137 #define X86_SEG_AR_DESC_TYPE (1u << 4) /* 4, descriptor type */
138 #define X86_SEG_AR_DPL 0x60 /* 6:5, descriptor privilege level */
139 #define X86_SEG_AR_SEG_PRESENT (1u << 7) /* 7, segment present */
140 #define X86_SEG_AR_AVL (1u << 12) /* 12, available for system software */
141 #define X86_SEG_AR_CS_LM_ACTIVE (1u << 13) /* 13, long mode active (CS only) */
142 #define X86_SEG_AR_DEF_OP_SIZE (1u << 14) /* 14, default operation size */
143 #define X86_SEG_AR_GRANULARITY (1u << 15) /* 15, granularity */
144 #define X86_SEG_AR_SEG_UNUSABLE (1u << 16) /* 16, segment unusable */
146 #define VMCALL_OPCODE ".byte 0x0f,0x01,0xc1\n"
147 #define VMCLEAR_OPCODE ".byte 0x66,0x0f,0xc7\n" /* reg/opcode: /6 */
148 #define VMLAUNCH_OPCODE ".byte 0x0f,0x01,0xc2\n"
149 #define VMPTRLD_OPCODE ".byte 0x0f,0xc7\n" /* reg/opcode: /6 */
150 #define VMPTRST_OPCODE ".byte 0x0f,0xc7\n" /* reg/opcode: /7 */
151 #define VMREAD_OPCODE ".byte 0x0f,0x78\n"
152 #define VMRESUME_OPCODE ".byte 0x0f,0x01,0xc3\n"
153 #define VMWRITE_OPCODE ".byte 0x0f,0x79\n"
154 #define VMXOFF_OPCODE ".byte 0x0f,0x01,0xc4\n"
155 #define VMXON_OPCODE ".byte 0xf3,0x0f,0xc7\n"
157 #define MODRM_EAX_06 ".byte 0x30\n" /* [EAX], with reg/opcode: /6 */
158 #define MODRM_EAX_07 ".byte 0x38\n" /* [EAX], with reg/opcode: /7 */
159 #define MODRM_EAX_ECX ".byte 0xc1\n" /* [EAX], [ECX] */
161 static inline void __vmptrld(u64 addr)
162 {
163 __asm__ __volatile__ ( VMPTRLD_OPCODE
164 MODRM_EAX_06
165 /* CF==1 or ZF==1 --> crash (ud2) */
166 "ja 1f ; ud2 ; 1:\n"
167 :
168 : "a" (&addr)
169 : "memory");
170 }
172 static inline void __vmptrst(u64 addr)
173 {
174 __asm__ __volatile__ ( VMPTRST_OPCODE
175 MODRM_EAX_07
176 :
177 : "a" (&addr)
178 : "memory");
179 }
181 static inline void __vmpclear(u64 addr)
182 {
183 __asm__ __volatile__ ( VMCLEAR_OPCODE
184 MODRM_EAX_06
185 /* CF==1 or ZF==1 --> crash (ud2) */
186 "ja 1f ; ud2 ; 1:\n"
187 :
188 : "a" (&addr)
189 : "memory");
190 }
192 static inline unsigned long __vmread(unsigned long field)
193 {
194 unsigned long ecx;
196 __asm__ __volatile__ ( VMREAD_OPCODE
197 MODRM_EAX_ECX
198 /* CF==1 or ZF==1 --> crash (ud2) */
199 "ja 1f ; ud2 ; 1:\n"
200 : "=c" (ecx)
201 : "a" (field)
202 : "memory");
204 return ecx;
205 }
207 static inline void __vmwrite(unsigned long field, unsigned long value)
208 {
209 __asm__ __volatile__ ( VMWRITE_OPCODE
210 MODRM_EAX_ECX
211 /* CF==1 or ZF==1 --> crash (ud2) */
212 "ja 1f ; ud2 ; 1:\n"
213 :
214 : "a" (field) , "c" (value)
215 : "memory");
216 }
218 static inline unsigned long __vmread_safe(unsigned long field, int *error)
219 {
220 unsigned long ecx;
222 __asm__ __volatile__ ( VMREAD_OPCODE
223 MODRM_EAX_ECX
224 /* CF==1 or ZF==1 --> rc = -1 */
225 "setna %b0 ; neg %0"
226 : "=q" (*error), "=c" (ecx)
227 : "0" (0), "a" (field)
228 : "memory");
230 return ecx;
231 }
233 static inline void __vm_set_bit(unsigned long field, unsigned int bit)
234 {
235 __vmwrite(field, __vmread(field) | (1UL << bit));
236 }
238 static inline void __vm_clear_bit(unsigned long field, unsigned int bit)
239 {
240 __vmwrite(field, __vmread(field) & ~(1UL << bit));
241 }
243 static inline void __vmxoff (void)
244 {
245 __asm__ __volatile__ ( VMXOFF_OPCODE
246 ::: "memory");
247 }
249 static inline int __vmxon (u64 addr)
250 {
251 int rc;
253 __asm__ __volatile__ ( VMXON_OPCODE
254 MODRM_EAX_06
255 /* CF==1 or ZF==1 --> rc = -1 */
256 "setna %b0 ; neg %0"
257 : "=q" (rc)
258 : "0" (0), "a" (&addr)
259 : "memory");
261 return rc;
262 }
264 static inline void __vmx_inject_exception(
265 struct vcpu *v, int trap, int type, int error_code)
266 {
267 unsigned long intr_fields;
269 /*
270 * NB. Callers do not need to worry about clearing STI/MOV-SS blocking:
271 * "If the VM entry is injecting, there is no blocking by STI or by
272 * MOV SS following the VM entry, regardless of the contents of the
273 * interruptibility-state field [in the guest-state area before the
274 * VM entry]", PRM Vol. 3, 22.6.1 (Interruptibility State).
275 */
277 intr_fields = (INTR_INFO_VALID_MASK | (type<<8) | trap);
278 if ( error_code != HVM_DELIVER_NO_ERROR_CODE ) {
279 __vmwrite(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
280 intr_fields |= INTR_INFO_DELIVER_CODE_MASK;
281 }
283 __vmwrite(VM_ENTRY_INTR_INFO, intr_fields);
285 if ( trap == TRAP_page_fault )
286 HVMTRACE_2D(PF_INJECT, v, v->arch.hvm_vcpu.guest_cr[2], error_code);
287 else
288 HVMTRACE_2D(INJ_EXC, v, trap, error_code);
289 }
291 static inline void vmx_inject_hw_exception(
292 struct vcpu *v, int trap, int error_code)
293 {
294 __vmx_inject_exception(v, trap, X86_EVENTTYPE_HW_EXCEPTION, error_code);
295 }
297 static inline void vmx_inject_extint(struct vcpu *v, int trap)
298 {
299 __vmx_inject_exception(v, trap, X86_EVENTTYPE_EXT_INTR,
300 HVM_DELIVER_NO_ERROR_CODE);
301 }
303 static inline void vmx_inject_nmi(struct vcpu *v)
304 {
305 __vmx_inject_exception(v, 2, X86_EVENTTYPE_NMI,
306 HVM_DELIVER_NO_ERROR_CODE);
307 }
309 #endif /* __ASM_X86_HVM_VMX_VMX_H__ */