ia64/xen-unstable

view xen/arch/x86/pci-pc.c @ 1589:9eda3ea2b4a0

bitkeeper revision 1.1019 (40de8639yjRdZbQS_JrcVsHsaPIwZw)

smp.h, irq.h, config.h, sched_bvt.c, setup.c, pci-pc.c:
Fix compile errors for latest GCC (3.4.0).
author kaf24@scramble.cl.cam.ac.uk
date Sun Jun 27 08:32:57 2004 +0000 (2004-06-27)
parents da46c0d041f1
children 42f37b71f9b1 dae98734f12e
line source
1 /*
2 * Low-Level PCI Support for PC
3 *
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
5 */
7 #include <xen/config.h>
8 #include <xen/types.h>
9 #include <xen/kernel.h>
10 #include <xen/sched.h>
11 #include <xen/pci.h>
12 #include <xen/init.h>
13 #include <xen/ioport.h>
14 #include <xen/acpi.h>
16 /*#include <asm/segment.h>*/
17 #include <asm/io.h>
18 #include <asm/smp.h>
19 #include <asm/smpboot.h>
21 #include "pci-x86.h"
23 extern int numnodes;
24 #define __KERNEL_CS __HYPERVISOR_CS
25 #define __KERNEL_DS __HYPERVISOR_DS
27 unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2;
29 int pcibios_last_bus = -1;
30 struct pci_bus *pci_root_bus = NULL;
31 struct pci_ops *pci_root_ops = NULL;
33 int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value) = NULL;
34 int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value) = NULL;
36 static int pci_using_acpi_prt = 0;
38 #ifdef CONFIG_MULTIQUAD
39 #define BUS2QUAD(global) (mp_bus_id_to_node[global])
40 #define BUS2LOCAL(global) (mp_bus_id_to_local[global])
41 #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
42 #else
43 #define BUS2QUAD(global) (0)
44 #define BUS2LOCAL(global) (global)
45 #define QUADLOCAL2BUS(quad,local) (local)
46 #endif
48 /*
49 * This interrupt-safe spinlock protects all accesses to PCI
50 * configuration space.
51 */
52 static spinlock_t pci_config_lock = SPIN_LOCK_UNLOCKED;
55 /*
56 * Functions for accessing PCI configuration space with type 1 accesses
57 */
59 #ifdef CONFIG_PCI_DIRECT
61 #ifdef CONFIG_MULTIQUAD
62 #define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
63 (0x80000000 | (BUS2LOCAL(bus) << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
65 static int pci_conf1_mq_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) /* CONFIG_MULTIQUAD */
66 {
67 unsigned long flags;
69 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
70 return -EINVAL;
72 spin_lock_irqsave(&pci_config_lock, flags);
74 outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus));
76 switch (len) {
77 case 1:
78 *value = inb_quad(0xCFC + (reg & 3), BUS2QUAD(bus));
79 break;
80 case 2:
81 *value = inw_quad(0xCFC + (reg & 2), BUS2QUAD(bus));
82 break;
83 case 4:
84 *value = inl_quad(0xCFC, BUS2QUAD(bus));
85 break;
86 }
88 spin_unlock_irqrestore(&pci_config_lock, flags);
90 return 0;
91 }
93 static int pci_conf1_mq_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) /* CONFIG_MULTIQUAD */
94 {
95 unsigned long flags;
97 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
98 return -EINVAL;
100 spin_lock_irqsave(&pci_config_lock, flags);
102 outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus));
104 switch (len) {
105 case 1:
106 outb_quad((u8)value, 0xCFC + (reg & 3), BUS2QUAD(bus));
107 break;
108 case 2:
109 outw_quad((u16)value, 0xCFC + (reg & 2), BUS2QUAD(bus));
110 break;
111 case 4:
112 outl_quad((u32)value, 0xCFC, BUS2QUAD(bus));
113 break;
114 }
116 spin_unlock_irqrestore(&pci_config_lock, flags);
118 return 0;
119 }
121 static int pci_conf1_read_mq_config_byte(struct pci_dev *dev, int where, u8 *value)
122 {
123 int result;
124 u32 data;
126 result = pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
127 PCI_FUNC(dev->devfn), where, 1, &data);
129 *value = (u8)data;
131 return result;
132 }
134 static int pci_conf1_read_mq_config_word(struct pci_dev *dev, int where, u16 *value)
135 {
136 int result;
137 u32 data;
139 result = pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
140 PCI_FUNC(dev->devfn), where, 2, &data);
142 *value = (u16)data;
144 return result;
145 }
147 static int pci_conf1_read_mq_config_dword(struct pci_dev *dev, int where, u32 *value)
148 {
149 if (!value)
150 return -EINVAL;
152 return pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
153 PCI_FUNC(dev->devfn), where, 4, value);
154 }
156 static int pci_conf1_write_mq_config_byte(struct pci_dev *dev, int where, u8 value)
157 {
158 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
159 PCI_FUNC(dev->devfn), where, 1, value);
160 }
162 static int pci_conf1_write_mq_config_word(struct pci_dev *dev, int where, u16 value)
163 {
164 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
165 PCI_FUNC(dev->devfn), where, 2, value);
166 }
168 static int pci_conf1_write_mq_config_dword(struct pci_dev *dev, int where, u32 value)
169 {
170 return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
171 PCI_FUNC(dev->devfn), where, 4, value);
172 }
174 static struct pci_ops pci_direct_mq_conf1 = {
175 pci_conf1_read_mq_config_byte,
176 pci_conf1_read_mq_config_word,
177 pci_conf1_read_mq_config_dword,
178 pci_conf1_write_mq_config_byte,
179 pci_conf1_write_mq_config_word,
180 pci_conf1_write_mq_config_dword
181 };
183 #endif /* !CONFIG_MULTIQUAD */
184 #define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \
185 (0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3))
187 static int pci_conf1_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) /* !CONFIG_MULTIQUAD */
188 {
189 unsigned long flags;
191 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
192 return -EINVAL;
194 spin_lock_irqsave(&pci_config_lock, flags);
196 outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
198 switch (len) {
199 case 1:
200 *value = inb(0xCFC + (reg & 3));
201 break;
202 case 2:
203 *value = inw(0xCFC + (reg & 2));
204 break;
205 case 4:
206 *value = inl(0xCFC);
207 break;
208 }
210 spin_unlock_irqrestore(&pci_config_lock, flags);
212 return 0;
213 }
215 static int pci_conf1_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) /* !CONFIG_MULTIQUAD */
216 {
217 unsigned long flags;
219 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
220 return -EINVAL;
222 spin_lock_irqsave(&pci_config_lock, flags);
224 outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8);
226 switch (len) {
227 case 1:
228 outb((u8)value, 0xCFC + (reg & 3));
229 break;
230 case 2:
231 outw((u16)value, 0xCFC + (reg & 2));
232 break;
233 case 4:
234 outl((u32)value, 0xCFC);
235 break;
236 }
238 spin_unlock_irqrestore(&pci_config_lock, flags);
240 return 0;
241 }
243 #undef PCI_CONF1_ADDRESS
245 static int pci_conf1_read_config_byte(struct pci_dev *dev, int where, u8 *value)
246 {
247 int result;
248 u32 data;
250 result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
251 PCI_FUNC(dev->devfn), where, 1, &data);
253 *value = (u8)data;
255 return result;
256 }
258 static int pci_conf1_read_config_word(struct pci_dev *dev, int where, u16 *value)
259 {
260 int result;
261 u32 data;
263 result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
264 PCI_FUNC(dev->devfn), where, 2, &data);
266 *value = (u16)data;
268 return result;
269 }
271 static int pci_conf1_read_config_dword(struct pci_dev *dev, int where, u32 *value)
272 {
273 return pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
274 PCI_FUNC(dev->devfn), where, 4, value);
275 }
277 static int pci_conf1_write_config_byte(struct pci_dev *dev, int where, u8 value)
278 {
279 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
280 PCI_FUNC(dev->devfn), where, 1, value);
281 }
283 static int pci_conf1_write_config_word(struct pci_dev *dev, int where, u16 value)
284 {
285 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
286 PCI_FUNC(dev->devfn), where, 2, value);
287 }
289 static int pci_conf1_write_config_dword(struct pci_dev *dev, int where, u32 value)
290 {
291 return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
292 PCI_FUNC(dev->devfn), where, 4, value);
293 }
295 static struct pci_ops pci_direct_conf1 = {
296 pci_conf1_read_config_byte,
297 pci_conf1_read_config_word,
298 pci_conf1_read_config_dword,
299 pci_conf1_write_config_byte,
300 pci_conf1_write_config_word,
301 pci_conf1_write_config_dword
302 };
305 /*
306 * Functions for accessing PCI configuration space with type 2 accesses
307 */
309 #define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg)
311 static int pci_conf2_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
312 {
313 unsigned long flags;
315 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
316 return -EINVAL;
318 if (dev & 0x10)
319 return PCIBIOS_DEVICE_NOT_FOUND;
321 spin_lock_irqsave(&pci_config_lock, flags);
323 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
324 outb((u8)bus, 0xCFA);
326 switch (len) {
327 case 1:
328 *value = inb(PCI_CONF2_ADDRESS(dev, reg));
329 break;
330 case 2:
331 *value = inw(PCI_CONF2_ADDRESS(dev, reg));
332 break;
333 case 4:
334 *value = inl(PCI_CONF2_ADDRESS(dev, reg));
335 break;
336 }
338 outb (0, 0xCF8);
340 spin_unlock_irqrestore(&pci_config_lock, flags);
342 return 0;
343 }
345 static int pci_conf2_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
346 {
347 unsigned long flags;
349 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
350 return -EINVAL;
352 if (dev & 0x10)
353 return PCIBIOS_DEVICE_NOT_FOUND;
355 spin_lock_irqsave(&pci_config_lock, flags);
357 outb((u8)(0xF0 | (fn << 1)), 0xCF8);
358 outb((u8)bus, 0xCFA);
360 switch (len) {
361 case 1:
362 outb ((u8)value, PCI_CONF2_ADDRESS(dev, reg));
363 break;
364 case 2:
365 outw ((u16)value, PCI_CONF2_ADDRESS(dev, reg));
366 break;
367 case 4:
368 outl ((u32)value, PCI_CONF2_ADDRESS(dev, reg));
369 break;
370 }
372 outb (0, 0xCF8);
374 spin_unlock_irqrestore(&pci_config_lock, flags);
376 return 0;
377 }
379 #undef PCI_CONF2_ADDRESS
381 static int pci_conf2_read_config_byte(struct pci_dev *dev, int where, u8 *value)
382 {
383 int result;
384 u32 data;
385 result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
386 PCI_FUNC(dev->devfn), where, 1, &data);
387 *value = (u8)data;
388 return result;
389 }
391 static int pci_conf2_read_config_word(struct pci_dev *dev, int where, u16 *value)
392 {
393 int result;
394 u32 data;
395 result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
396 PCI_FUNC(dev->devfn), where, 2, &data);
397 *value = (u16)data;
398 return result;
399 }
401 static int pci_conf2_read_config_dword(struct pci_dev *dev, int where, u32 *value)
402 {
403 return pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
404 PCI_FUNC(dev->devfn), where, 4, value);
405 }
407 static int pci_conf2_write_config_byte(struct pci_dev *dev, int where, u8 value)
408 {
409 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
410 PCI_FUNC(dev->devfn), where, 1, value);
411 }
413 static int pci_conf2_write_config_word(struct pci_dev *dev, int where, u16 value)
414 {
415 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
416 PCI_FUNC(dev->devfn), where, 2, value);
417 }
419 static int pci_conf2_write_config_dword(struct pci_dev *dev, int where, u32 value)
420 {
421 return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
422 PCI_FUNC(dev->devfn), where, 4, value);
423 }
425 static struct pci_ops pci_direct_conf2 = {
426 pci_conf2_read_config_byte,
427 pci_conf2_read_config_word,
428 pci_conf2_read_config_dword,
429 pci_conf2_write_config_byte,
430 pci_conf2_write_config_word,
431 pci_conf2_write_config_dword
432 };
435 /*
436 * Before we decide to use direct hardware access mechanisms, we try to do some
437 * trivial checks to ensure it at least _seems_ to be working -- we just test
438 * whether bus 00 contains a host bridge (this is similar to checking
439 * techniques used in XFree86, but ours should be more reliable since we
440 * attempt to make use of direct access hints provided by the PCI BIOS).
441 *
442 * This should be close to trivial, but it isn't, because there are buggy
443 * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
444 */
445 static int __devinit pci_sanity_check(struct pci_ops *o)
446 {
447 u16 x;
448 struct pci_bus bus; /* Fake bus and device */
449 struct pci_dev dev;
451 if (pci_probe & PCI_NO_CHECKS)
452 return 1;
453 bus.number = 0;
454 dev.bus = &bus;
455 for(dev.devfn=0; dev.devfn < 0x100; dev.devfn++)
456 if ((!o->read_word(&dev, PCI_CLASS_DEVICE, &x) &&
457 (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
458 (!o->read_word(&dev, PCI_VENDOR_ID, &x) &&
459 (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
460 return 1;
461 DBG("PCI: Sanity check failed\n");
462 return 0;
463 }
465 static struct pci_ops * __devinit pci_check_direct(void)
466 {
467 unsigned int tmp;
468 unsigned long flags;
470 __save_flags(flags); __cli();
472 /*
473 * Check if configuration type 1 works.
474 */
475 if (pci_probe & PCI_PROBE_CONF1) {
476 outb (0x01, 0xCFB);
477 tmp = inl (0xCF8);
478 outl (0x80000000, 0xCF8);
479 if (inl (0xCF8) == 0x80000000 &&
480 pci_sanity_check(&pci_direct_conf1)) {
481 outl (tmp, 0xCF8);
482 __restore_flags(flags);
483 printk(KERN_INFO "PCI: Using configuration type 1\n");
484 request_region(0xCF8, 8, "PCI conf1");
486 #ifdef CONFIG_MULTIQUAD
487 /* Multi-Quad has an extended PCI Conf1 */
488 if(clustered_apic_mode == CLUSTERED_APIC_NUMAQ)
489 return &pci_direct_mq_conf1;
490 #endif
491 return &pci_direct_conf1;
492 }
493 outl (tmp, 0xCF8);
494 }
496 /*
497 * Check if configuration type 2 works.
498 */
499 if (pci_probe & PCI_PROBE_CONF2) {
500 outb (0x00, 0xCFB);
501 outb (0x00, 0xCF8);
502 outb (0x00, 0xCFA);
503 if (inb (0xCF8) == 0x00 && inb (0xCFA) == 0x00 &&
504 pci_sanity_check(&pci_direct_conf2)) {
505 __restore_flags(flags);
506 printk(KERN_INFO "PCI: Using configuration type 2\n");
507 request_region(0xCF8, 4, "PCI conf2");
508 return &pci_direct_conf2;
509 }
510 }
512 __restore_flags(flags);
513 return NULL;
514 }
516 #endif
518 /*
519 * BIOS32 and PCI BIOS handling.
520 */
522 #ifdef CONFIG_PCI_BIOS
524 #define PCIBIOS_PCI_FUNCTION_ID 0xb1XX
525 #define PCIBIOS_PCI_BIOS_PRESENT 0xb101
526 #define PCIBIOS_FIND_PCI_DEVICE 0xb102
527 #define PCIBIOS_FIND_PCI_CLASS_CODE 0xb103
528 #define PCIBIOS_GENERATE_SPECIAL_CYCLE 0xb106
529 #define PCIBIOS_READ_CONFIG_BYTE 0xb108
530 #define PCIBIOS_READ_CONFIG_WORD 0xb109
531 #define PCIBIOS_READ_CONFIG_DWORD 0xb10a
532 #define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
533 #define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
534 #define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
535 #define PCIBIOS_GET_ROUTING_OPTIONS 0xb10e
536 #define PCIBIOS_SET_PCI_HW_INT 0xb10f
538 /* BIOS32 signature: "_32_" */
539 #define BIOS32_SIGNATURE (('_' << 0) + ('3' << 8) + ('2' << 16) + ('_' << 24))
541 /* PCI signature: "PCI " */
542 #define PCI_SIGNATURE (('P' << 0) + ('C' << 8) + ('I' << 16) + (' ' << 24))
544 /* PCI service signature: "$PCI" */
545 #define PCI_SERVICE (('$' << 0) + ('P' << 8) + ('C' << 16) + ('I' << 24))
547 /* PCI BIOS hardware mechanism flags */
548 #define PCIBIOS_HW_TYPE1 0x01
549 #define PCIBIOS_HW_TYPE2 0x02
550 #define PCIBIOS_HW_TYPE1_SPEC 0x10
551 #define PCIBIOS_HW_TYPE2_SPEC 0x20
553 /*
554 * This is the standard structure used to identify the entry point
555 * to the BIOS32 Service Directory, as documented in
556 * Standard BIOS 32-bit Service Directory Proposal
557 * Revision 0.4 May 24, 1993
558 * Phoenix Technologies Ltd.
559 * Norwood, MA
560 * and the PCI BIOS specification.
561 */
563 union bios32 {
564 struct {
565 unsigned long signature; /* _32_ */
566 unsigned long entry; /* 32 bit physical address */
567 unsigned char revision; /* Revision level, 0 */
568 unsigned char length; /* Length in paragraphs should be 01 */
569 unsigned char checksum; /* All bytes must add up to zero */
570 unsigned char reserved[5]; /* Must be zero */
571 } fields;
572 char chars[16];
573 };
575 /*
576 * Physical address of the service directory. I don't know if we're
577 * allowed to have more than one of these or not, so just in case
578 * we'll make pcibios_present() take a memory start parameter and store
579 * the array there.
580 */
582 static struct {
583 unsigned long address;
584 unsigned short segment;
585 } bios32_indirect = { 0, __KERNEL_CS };
587 /*
588 * Returns the entry point for the given service, NULL on error
589 */
591 static unsigned long bios32_service(unsigned long service)
592 {
593 unsigned char return_code; /* %al */
594 unsigned long address; /* %ebx */
595 unsigned long length; /* %ecx */
596 unsigned long entry; /* %edx */
597 unsigned long flags;
599 __save_flags(flags); __cli();
600 __asm__("lcall *(%%edi); cld"
601 : "=a" (return_code),
602 "=b" (address),
603 "=c" (length),
604 "=d" (entry)
605 : "0" (service),
606 "1" (0),
607 "D" (&bios32_indirect));
608 __restore_flags(flags);
610 switch (return_code) {
611 case 0:
612 return address + entry;
613 case 0x80: /* Not present */
614 printk(KERN_WARNING "bios32_service(0x%lx): not present\n", service);
615 return 0;
616 default: /* Shouldn't happen */
617 printk(KERN_WARNING "bios32_service(0x%lx): returned 0x%x -- BIOS bug!\n",
618 service, return_code);
619 return 0;
620 }
621 }
623 static struct {
624 unsigned long address;
625 unsigned short segment;
626 } pci_indirect = { 0, __KERNEL_CS };
628 static int pci_bios_present;
630 static int __devinit check_pcibios(void)
631 {
632 u32 signature, eax, ebx, ecx;
633 u8 status, major_ver, minor_ver, hw_mech;
634 unsigned long flags, pcibios_entry;
636 if ((pcibios_entry = bios32_service(PCI_SERVICE))) {
637 pci_indirect.address = pcibios_entry + PAGE_OFFSET;
639 __save_flags(flags); __cli();
640 __asm__(
641 "lcall *(%%edi); cld\n\t"
642 "jc 1f\n\t"
643 "xor %%ah, %%ah\n"
644 "1:"
645 : "=d" (signature),
646 "=a" (eax),
647 "=b" (ebx),
648 "=c" (ecx)
649 : "1" (PCIBIOS_PCI_BIOS_PRESENT),
650 "D" (&pci_indirect)
651 : "memory");
652 __restore_flags(flags);
654 status = (eax >> 8) & 0xff;
655 hw_mech = eax & 0xff;
656 major_ver = (ebx >> 8) & 0xff;
657 minor_ver = ebx & 0xff;
658 if (pcibios_last_bus < 0)
659 pcibios_last_bus = ecx & 0xff;
660 DBG("PCI: BIOS probe returned s=%02x hw=%02x ver=%02x.%02x l=%02x\n",
661 status, hw_mech, major_ver, minor_ver, pcibios_last_bus);
662 if (status || signature != PCI_SIGNATURE) {
663 printk (KERN_ERR "PCI: BIOS BUG #%x[%08x] found\n",
664 status, signature);
665 return 0;
666 }
667 printk(KERN_INFO "PCI: PCI BIOS revision %x.%02x entry at 0x%lx, last bus=%d\n",
668 major_ver, minor_ver, pcibios_entry, pcibios_last_bus);
669 #ifdef CONFIG_PCI_DIRECT
670 if (!(hw_mech & PCIBIOS_HW_TYPE1))
671 pci_probe &= ~PCI_PROBE_CONF1;
672 if (!(hw_mech & PCIBIOS_HW_TYPE2))
673 pci_probe &= ~PCI_PROBE_CONF2;
674 #endif
675 return 1;
676 }
677 return 0;
678 }
680 static int __devinit pci_bios_find_device (unsigned short vendor, unsigned short device_id,
681 unsigned short index, unsigned char *bus, unsigned char *device_fn)
682 {
683 unsigned short bx;
684 unsigned short ret;
686 __asm__("lcall *(%%edi); cld\n\t"
687 "jc 1f\n\t"
688 "xor %%ah, %%ah\n"
689 "1:"
690 : "=b" (bx),
691 "=a" (ret)
692 : "1" (PCIBIOS_FIND_PCI_DEVICE),
693 "c" (device_id),
694 "d" (vendor),
695 "S" ((int) index),
696 "D" (&pci_indirect));
697 *bus = (bx >> 8) & 0xff;
698 *device_fn = bx & 0xff;
699 return (int) (ret & 0xff00) >> 8;
700 }
702 static int pci_bios_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value)
703 {
704 unsigned long result = 0;
705 unsigned long flags;
706 unsigned long bx = ((bus << 8) | (dev << 3) | fn);
708 if (bus > 255 || dev > 31 || fn > 7 || reg > 255)
709 return -EINVAL;
711 spin_lock_irqsave(&pci_config_lock, flags);
713 switch (len) {
714 case 1:
715 __asm__("lcall *(%%esi); cld\n\t"
716 "jc 1f\n\t"
717 "xor %%ah, %%ah\n"
718 "1:"
719 : "=c" (*value),
720 "=a" (result)
721 : "1" (PCIBIOS_READ_CONFIG_BYTE),
722 "b" (bx),
723 "D" ((long)reg),
724 "S" (&pci_indirect));
725 break;
726 case 2:
727 __asm__("lcall *(%%esi); cld\n\t"
728 "jc 1f\n\t"
729 "xor %%ah, %%ah\n"
730 "1:"
731 : "=c" (*value),
732 "=a" (result)
733 : "1" (PCIBIOS_READ_CONFIG_WORD),
734 "b" (bx),
735 "D" ((long)reg),
736 "S" (&pci_indirect));
737 break;
738 case 4:
739 __asm__("lcall *(%%esi); cld\n\t"
740 "jc 1f\n\t"
741 "xor %%ah, %%ah\n"
742 "1:"
743 : "=c" (*value),
744 "=a" (result)
745 : "1" (PCIBIOS_READ_CONFIG_DWORD),
746 "b" (bx),
747 "D" ((long)reg),
748 "S" (&pci_indirect));
749 break;
750 }
752 spin_unlock_irqrestore(&pci_config_lock, flags);
754 return (int)((result & 0xff00) >> 8);
755 }
757 static int pci_bios_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value)
758 {
759 unsigned long result = 0;
760 unsigned long flags;
761 unsigned long bx = ((bus << 8) | (dev << 3) | fn);
763 if ((bus > 255 || dev > 31 || fn > 7 || reg > 255))
764 return -EINVAL;
766 spin_lock_irqsave(&pci_config_lock, flags);
768 switch (len) {
769 case 1:
770 __asm__("lcall *(%%esi); cld\n\t"
771 "jc 1f\n\t"
772 "xor %%ah, %%ah\n"
773 "1:"
774 : "=a" (result)
775 : "0" (PCIBIOS_WRITE_CONFIG_BYTE),
776 "c" (value),
777 "b" (bx),
778 "D" ((long)reg),
779 "S" (&pci_indirect));
780 break;
781 case 2:
782 __asm__("lcall *(%%esi); cld\n\t"
783 "jc 1f\n\t"
784 "xor %%ah, %%ah\n"
785 "1:"
786 : "=a" (result)
787 : "0" (PCIBIOS_WRITE_CONFIG_WORD),
788 "c" (value),
789 "b" (bx),
790 "D" ((long)reg),
791 "S" (&pci_indirect));
792 break;
793 case 4:
794 __asm__("lcall *(%%esi); cld\n\t"
795 "jc 1f\n\t"
796 "xor %%ah, %%ah\n"
797 "1:"
798 : "=a" (result)
799 : "0" (PCIBIOS_WRITE_CONFIG_DWORD),
800 "c" (value),
801 "b" (bx),
802 "D" ((long)reg),
803 "S" (&pci_indirect));
804 break;
805 }
807 spin_unlock_irqrestore(&pci_config_lock, flags);
809 return (int)((result & 0xff00) >> 8);
810 }
812 static int pci_bios_read_config_byte(struct pci_dev *dev, int where, u8 *value)
813 {
814 int result;
815 u32 data;
817 if (!value)
818 BUG();
820 result = pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
821 PCI_FUNC(dev->devfn), where, 1, &data);
823 *value = (u8)data;
825 return result;
826 }
828 static int pci_bios_read_config_word(struct pci_dev *dev, int where, u16 *value)
829 {
830 int result;
831 u32 data;
833 if (!value)
834 BUG();
836 result = pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
837 PCI_FUNC(dev->devfn), where, 2, &data);
839 *value = (u16)data;
841 return result;
842 }
844 static int pci_bios_read_config_dword(struct pci_dev *dev, int where, u32 *value)
845 {
846 if (!value)
847 BUG();
849 return pci_bios_read(0, dev->bus->number, PCI_SLOT(dev->devfn),
850 PCI_FUNC(dev->devfn), where, 4, value);
851 }
853 static int pci_bios_write_config_byte(struct pci_dev *dev, int where, u8 value)
854 {
855 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
856 PCI_FUNC(dev->devfn), where, 1, value);
857 }
859 static int pci_bios_write_config_word(struct pci_dev *dev, int where, u16 value)
860 {
861 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
862 PCI_FUNC(dev->devfn), where, 2, value);
863 }
865 static int pci_bios_write_config_dword(struct pci_dev *dev, int where, u32 value)
866 {
867 return pci_bios_write(0, dev->bus->number, PCI_SLOT(dev->devfn),
868 PCI_FUNC(dev->devfn), where, 4, value);
869 }
872 /*
873 * Function table for BIOS32 access
874 */
876 static struct pci_ops pci_bios_access = {
877 pci_bios_read_config_byte,
878 pci_bios_read_config_word,
879 pci_bios_read_config_dword,
880 pci_bios_write_config_byte,
881 pci_bios_write_config_word,
882 pci_bios_write_config_dword
883 };
885 /*
886 * Try to find PCI BIOS.
887 */
889 static struct pci_ops * __devinit pci_find_bios(void)
890 {
891 union bios32 *check;
892 unsigned char sum;
893 int i, length;
895 /*
896 * Follow the standard procedure for locating the BIOS32 Service
897 * directory by scanning the permissible address range from
898 * 0xe0000 through 0xfffff for a valid BIOS32 structure.
899 */
901 for (check = (union bios32 *) __va(0xe0000);
902 check <= (union bios32 *) __va(0xffff0);
903 ++check) {
904 if (check->fields.signature != BIOS32_SIGNATURE)
905 continue;
906 length = check->fields.length * 16;
907 if (!length)
908 continue;
909 sum = 0;
910 for (i = 0; i < length ; ++i)
911 sum += check->chars[i];
912 if (sum != 0)
913 continue;
914 if (check->fields.revision != 0) {
915 printk("PCI: unsupported BIOS32 revision %d at 0x%p\n",
916 check->fields.revision, check);
917 continue;
918 }
919 DBG("PCI: BIOS32 Service Directory structure at 0x%p\n", check);
920 if (check->fields.entry >= 0x100000) {
921 printk("PCI: BIOS32 entry (0x%p) in high memory, cannot use.\n", check);
922 return NULL;
923 } else {
924 unsigned long bios32_entry = check->fields.entry;
925 DBG("PCI: BIOS32 Service Directory entry at 0x%lx\n", bios32_entry);
926 bios32_indirect.address = bios32_entry + PAGE_OFFSET;
927 if (check_pcibios())
928 return &pci_bios_access;
929 }
930 break; /* Hopefully more than one BIOS32 cannot happen... */
931 }
933 return NULL;
934 }
936 /*
937 * Sort the device list according to PCI BIOS. Nasty hack, but since some
938 * fool forgot to define the `correct' device order in the PCI BIOS specs
939 * and we want to be (possibly bug-to-bug ;-]) compatible with older kernels
940 * which used BIOS ordering, we are bound to do this...
941 */
943 static void __devinit pcibios_sort(void)
944 {
945 LIST_HEAD(sorted_devices);
946 struct list_head *ln;
947 struct pci_dev *dev, *d;
948 int idx, found;
949 unsigned char bus, devfn;
951 DBG("PCI: Sorting device list...\n");
952 while (!list_empty(&pci_devices)) {
953 ln = pci_devices.next;
954 dev = pci_dev_g(ln);
955 idx = found = 0;
956 while (pci_bios_find_device(dev->vendor, dev->device, idx, &bus, &devfn) == PCIBIOS_SUCCESSFUL) {
957 idx++;
958 for (ln=pci_devices.next; ln != &pci_devices; ln=ln->next) {
959 d = pci_dev_g(ln);
960 if (d->bus->number == bus && d->devfn == devfn) {
961 list_del(&d->global_list);
962 list_add_tail(&d->global_list, &sorted_devices);
963 if (d == dev)
964 found = 1;
965 break;
966 }
967 }
968 if (ln == &pci_devices) {
969 printk(KERN_WARNING "PCI: BIOS reporting unknown device %02x:%02x\n", bus, devfn);
970 /*
971 * We must not continue scanning as several buggy BIOSes
972 * return garbage after the last device. Grr.
973 */
974 break;
975 }
976 }
977 if (!found) {
978 printk(KERN_WARNING "PCI: Device %02x:%02x not found by BIOS\n",
979 dev->bus->number, dev->devfn);
980 list_del(&dev->global_list);
981 list_add_tail(&dev->global_list, &sorted_devices);
982 }
983 }
984 list_splice(&sorted_devices, &pci_devices);
985 }
987 /*
988 * BIOS Functions for IRQ Routing
989 */
991 struct irq_routing_options {
992 u16 size;
993 struct irq_info *table;
994 u16 segment;
995 } __attribute__((packed));
997 struct irq_routing_table * __devinit pcibios_get_irq_routing_table(void)
998 {
999 struct irq_routing_options opt;
1000 struct irq_routing_table *rt = NULL;
1001 int ret, map;
1002 unsigned long page;
1004 if (!pci_bios_present)
1005 return NULL;
1006 page = __get_free_page();
1007 if (!page)
1008 return NULL;
1009 opt.table = (struct irq_info *) page;
1010 opt.size = PAGE_SIZE;
1011 opt.segment = __KERNEL_DS;
1013 DBG("PCI: Fetching IRQ routing table... ");
1014 __asm__("push %%es\n\t"
1015 "push %%ds\n\t"
1016 "pop %%es\n\t"
1017 "lcall *(%%esi); cld\n\t"
1018 "pop %%es\n\t"
1019 "jc 1f\n\t"
1020 "xor %%ah, %%ah\n"
1021 "1:"
1022 : "=a" (ret),
1023 "=b" (map)
1024 : "0" (PCIBIOS_GET_ROUTING_OPTIONS),
1025 "1" (0),
1026 "D" (&opt),
1027 "S" (&pci_indirect)
1028 : "memory");
1029 DBG("OK ret=%d, size=%d, map=%x\n", ret, opt.size, map);
1030 if (ret & 0xff00)
1031 printk(KERN_ERR "PCI: Error %02x when fetching IRQ routing table.\n", (ret >> 8) & 0xff);
1032 else if (opt.size) {
1033 rt = kmalloc(sizeof(struct irq_routing_table) + opt.size);
1034 if (rt) {
1035 memset(rt, 0, sizeof(struct irq_routing_table));
1036 rt->size = opt.size + sizeof(struct irq_routing_table);
1037 rt->exclusive_irqs = map;
1038 memcpy(rt->slots, (void *) page, opt.size);
1039 printk(KERN_INFO "PCI: Using BIOS Interrupt Routing Table\n");
1042 free_page(page);
1043 return rt;
1047 int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq)
1049 int ret;
1051 __asm__("lcall *(%%esi); cld\n\t"
1052 "jc 1f\n\t"
1053 "xor %%ah, %%ah\n"
1054 "1:"
1055 : "=a" (ret)
1056 : "0" (PCIBIOS_SET_PCI_HW_INT),
1057 "b" ((dev->bus->number << 8) | dev->devfn),
1058 "c" ((irq << 8) | (pin + 10)),
1059 "S" (&pci_indirect));
1060 return !(ret & 0xff00);
1063 #endif
1065 /*
1066 * Several buggy motherboards address only 16 devices and mirror
1067 * them to next 16 IDs. We try to detect this `feature' on all
1068 * primary buses (those containing host bridges as they are
1069 * expected to be unique) and remove the ghost devices.
1070 */
1072 static void __devinit pcibios_fixup_ghosts(struct pci_bus *b)
1074 struct list_head *ln, *mn;
1075 struct pci_dev *d, *e;
1076 int mirror = PCI_DEVFN(16,0);
1077 int seen_host_bridge = 0;
1078 int i;
1080 DBG("PCI: Scanning for ghost devices on bus %d\n", b->number);
1081 for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
1082 d = pci_dev_b(ln);
1083 if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1084 seen_host_bridge++;
1085 for (mn=ln->next; mn != &b->devices; mn=mn->next) {
1086 e = pci_dev_b(mn);
1087 if (e->devfn != d->devfn + mirror ||
1088 e->vendor != d->vendor ||
1089 e->device != d->device ||
1090 e->class != d->class)
1091 continue;
1092 for(i=0; i<PCI_NUM_RESOURCES; i++)
1093 if (e->resource[i].start != d->resource[i].start ||
1094 e->resource[i].end != d->resource[i].end ||
1095 e->resource[i].flags != d->resource[i].flags)
1096 continue;
1097 break;
1099 if (mn == &b->devices)
1100 return;
1102 if (!seen_host_bridge)
1103 return;
1104 printk(KERN_WARNING "PCI: Ignoring ghost devices on bus %02x\n", b->number);
1106 ln = &b->devices;
1107 while (ln->next != &b->devices) {
1108 d = pci_dev_b(ln->next);
1109 if (d->devfn >= mirror) {
1110 list_del(&d->global_list);
1111 list_del(&d->bus_list);
1112 kfree(d);
1113 } else
1114 ln = ln->next;
1118 /*
1119 * Discover remaining PCI buses in case there are peer host bridges.
1120 * We use the number of last PCI bus provided by the PCI BIOS.
1121 */
1122 static void __devinit pcibios_fixup_peer_bridges(void)
1124 int n;
1125 struct pci_bus bus;
1126 struct pci_dev dev;
1127 u16 l;
1129 if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
1130 return;
1131 DBG("PCI: Peer bridge fixup\n");
1132 for (n=0; n <= pcibios_last_bus; n++) {
1133 if (pci_bus_exists(&pci_root_buses, n))
1134 continue;
1135 bus.number = n;
1136 bus.ops = pci_root_ops;
1137 dev.bus = &bus;
1138 for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
1139 if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
1140 l != 0x0000 && l != 0xffff) {
1141 DBG("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
1142 printk(KERN_INFO "PCI: Discovered peer bus %02x\n", n);
1143 pci_scan_bus(n, pci_root_ops, NULL);
1144 break;
1149 /*
1150 * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
1151 */
1153 static void __devinit pci_fixup_i450nx(struct pci_dev *d)
1155 /*
1156 * i450NX -- Find and scan all secondary buses on all PXB's.
1157 */
1158 int pxb, reg;
1159 u8 busno, suba, subb;
1160 #ifdef CONFIG_MULTIQUAD
1161 int quad = BUS2QUAD(d->bus->number);
1162 #endif
1163 printk("PCI: Searching for i450NX host bridges on %s\n", d->slot_name);
1164 reg = 0xd0;
1165 for(pxb=0; pxb<2; pxb++) {
1166 pci_read_config_byte(d, reg++, &busno);
1167 pci_read_config_byte(d, reg++, &suba);
1168 pci_read_config_byte(d, reg++, &subb);
1169 DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
1170 if (busno)
1171 pci_scan_bus(QUADLOCAL2BUS(quad,busno), pci_root_ops, NULL); /* Bus A */
1172 if (suba < subb)
1173 pci_scan_bus(QUADLOCAL2BUS(quad,suba+1), pci_root_ops, NULL); /* Bus B */
1175 pcibios_last_bus = -1;
1178 static void __devinit pci_fixup_i450gx(struct pci_dev *d)
1180 /*
1181 * i450GX and i450KX -- Find and scan all secondary buses.
1182 * (called separately for each PCI bridge found)
1183 */
1184 u8 busno;
1185 pci_read_config_byte(d, 0x4a, &busno);
1186 printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", d->slot_name, busno);
1187 pci_scan_bus(busno, pci_root_ops, NULL);
1188 pcibios_last_bus = -1;
1191 static void __devinit pci_fixup_umc_ide(struct pci_dev *d)
1193 /*
1194 * UM8886BF IDE controller sets region type bits incorrectly,
1195 * therefore they look like memory despite of them being I/O.
1196 */
1197 int i;
1199 printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", d->slot_name);
1200 for(i=0; i<4; i++)
1201 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
1204 static void __devinit pci_fixup_ncr53c810(struct pci_dev *d)
1206 /*
1207 * NCR 53C810 returns class code 0 (at least on some systems).
1208 * Fix class to be PCI_CLASS_STORAGE_SCSI
1209 */
1210 if (!d->class) {
1211 printk("PCI: fixing NCR 53C810 class code for %s\n", d->slot_name);
1212 d->class = PCI_CLASS_STORAGE_SCSI << 8;
1216 static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
1218 int i;
1220 /*
1221 * PCI IDE controllers use non-standard I/O port decoding, respect it.
1222 */
1223 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
1224 return;
1225 DBG("PCI: IDE base address fixup for %s\n", d->slot_name);
1226 for(i=0; i<4; i++) {
1227 struct resource *r = &d->resource[i];
1228 if ((r->start & ~0x80) == 0x374) {
1229 r->start |= 2;
1230 r->end = r->start;
1235 static void __devinit pci_fixup_ide_trash(struct pci_dev *d)
1237 int i;
1239 /*
1240 * There exist PCI IDE controllers which have utter garbage
1241 * in first four base registers. Ignore that.
1242 */
1243 DBG("PCI: IDE base address trash cleared for %s\n", d->slot_name);
1244 for(i=0; i<4; i++)
1245 d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
1248 static void __devinit pci_fixup_latency(struct pci_dev *d)
1250 /*
1251 * SiS 5597 and 5598 chipsets require latency timer set to
1252 * at most 32 to avoid lockups.
1253 */
1254 DBG("PCI: Setting max latency to 32\n");
1255 pcibios_max_latency = 32;
1258 static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
1260 /*
1261 * PIIX4 ACPI device: hardwired IRQ9
1262 */
1263 d->irq = 9;
1266 /*
1267 * Addresses issues with problems in the memory write queue timer in
1268 * certain VIA Northbridges. This bugfix is per VIA's specifications,
1269 * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
1270 * to trigger a bug in its integrated ProSavage video card, which
1271 * causes screen corruption. We only clear bits 6 and 7 for that chipset,
1272 * until VIA can provide us with definitive information on why screen
1273 * corruption occurs, and what exactly those bits do.
1275 * VIA 8363,8622,8361 Northbridges:
1276 * - bits 5, 6, 7 at offset 0x55 need to be turned off
1277 * VIA 8367 (KT266x) Northbridges:
1278 * - bits 5, 6, 7 at offset 0x95 need to be turned off
1279 * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
1280 * - bits 6, 7 at offset 0x55 need to be turned off
1281 */
1283 #define VIA_8363_KL133_REVISION_ID 0x81
1284 #define VIA_8363_KM133_REVISION_ID 0x84
1286 static void __init pci_fixup_via_northbridge_bug(struct pci_dev *d)
1288 u8 v;
1289 u8 revision;
1290 int where = 0x55;
1291 int mask = 0x1f; /* clear bits 5, 6, 7 by default */
1293 pci_read_config_byte(d, PCI_REVISION_ID, &revision);
1295 if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
1296 /* fix pci bus latency issues resulted by NB bios error
1297 it appears on bug free^Wreduced kt266x's bios forces
1298 NB latency to zero */
1299 pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
1301 where = 0x95; /* the memory write queue timer register is
1302 different for the KT266x's: 0x95 not 0x55 */
1303 } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
1304 (revision == VIA_8363_KL133_REVISION_ID ||
1305 revision == VIA_8363_KM133_REVISION_ID)) {
1306 mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
1307 causes screen corruption on the KL133/KM133 */
1310 pci_read_config_byte(d, where, &v);
1311 if (v & ~mask) {
1312 printk("Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
1313 d->device, revision, where, v, mask, v & mask);
1314 v &= mask;
1315 pci_write_config_byte(d, where, v);
1319 /*
1320 * For some reasons Intel decided that certain parts of their
1321 * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
1322 * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
1323 * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
1324 * to Intel terminology. These devices do forward all addresses from
1325 * system to PCI bus no matter what are their window settings, so they are
1326 * "transparent" (or subtractive decoding) from programmers point of view.
1327 */
1328 static void __init pci_fixup_transparent_bridge(struct pci_dev *dev)
1330 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
1331 (dev->device & 0xff00) == 0x2400)
1332 dev->transparent = 1;
1335 struct pci_fixup pcibios_fixups[] = {
1336 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx },
1337 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx },
1338 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide },
1339 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash },
1340 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases },
1341 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency },
1342 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency },
1343 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi },
1344 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug },
1345 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug },
1346 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug },
1347 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug },
1348 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810 },
1349 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge },
1350 { 0 }
1351 };
1353 /*
1354 * Called after each bus is probed, but before its children
1355 * are examined.
1356 */
1358 void __devinit pcibios_fixup_bus(struct pci_bus *b)
1360 pcibios_fixup_ghosts(b);
1361 pci_read_bridge_bases(b);
1364 struct pci_bus * __devinit pcibios_scan_root(int busnum)
1366 struct list_head *list;
1367 struct pci_bus *bus;
1369 list_for_each(list, &pci_root_buses) {
1370 bus = pci_bus_b(list);
1371 if (bus->number == busnum) {
1372 /* Already scanned */
1373 return bus;
1377 printk("PCI: Probing PCI hardware (bus %02x)\n", busnum);
1379 return pci_scan_bus(busnum, pci_root_ops, NULL);
1382 void __devinit pcibios_config_init(void)
1384 /*
1385 * Try all known PCI access methods. Note that we support using
1386 * both PCI BIOS and direct access, with a preference for direct.
1387 */
1389 #ifdef CONFIG_PCI_DIRECT
1390 struct pci_ops *tmp = NULL;
1391 #endif
1394 #ifdef CONFIG_PCI_BIOS
1395 if ((pci_probe & PCI_PROBE_BIOS)
1396 && ((pci_root_ops = pci_find_bios()))) {
1397 pci_probe |= PCI_BIOS_SORT;
1398 pci_bios_present = 1;
1399 pci_config_read = pci_bios_read;
1400 pci_config_write = pci_bios_write;
1402 #endif
1404 #ifdef CONFIG_PCI_DIRECT
1405 if ((pci_probe & (PCI_PROBE_CONF1 | PCI_PROBE_CONF2))
1406 && (tmp = pci_check_direct())) {
1407 pci_root_ops = tmp;
1408 if (pci_root_ops == &pci_direct_conf1) {
1409 pci_config_read = pci_conf1_read;
1410 pci_config_write = pci_conf1_write;
1412 else {
1413 pci_config_read = pci_conf2_read;
1414 pci_config_write = pci_conf2_write;
1417 #endif
1419 return;
1422 void __init pcibios_init(void)
1424 int quad;
1426 if (!pci_root_ops)
1427 pcibios_config_init();
1428 if (!pci_root_ops) {
1429 printk(KERN_WARNING "PCI: System does not support PCI\n");
1430 return;
1433 pcibios_set_cacheline_size();
1435 printk(KERN_INFO "PCI: Probing PCI hardware\n");
1436 #ifdef CONFIG_ACPI_PCI
1437 if (!acpi_noirq && !acpi_pci_irq_init()) {
1438 pci_using_acpi_prt = 1;
1439 printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
1440 printk(KERN_INFO "PCI: if you experience problems, try using option 'pci=noacpi' or even 'acpi=off'\n");
1442 #endif
1443 if (!pci_using_acpi_prt) {
1444 pci_root_bus = pcibios_scan_root(0);
1445 pcibios_irq_init();
1446 pcibios_fixup_peer_bridges();
1447 pcibios_fixup_irqs();
1449 if (clustered_apic_mode && (numnodes > 1)) {
1450 for (quad = 1; quad < numnodes; ++quad) {
1451 printk("Scanning PCI bus %d for quad %d\n",
1452 QUADLOCAL2BUS(quad,0), quad);
1453 pci_scan_bus(QUADLOCAL2BUS(quad,0),
1454 pci_root_ops, NULL);
1458 pcibios_resource_survey();
1460 #ifdef CONFIG_PCI_BIOS
1461 if ((pci_probe & PCI_BIOS_SORT) && !(pci_probe & PCI_NO_SORT))
1462 pcibios_sort();
1463 #endif
1466 char * __devinit pcibios_setup(char *str)
1468 if (!strcmp(str, "off")) {
1469 pci_probe = 0;
1470 return NULL;
1472 #ifdef CONFIG_PCI_BIOS
1473 else if (!strcmp(str, "bios")) {
1474 pci_probe = PCI_PROBE_BIOS;
1475 return NULL;
1476 } else if (!strcmp(str, "nobios")) {
1477 pci_probe &= ~PCI_PROBE_BIOS;
1478 return NULL;
1479 } else if (!strcmp(str, "nosort")) {
1480 pci_probe |= PCI_NO_SORT;
1481 return NULL;
1482 } else if (!strcmp(str, "biosirq")) {
1483 pci_probe |= PCI_BIOS_IRQ_SCAN;
1484 return NULL;
1486 #endif
1487 #ifdef CONFIG_PCI_DIRECT
1488 else if (!strcmp(str, "conf1")) {
1489 pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
1490 return NULL;
1492 else if (!strcmp(str, "conf2")) {
1493 pci_probe = PCI_PROBE_CONF2 | PCI_NO_CHECKS;
1494 return NULL;
1496 #endif
1497 else if (!strcmp(str, "rom")) {
1498 pci_probe |= PCI_ASSIGN_ROMS;
1499 return NULL;
1500 } else if (!strcmp(str, "assign-busses")) {
1501 pci_probe |= PCI_ASSIGN_ALL_BUSSES;
1502 return NULL;
1503 } else if (!strncmp(str, "irqmask=", 8)) {
1504 pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
1505 return NULL;
1506 } else if (!strncmp(str, "lastbus=", 8)) {
1507 pcibios_last_bus = simple_strtol(str+8, NULL, 0);
1508 return NULL;
1509 } else if (!strncmp(str, "noacpi", 6)) {
1510 acpi_noirq_set();
1511 return NULL;
1513 return str;
1516 unsigned int pcibios_assign_all_busses(void)
1518 return (pci_probe & PCI_ASSIGN_ALL_BUSSES) ? 1 : 0;
1521 int pcibios_enable_device(struct pci_dev *dev, int mask)
1523 int err;
1525 if ((err = pcibios_enable_resources(dev, mask)) < 0)
1526 return err;
1528 #ifdef CONFIG_ACPI_PCI
1529 if (pci_using_acpi_prt) {
1530 acpi_pci_irq_enable(dev);
1531 return 0;
1533 #endif
1535 pcibios_enable_irq(dev);
1537 return 0;