ia64/xen-unstable

view xen/include/asm-x86/config.h @ 13878:9d103e5fd471

[XEN] Fix typos in comment describing 32on64 memory layout

Signed-off-by: Ian Campbell <ian.campbell@xensource.com>
author Ian Campbell <ian.campbell@xensource.com>
date Thu Feb 08 12:33:32 2007 +0000 (2007-02-08)
parents 244e46e7d021
children ee4850bc895b
line source
1 /******************************************************************************
2 * config.h
3 *
4 * A Linux-style configuration list.
5 */
7 #ifndef __X86_CONFIG_H__
8 #define __X86_CONFIG_H__
10 #if defined(__x86_64__)
11 # define CONFIG_PAGING_LEVELS 4
12 #elif defined(CONFIG_X86_PAE)
13 # define CONFIG_PAGING_LEVELS 3
14 #else
15 # define CONFIG_PAGING_LEVELS 2
16 #endif
18 #define CONFIG_X86 1
19 #define CONFIG_X86_HT 1
20 #define CONFIG_SHADOW 1
21 #define CONFIG_SMP 1
22 #define CONFIG_X86_LOCAL_APIC 1
23 #define CONFIG_X86_GOOD_APIC 1
24 #define CONFIG_X86_IO_APIC 1
25 #define CONFIG_HPET_TIMER 1
26 #define CONFIG_X86_MCE_P4THERMAL 1
27 #define CONFIG_ACPI_NUMA 1
28 #define CONFIG_NUMA 1
29 #define CONFIG_ACPI_SRAT 1
30 #define CONFIG_DISCONTIGMEM 1
31 #define CONFIG_NUMA_EMU 1
33 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */
34 #define CONFIG_X86_L1_CACHE_SHIFT 7
36 #define CONFIG_ACPI 1
37 #define CONFIG_ACPI_BOOT 1
39 #define CONFIG_VGA 1
41 #define HZ 100
43 #define OPT_CONSOLE_STR "com1,vga"
45 #ifdef MAX_PHYS_CPUS
46 #define NR_CPUS MAX_PHYS_CPUS
47 #else
48 #define NR_CPUS 32
49 #endif
51 #if defined(__i386__) && (NR_CPUS > 32)
52 #error "Maximum of 32 physical processors supported by Xen on x86_32"
53 #endif
55 #ifdef CONFIG_X86_SUPERVISOR_MODE_KERNEL
56 # define supervisor_mode_kernel (1)
57 #else
58 # define supervisor_mode_kernel (0)
59 #endif
61 /* Linkage for x86 */
62 #define __ALIGN .align 16,0x90
63 #define __ALIGN_STR ".align 16,0x90"
64 #ifdef __ASSEMBLY__
65 #define ALIGN __ALIGN
66 #define ALIGN_STR __ALIGN_STR
67 #define ENTRY(name) \
68 .globl name; \
69 ALIGN; \
70 name:
71 #endif
73 #define NR_hypercalls 64
75 #ifndef NDEBUG
76 #define MEMORY_GUARD
77 #endif
79 #define STACK_ORDER 2
80 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER)
82 /* Debug stack is restricted to 8kB by guard pages. */
83 #define DEBUG_STACK_SIZE 8192
85 #define CONFIG_DMA_BITSIZE 30
87 #if defined(__x86_64__)
89 #define CONFIG_X86_64 1
90 #define CONFIG_COMPAT 1
92 #define asmlinkage
94 #define XENHEAP_DEFAULT_MB (16)
96 #define PML4_ENTRY_BITS 39
97 #ifndef __ASSEMBLY__
98 #define PML4_ENTRY_BYTES (1UL << PML4_ENTRY_BITS)
99 #define PML4_ADDR(_slot) \
100 ((((_slot ## UL) >> 8) * 0xffff000000000000UL) | \
101 (_slot ## UL << PML4_ENTRY_BITS))
102 #else
103 #define PML4_ENTRY_BYTES (1 << PML4_ENTRY_BITS)
104 #define PML4_ADDR(_slot) \
105 (((_slot >> 8) * 0xffff000000000000) | (_slot << PML4_ENTRY_BITS))
106 #endif
108 /*
109 * Memory layout:
110 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255]
111 * Guest-defined use (see below for compatibility mode guests).
112 * 0x0000800000000000 - 0xffff7fffffffffff [16EB]
113 * Inaccessible: current arch only supports 48-bit sign-extended VAs.
114 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256]
115 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
116 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256]
117 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE).
118 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257]
119 * Read-only guest linear page table (GUEST ACCESSIBLE).
120 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258]
121 * Guest linear page table.
122 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259]
123 * Shadow linear page table.
124 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260]
125 * Per-domain mappings (e.g., GDT, LDT).
126 * 0xffff828000000000 - 0xffff8283ffffffff [16GB, 2^34 bytes, PML4:261]
127 * Machine-to-phys translation table.
128 * 0xffff828400000000 - 0xffff8287ffffffff [16GB, 2^34 bytes, PML4:261]
129 * Page-frame information array.
130 * 0xffff828800000000 - 0xffff828bffffffff [16GB, 2^34 bytes, PML4:261]
131 * ioremap()/fixmap area.
132 * 0xffff828c00000000 - 0xffff828c3fffffff [1GB, 2^30 bytes, PML4:261]
133 * Compatibility machine-to-phys translation table.
134 * 0xffff828c40000000 - 0xffff828c7fffffff [1GB, 2^30 bytes, PML4:261]
135 * High read-only compatibility machine-to-phys translation table.
136 * 0xffff828c80000000 - 0xffff82ffffffffff [462GB, PML4:261]
137 * Reserved for future use.
138 * 0xffff830000000000 - 0xffff83ffffffffff [1TB, 2^40 bytes, PML4:262-263]
139 * 1:1 direct mapping of all physical memory. Xen and its heap live here.
140 * 0xffff840000000000 - 0xffff87ffffffffff [4TB, 2^42 bytes, PML4:264-271]
141 * Reserved for future use.
142 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511]
143 * Guest-defined use.
144 *
145 * Compatibility guest area layout:
146 * 0x0000000000000000 - 0x00000000f57fffff [3928MB, PML4:0]
147 * Guest-defined use.
148 * 0x00000000f5800000 - 0x00000000ffffffff [168MB, PML4:0]
149 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
150 * 0x0000000100000000 - 0x0000007fffffffff [508GB, PML4:0]
151 * Unused.
152 * 0x0000008000000000 - 0x000000ffffffffff [512GB, 2^39 bytes, PML4:1]
153 * Hypercall argument translation area.
154 * 0x0000010000000000 - 0x00007fffffffffff [127TB, 2^46 bytes, PML4:2-255]
155 * Reserved for future use.
156 */
159 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256
160 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271
161 #define ROOT_PAGETABLE_XEN_SLOTS \
162 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1)
164 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */
165 #define HYPERVISOR_VIRT_START (PML4_ADDR(256))
166 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16)
167 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */
168 #define RO_MPT_VIRT_START (PML4_ADDR(256))
169 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + PML4_ENTRY_BYTES/2)
171 // current unused?
172 #if 0
173 /* Slot 257: read-only guest-accessible linear page table. */
174 #define RO_LINEAR_PT_VIRT_START (PML4_ADDR(257))
175 #define RO_LINEAR_PT_VIRT_END (RO_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
176 #endif
178 /* Slot 258: linear page table (guest table). */
179 #define LINEAR_PT_VIRT_START (PML4_ADDR(258))
180 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
181 /* Slot 259: linear page table (shadow table). */
182 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259))
183 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
184 /* Slot 260: per-domain mappings. */
185 #define PERDOMAIN_VIRT_START (PML4_ADDR(260))
186 #define PERDOMAIN_VIRT_END (PERDOMAIN_VIRT_START + (PERDOMAIN_MBYTES<<20))
187 #define PERDOMAIN_MBYTES ((unsigned long)GDT_LDT_MBYTES)
188 /* Slot 261: machine-to-phys conversion table (16GB). */
189 #define RDWR_MPT_VIRT_START (PML4_ADDR(261))
190 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + (16UL<<30))
191 /* Slot 261: page-frame information array (16GB). */
192 #define FRAMETABLE_VIRT_START (RDWR_MPT_VIRT_END)
193 #define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + (16UL<<30))
194 /* Slot 261: ioremap()/fixmap area (16GB). */
195 #define IOREMAP_VIRT_START (FRAMETABLE_VIRT_END)
196 #define IOREMAP_VIRT_END (IOREMAP_VIRT_START + (16UL<<30))
197 /* Slot 261: compatibility machine-to-phys conversion table (1GB). */
198 #define RDWR_COMPAT_MPT_VIRT_START IOREMAP_VIRT_END
199 #define RDWR_COMPAT_MPT_VIRT_END (RDWR_COMPAT_MPT_VIRT_START + (1UL << 30))
200 /* Slot 261: high read-only compatibility machine-to-phys conversion table (1GB). */
201 #define HIRO_COMPAT_MPT_VIRT_START RDWR_COMPAT_MPT_VIRT_END
202 #define HIRO_COMPAT_MPT_VIRT_END (HIRO_COMPAT_MPT_VIRT_START + (1UL << 30))
203 /* Slot 262-263: A direct 1:1 mapping of all of physical memory. */
204 #define DIRECTMAP_VIRT_START (PML4_ADDR(262))
205 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + PML4_ENTRY_BYTES*2)
207 #ifndef __ASSEMBLY__
209 /* This is not a fixed value, just a lower limit. */
210 #define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000
211 #define HYPERVISOR_COMPAT_VIRT_START(d) ((d)->arch.hv_compat_vstart)
212 #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START
213 #define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000
214 #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \
215 ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2)
217 #define COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) \
218 l2_table_offset(HYPERVISOR_COMPAT_VIRT_START(d))
219 #define COMPAT_L2_PAGETABLE_LAST_XEN_SLOT l2_table_offset(~0U)
220 #define COMPAT_L2_PAGETABLE_XEN_SLOTS(d) \
221 (COMPAT_L2_PAGETABLE_LAST_XEN_SLOT - COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) + 1)
223 #endif
225 #define COMPAT_ARG_XLAT_VIRT_BASE (1UL << ROOT_PAGETABLE_SHIFT)
226 #define COMPAT_ARG_XLAT_SHIFT 0
227 #define COMPAT_ARG_XLAT_PAGES (1U << COMPAT_ARG_XLAT_SHIFT)
228 #define COMPAT_ARG_XLAT_SIZE (COMPAT_ARG_XLAT_PAGES << PAGE_SHIFT)
229 #define COMPAT_ARG_XLAT_VIRT_START(vcpu_id) \
230 (COMPAT_ARG_XLAT_VIRT_BASE + ((unsigned long)(vcpu_id) << \
231 (PAGE_SHIFT + COMPAT_ARG_XLAT_SHIFT + 1)))
233 #define PGT_base_page_table PGT_l4_page_table
235 #define __HYPERVISOR_CS64 0xe008
236 #define __HYPERVISOR_CS32 0xe038
237 #define __HYPERVISOR_CS __HYPERVISOR_CS64
238 #define __HYPERVISOR_DS64 0x0000
239 #define __HYPERVISOR_DS32 0xe010
240 #define __HYPERVISOR_DS __HYPERVISOR_DS64
242 /* For generic assembly code: use macros to define operation/operand sizes. */
243 #define __OS "q" /* Operation Suffix */
244 #define __OP "r" /* Operand Prefix */
245 #define __FIXUP_ALIGN ".align 8"
246 #define __FIXUP_WORD ".quad"
248 #elif defined(__i386__)
250 #define CONFIG_X86_32 1
251 #define CONFIG_DOMAIN_PAGE 1
253 #define asmlinkage __attribute__((regparm(0)))
255 /*
256 * Memory layout (high to low): SIZE PAE-SIZE
257 * ------ ------
258 * I/O remapping area ( 4MB)
259 * Direct-map (1:1) area [Xen code/data/heap] (12MB)
260 * Per-domain mappings (inc. 4MB map_domain_page cache) ( 8MB)
261 * Shadow linear pagetable ( 4MB) ( 8MB)
262 * Guest linear pagetable ( 4MB) ( 8MB)
263 * Machine-to-physical translation table [writable] ( 4MB) (16MB)
264 * Frame-info table (24MB) (96MB)
265 * * Start of guest inaccessible area
266 * Machine-to-physical translation table [read-only] ( 4MB) (16MB)
267 * * Start of guest unmodifiable area
268 */
270 #define IOREMAP_MBYTES 4
271 #define DIRECTMAP_MBYTES 12
272 #define MAPCACHE_MBYTES 4
273 #define PERDOMAIN_MBYTES 8
275 #ifdef CONFIG_X86_PAE
276 # define LINEARPT_MBYTES 8
277 # define MACHPHYS_MBYTES 16 /* 1 MB needed per 1 GB memory */
278 # define FRAMETABLE_MBYTES (MACHPHYS_MBYTES * 6)
279 #else
280 # define LINEARPT_MBYTES 4
281 # define MACHPHYS_MBYTES 4
282 # define FRAMETABLE_MBYTES 24
283 #endif
285 #define IOREMAP_VIRT_END 0UL
286 #define IOREMAP_VIRT_START (IOREMAP_VIRT_END - (IOREMAP_MBYTES<<20))
287 #define DIRECTMAP_VIRT_END IOREMAP_VIRT_START
288 #define DIRECTMAP_VIRT_START (DIRECTMAP_VIRT_END - (DIRECTMAP_MBYTES<<20))
289 #define MAPCACHE_VIRT_END DIRECTMAP_VIRT_START
290 #define MAPCACHE_VIRT_START (MAPCACHE_VIRT_END - (MAPCACHE_MBYTES<<20))
291 #define PERDOMAIN_VIRT_END DIRECTMAP_VIRT_START
292 #define PERDOMAIN_VIRT_START (PERDOMAIN_VIRT_END - (PERDOMAIN_MBYTES<<20))
293 #define SH_LINEAR_PT_VIRT_END PERDOMAIN_VIRT_START
294 #define SH_LINEAR_PT_VIRT_START (SH_LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
295 #define LINEAR_PT_VIRT_END SH_LINEAR_PT_VIRT_START
296 #define LINEAR_PT_VIRT_START (LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
297 #define RDWR_MPT_VIRT_END LINEAR_PT_VIRT_START
298 #define RDWR_MPT_VIRT_START (RDWR_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
299 #define FRAMETABLE_VIRT_END RDWR_MPT_VIRT_START
300 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - (FRAMETABLE_MBYTES<<20))
301 #define RO_MPT_VIRT_END FRAMETABLE_VIRT_START
302 #define RO_MPT_VIRT_START (RO_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
304 #define XENHEAP_DEFAULT_MB (DIRECTMAP_MBYTES)
305 #define DIRECTMAP_PHYS_END (DIRECTMAP_MBYTES<<20)
307 /* Maximum linear address accessible via guest memory segments. */
308 #define GUEST_SEGMENT_MAX_ADDR RO_MPT_VIRT_END
310 #ifdef CONFIG_X86_PAE
311 /* Hypervisor owns top 168MB of virtual address space. */
312 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xF5800000)
313 #else
314 /* Hypervisor owns top 64MB of virtual address space. */
315 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xFC000000)
316 #endif
318 #define L2_PAGETABLE_FIRST_XEN_SLOT \
319 (HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT)
320 #define L2_PAGETABLE_LAST_XEN_SLOT \
321 (~0UL >> L2_PAGETABLE_SHIFT)
322 #define L2_PAGETABLE_XEN_SLOTS \
323 (L2_PAGETABLE_LAST_XEN_SLOT - L2_PAGETABLE_FIRST_XEN_SLOT + 1)
325 #ifdef CONFIG_X86_PAE
326 # define PGT_base_page_table PGT_l3_page_table
327 #else
328 # define PGT_base_page_table PGT_l2_page_table
329 #endif
331 #define __HYPERVISOR_CS 0xe008
332 #define __HYPERVISOR_DS 0xe010
334 /* For generic assembly code: use macros to define operation/operand sizes. */
335 #define __OS "l" /* Operation Suffix */
336 #define __OP "e" /* Operand Prefix */
337 #define __FIXUP_ALIGN ".align 4"
338 #define __FIXUP_WORD ".long"
340 #endif /* __i386__ */
342 #ifndef __ASSEMBLY__
343 extern unsigned long xenheap_phys_end; /* user-configurable */
344 #endif
346 /* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */
347 #define GDT_LDT_VCPU_SHIFT 5
348 #define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT)
349 #define GDT_LDT_MBYTES (MAX_VIRT_CPUS >> (20-GDT_LDT_VCPU_VA_SHIFT))
350 #define GDT_LDT_VIRT_START PERDOMAIN_VIRT_START
351 #define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20))
353 /* The address of a particular VCPU's GDT or LDT. */
354 #define GDT_VIRT_START(v) \
355 (PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT))
356 #define LDT_VIRT_START(v) \
357 (GDT_VIRT_START(v) + (64*1024))
359 #define PDPT_L1_ENTRIES \
360 ((PERDOMAIN_VIRT_END - PERDOMAIN_VIRT_START) >> PAGE_SHIFT)
361 #define PDPT_L2_ENTRIES \
362 ((PDPT_L1_ENTRIES + (1 << PAGETABLE_ORDER) - 1) >> PAGETABLE_ORDER)
364 #if defined(__x86_64__)
365 #define ELFSIZE 64
366 #else
367 #define ELFSIZE 32
368 #endif
370 #endif /* __X86_CONFIG_H__ */