ia64/xen-unstable

view xen/common/physdev.c @ 3268:9a8889149665

bitkeeper revision 1.1159.187.62 (41bb06dfBOXZ2Y0I-fSinx_R6pcANQ)

Fix PCI cardbus.
author kaf24@scramble.cl.cam.ac.uk
date Sat Dec 11 14:40:31 2004 +0000 (2004-12-11)
parents e16455258e29
children f21030c169e2
line source
1 /* -*- Mode:C; c-basic-offset:4; tab-width:4 -*-
2 ****************************************************************************
3 * (c) 2004 - Rolf Neugebauer - Intel Research Cambridge
4 * (c) 2004 - Keir Fraser - University of Cambridge
5 ****************************************************************************
6 *
7 * Description: allows a domain to access devices on the PCI bus
8 *
9 * A guest OS may be given access to particular devices on the PCI bus.
10 * For each domain a list of PCI devices is maintained, describing the
11 * access mode for the domain.
12 *
13 * Guests can figure out the virtualised PCI space through normal PCI config
14 * register access. Some of the accesses, in particular write accesses, are
15 * faked. For example the sequence for detecting the IO regions, which requires
16 * writes to determine the size of the region, is faked out by a very simple
17 * state machine, preventing direct writes to the PCI config registers by a
18 * guest.
19 */
21 #include <xen/config.h>
22 #include <xen/lib.h>
23 #include <xen/types.h>
24 #include <xen/sched.h>
25 #include <xen/pci.h>
26 #include <xen/irq.h>
27 #include <xen/event.h>
28 #include <asm/pci.h>
29 #include <public/xen.h>
30 #include <public/physdev.h>
32 /* Called by PHYSDEV_PCI_INITIALISE_DEVICE to finalise IRQ routing. */
33 extern void pcibios_enable_irq(struct pci_dev *dev);
35 #if 0
36 #define VERBOSE_INFO(_f, _a...) printk( _f , ## _a )
37 #else
38 #define VERBOSE_INFO(_f, _a...) ((void)0)
39 #endif
41 #ifdef VERBOSE
42 #define INFO(_f, _a...) printk( _f, ## _a )
43 #else
44 #define INFO(_f, _a...) ((void)0)
45 #endif
48 #define ACC_READ 1
49 #define ACC_WRITE 2
51 /* Upper bounds for PCI-device addressing. */
52 #define PCI_BUSMAX 255
53 #define PCI_DEVMAX 31
54 #define PCI_FUNCMAX 7
55 #define PCI_REGMAX 255
57 /* Bit offsets into state. */
58 #define ST_BASE_ADDRESS 0 /* bits 0-5: are for base address access */
59 #define ST_ROM_ADDRESS 6 /* bit 6: is for rom address access */
61 typedef struct _phys_dev_st {
62 int flags; /* flags for access etc */
63 struct pci_dev *dev; /* the device */
64 struct list_head node; /* link to the list */
65 struct domain *owner; /* 'owner of this device' */
66 int state; /* state for various checks */
67 } phys_dev_t;
70 /* Find a device on a per-domain device list. */
71 static phys_dev_t *find_pdev(struct domain *p, struct pci_dev *dev)
72 {
73 phys_dev_t *t, *res = NULL;
74 struct list_head *tmp;
76 list_for_each(tmp, &p->pcidev_list)
77 {
78 t = list_entry(tmp, phys_dev_t, node);
79 if ( dev == t->dev )
80 {
81 res = t;
82 break;
83 }
84 }
85 return res;
86 }
88 /* Add a device to a per-domain device-access list. */
89 static void add_dev_to_task(struct domain *p,
90 struct pci_dev *dev, int acc)
91 {
92 phys_dev_t *pdev;
94 if ( (pdev = find_pdev(p, dev)) )
95 {
96 /* Sevice already on list: update access permissions. */
97 pdev->flags = acc;
98 return;
99 }
101 if ( (pdev = xmalloc(sizeof(phys_dev_t))) == NULL )
102 {
103 INFO("Error allocating pdev structure.\n");
104 return;
105 }
107 pdev->dev = dev;
108 pdev->flags = acc;
109 pdev->state = 0;
110 list_add(&pdev->node, &p->pcidev_list);
112 if ( acc == ACC_WRITE )
113 pdev->owner = p;
114 }
116 /*
117 * physdev_pci_access_modify:
118 * Allow/disallow access to a specific PCI device. Guests should not be
119 * allowed to see bridge devices as it needlessly complicates things (one
120 * possible exception to this is the AGP bridge). If the given device is a
121 * bridge, then the domain should get access to all the leaf devices below
122 * that bridge (XXX this is unimplemented!).
123 */
124 int physdev_pci_access_modify(
125 domid_t dom, int bus, int dev, int func, int enable)
126 {
127 struct domain *p;
128 struct pci_dev *pdev;
129 int i, j, rc = 0;
131 if ( !IS_PRIV(current) )
132 BUG();
134 if ( (bus > PCI_BUSMAX) || (dev > PCI_DEVMAX) || (func > PCI_FUNCMAX) )
135 return -EINVAL;
137 if ( !enable )
138 {
139 INFO("Disallowing access is not yet supported.\n");
140 return -EINVAL;
141 }
143 INFO("physdev_pci_access_modify: %02x:%02x:%02x\n", bus, dev, func);
145 if ( (p = find_domain_by_id(dom)) == NULL )
146 return -ESRCH;
148 /* Make the domain privileged. */
149 set_bit(DF_PHYSDEV, &p->flags);
150 /* FIXME: MAW for now make the domain REALLY privileged so that it
151 * can run a backend driver (hw access should work OK otherwise) */
152 set_bit(DF_PRIVILEGED, &p->flags);
154 /* Grant write access to the specified device. */
155 if ( (pdev = pci_find_slot(bus, PCI_DEVFN(dev, func))) == NULL )
156 {
157 INFO(" dev does not exist\n");
158 rc = -ENODEV;
159 goto out;
160 }
161 add_dev_to_task(p, pdev, ACC_WRITE);
163 INFO(" add RW %02x:%02x:%02x\n", pdev->bus->number,
164 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
166 /* Is the device a bridge or cardbus? */
167 if ( pdev->hdr_type != PCI_HEADER_TYPE_NORMAL )
168 INFO("XXX can't give access to bridge devices yet\n");
170 /* Now, setup access to the IO ports and memory regions for the device. */
172 if ( p->thread.io_bitmap == NULL )
173 {
174 if ( (p->thread.io_bitmap = xmalloc(IOBMP_BYTES)) == NULL )
175 {
176 rc = -ENOMEM;
177 goto out;
178 }
179 memset(p->thread.io_bitmap, 0xFF, IOBMP_BYTES);
181 p->thread.io_bitmap_sel = ~0ULL;
182 }
184 for ( i = 0; i < DEVICE_COUNT_RESOURCE; i++ )
185 {
186 struct resource *r = &pdev->resource[i];
188 if ( r->flags & IORESOURCE_IO )
189 {
190 /* Give the domain access to the IO ports it needs. Currently,
191 * this will allow all processes in that domain access to those
192 * ports as well. This will do for now, since driver domains don't
193 * run untrusted processes! */
194 INFO("Giving domain %u IO resources (%lx - %lx) "
195 "for device %s\n", dom, r->start, r->end, pdev->slot_name);
196 for ( j = r->start; j < r->end + 1; j++ )
197 {
198 clear_bit(j, p->thread.io_bitmap);
199 clear_bit(j / IOBMP_BITS_PER_SELBIT, &p->thread.io_bitmap_sel);
200 }
201 }
203 /* rights to IO memory regions are checked when the domain maps them */
204 }
205 out:
206 put_domain(p);
207 return rc;
208 }
210 /* Check if a domain controls a device with IO memory within frame @pfn.
211 * Returns: 1 if the domain should be allowed to map @pfn, 0 otherwise. */
212 int domain_iomem_in_pfn(struct domain *p, unsigned long pfn)
213 {
214 int ret = 0;
215 struct list_head *l;
217 VERBOSE_INFO("Checking if physdev-capable domain %u needs access to "
218 "pfn %08lx\n", p->id, pfn);
220 spin_lock(&p->pcidev_lock);
222 list_for_each(l, &p->pcidev_list)
223 {
224 int i;
225 phys_dev_t *phys_dev = list_entry(l, phys_dev_t, node);
226 struct pci_dev *pci_dev = phys_dev->dev;
228 for ( i = 0; (i < DEVICE_COUNT_RESOURCE) && (ret == 0); i++ )
229 {
230 struct resource *r = &pci_dev->resource[i];
232 if ( r->flags & IORESOURCE_MEM )
233 if ( (r->start >> PAGE_SHIFT) == pfn
234 || (r->end >> PAGE_SHIFT) == pfn
235 || ((r->start >> PAGE_SHIFT < pfn)
236 && (r->end >> PAGE_SHIFT > pfn)) )
237 ret = 1;
238 }
240 if ( ret != 0 ) break;
241 }
243 spin_unlock(&p->pcidev_lock);
245 VERBOSE_INFO("Domain %u %s mapping of pfn %08lx\n",
246 p->id, ret ? "allowed" : "disallowed", pfn);
248 return ret;
249 }
251 /* check if a domain has general access to a device */
252 inline static int check_dev_acc (struct domain *p,
253 int bus, int dev, int func,
254 phys_dev_t **pdev)
255 {
256 struct pci_dev *target_dev;
257 phys_dev_t *target_pdev;
258 unsigned int target_devfn;
260 *pdev = NULL;
262 if ( !IS_CAPABLE_PHYSDEV(p) )
263 return -EPERM; /* no pci access permission */
265 if ( bus > PCI_BUSMAX || dev > PCI_DEVMAX || func > PCI_FUNCMAX )
266 return -EINVAL;
268 VERBOSE_INFO("b=%x d=%x f=%x ", bus, dev, func);
270 /* check target device */
271 target_devfn = PCI_DEVFN(dev, func);
272 target_dev = pci_find_slot(bus, target_devfn);
273 if ( !target_dev )
274 {
275 VERBOSE_INFO("target does not exist\n");
276 return -ENODEV;
277 }
279 /* check access */
280 target_pdev = find_pdev(p, target_dev);
281 if ( !target_pdev )
282 {
283 VERBOSE_INFO("dom has no access to target\n");
284 return -EPERM;
285 }
287 *pdev = target_pdev;
288 return 0;
289 }
292 /*
293 * Base address registers contain the base address for IO regions.
294 * The length can be determined by writing all 1s to the register and
295 * reading the value again. The device will zero the lower unused bits.
296 *
297 * to work out the length of the io region a device probe typically does:
298 * 1) a = read_base_addr_reg()
299 * 2) write_base_addr_reg(0xffffffff)
300 * 3) b = read_base_addr_reg() [device zeros lower bits]
301 * 4) write_base_addr_reg(a) [restore original value]
302 * this function fakes out step 2-4. *no* writes are made to the device.
303 *
304 * phys_dev_t contains a bit field (a bit for each base address register).
305 * if the bit for a register is set the guest had writen all 1s to the
306 * register and subsequent read request need to fake out the b.
307 * if the guest restores the original value (step 4 above) the bit is
308 * cleared again. If the guest attempts to "restores" a wrong value an
309 * error is flagged.
310 */
311 static int do_base_address_access(phys_dev_t *pdev, int acc, int idx,
312 int len, u32 *val)
313 {
314 int st_bit, reg = PCI_BASE_ADDRESS_0 + (idx*4), ret = -EINVAL;
315 struct pci_dev *dev = pdev->dev;
316 u32 orig_val, sz;
317 struct resource *res;
319 if ( len != sizeof(u32) )
320 {
321 /* This isn't illegal, but there doesn't seem to be a very good reason
322 * to do it for normal devices (bridges are another matter). Since it
323 * would complicate the code below, we don't support this for now. */
325 /* We could set *val to some value but the guest may well be in trouble
326 * anyway if this write fails. Hopefully the printk will give us a
327 * clue what went wrong. */
328 INFO("Guest %u attempting sub-dword %s to BASE_ADDRESS %d\n",
329 pdev->owner->id, (acc == ACC_READ) ? "read" : "write", idx);
331 return -EPERM;
332 }
334 st_bit = idx + ST_BASE_ADDRESS;
335 res = &(pdev->dev->resource[idx]);
337 if ( acc == ACC_WRITE )
338 {
339 if ( (*val == 0xffffffff) ||
340 ((res->flags & IORESOURCE_IO) && (*val == 0xffff)) )
341 {
342 /* Set bit and return. */
343 set_bit(st_bit, &pdev->state);
344 ret = 0;
345 }
346 else
347 {
348 /* Assume guest wants to set the base address. */
349 clear_bit(st_bit, &pdev->state);
351 /* check if guest tries to restore orig value */
352 ret = pci_read_config_dword(dev, reg, &orig_val);
353 if ( (ret == 0) && (*val != orig_val) )
354 {
355 INFO("Guest attempting update to BASE_ADDRESS %d\n", idx);
356 ret = -EPERM;
357 }
358 }
359 VERBOSE_INFO("fixed pci write: %02x:%02x:%02x reg=0x%02x len=0x%02x"
360 " val=0x%08x %x\n",
361 dev->bus->number, PCI_SLOT(dev->devfn),
362 PCI_FUNC(dev->devfn), reg, len, *val, pdev->state);
363 }
364 else if ( acc == ACC_READ )
365 {
366 ret = pci_read_config_dword(dev, reg, val);
367 if ( (ret == 0) && test_bit(st_bit, &pdev->state) )
368 {
369 /* Cook the value. */
370 sz = res->end - res->start;
371 if ( res->flags & IORESOURCE_MEM )
372 {
373 /* this is written out explicitly for clarity */
374 *val = 0xffffffff;
375 /* bit 0 = 0 */
376 /* bit 21 = memory type */
377 /* bit 3 = prefetchable */
378 /* bit 4-31 width */
379 sz = sz >> 4; /* size in blocks of 16 byte */
380 sz = ~sz; /* invert */
381 *val = *val & (sz << 4); /* and in the size */
382 /* use read values for low 4 bits */
383 *val = *val | (orig_val & 0xf);
384 }
385 else if ( res->flags & IORESOURCE_IO )
386 {
387 *val = 0x0000ffff;
388 /* bit 10 = 01 */
389 /* bit 2-31 width */
390 sz = sz >> 2; /* size in dwords */
391 sz = ~sz & 0x0000ffff;
392 *val = *val & (sz << 2);
393 *val = *val | 0x1;
394 }
395 }
396 VERBOSE_INFO("fixed pci read: %02x:%02x:%02x reg=0x%02x len=0x%02x"
397 " val=0x%08x %x\n",
398 dev->bus->number, PCI_SLOT(dev->devfn),
399 PCI_FUNC(dev->devfn), reg, len, *val, pdev->state);
400 }
402 return ret;
403 }
406 static int do_rom_address_access(phys_dev_t *pdev, int acc, int len, u32 *val)
407 {
408 int st_bit, ret = -EINVAL;
409 struct pci_dev *dev = pdev->dev;
410 u32 orig_val, sz;
411 struct resource *res;
413 if ( len != sizeof(u32) )
414 {
415 INFO("Guest attempting sub-dword %s to ROM_ADDRESS\n",
416 (acc == ACC_READ) ? "read" : "write");
417 return -EPERM;
418 }
420 st_bit = ST_ROM_ADDRESS;
421 res = &(pdev->dev->resource[PCI_ROM_RESOURCE]);
423 if ( acc == ACC_WRITE )
424 {
425 if ( (*val == 0xffffffff) || (*val == 0xfffffffe) )
426 {
427 /* NB. 0xffffffff would be unusual, but we trap it anyway. */
428 set_bit(st_bit, &pdev->state);
429 ret = 0;
430 }
431 else
432 {
433 /* Assume guest wants simply to set the base address. */
434 clear_bit(st_bit, &pdev->state);
436 /* Check if guest tries to restore the original value. */
437 ret = pci_read_config_dword(dev, PCI_ROM_ADDRESS, &orig_val);
438 if ( (ret == 0) && (*val != orig_val) )
439 {
440 if ( (*val != 0x00000000) )
441 {
442 INFO("caution: guest tried to change rom address.\n");
443 ret = -EPERM;
444 }
445 else
446 {
447 INFO("guest disabled rom access for %02x:%02x:%02x\n",
448 dev->bus->number, PCI_SLOT(dev->devfn),
449 PCI_FUNC(dev->devfn));
450 }
451 }
452 }
453 VERBOSE_INFO("fixed pci write: %02x:%02x:%02x reg=0x%02x len=0x%02x"
454 " val=0x%08x %x\n",
455 dev->bus->number, PCI_SLOT(dev->devfn),
456 PCI_FUNC(dev->devfn), PCI_ROM_ADDRESS, len, *val, pdev->state);
457 }
458 else if ( acc == ACC_READ )
459 {
460 ret = pci_read_config_dword(dev, PCI_ROM_ADDRESS, val);
461 if ( (ret == 0) && test_bit(st_bit, &pdev->state) )
462 {
463 /* Cook the value. */
464 sz = res->end - res->start;
465 *val = 0xffffffff;
466 /* leave bit 0 untouched */
467 /* bit 1-10 reserved, harwired to 0 */
468 sz = sz >> 11; /* size is in 2KB blocks */
469 sz = ~sz;
470 *val = *val & (sz << 11);
471 *val = *val | (orig_val & 0x1);
472 }
473 VERBOSE_INFO("fixed pci read: %02x:%02x:%02x reg=0x%02x len=0x%02x"
474 " val=0x%08x %x\n",
475 dev->bus->number, PCI_SLOT(dev->devfn),
476 PCI_FUNC(dev->devfn), PCI_ROM_ADDRESS, len, *val, pdev->state);
477 }
479 return ret;
481 }
483 /*
484 * Handle a PCI config space read access if the domain has access privileges.
485 */
486 static long pci_cfgreg_read(int bus, int dev, int func, int reg,
487 int len, u32 *val)
488 {
489 int ret;
490 phys_dev_t *pdev;
492 if ( (ret = check_dev_acc(current, bus, dev, func, &pdev)) != 0 )
493 {
494 /* PCI spec states that reads from non-existent devices should return
495 * all 1s. In this case the domain has no read access, which should
496 * also look like the device is non-existent. */
497 *val = 0xFFFFFFFF;
498 return ret; /* KAF: error return seems to matter on my test machine. */
499 }
501 /* Fake out read requests for some registers. */
502 switch ( reg )
503 {
504 case PCI_BASE_ADDRESS_0:
505 ret = do_base_address_access(pdev, ACC_READ, 0, len, val);
506 break;
508 case PCI_BASE_ADDRESS_1:
509 ret = do_base_address_access(pdev, ACC_READ, 1, len, val);
510 break;
512 case PCI_BASE_ADDRESS_2:
513 ret = do_base_address_access(pdev, ACC_READ, 2, len, val);
514 break;
516 case PCI_BASE_ADDRESS_3:
517 ret = do_base_address_access(pdev, ACC_READ, 3, len, val);
518 break;
520 case PCI_BASE_ADDRESS_4:
521 ret = do_base_address_access(pdev, ACC_READ, 4, len, val);
522 break;
524 case PCI_BASE_ADDRESS_5:
525 ret = do_base_address_access(pdev, ACC_READ, 5, len, val);
526 break;
528 case PCI_ROM_ADDRESS:
529 ret = do_rom_address_access(pdev, ACC_READ, len, val);
530 break;
532 case PCI_INTERRUPT_LINE:
533 *val = pdev->dev->irq;
534 ret = 0;
535 break;
537 default:
538 ret = pci_config_read(0, bus, dev, func, reg, len, val);
539 VERBOSE_INFO("pci read : %02x:%02x:%02x reg=0x%02x len=0x%02x "
540 "val=0x%08x\n", bus, dev, func, reg, len, *val);
541 break;
542 }
544 return ret;
545 }
548 /*
549 * Handle a PCI config space write access if the domain has access privileges.
550 */
551 static long pci_cfgreg_write(int bus, int dev, int func, int reg,
552 int len, u32 val)
553 {
554 int ret;
555 phys_dev_t *pdev;
557 if ( (ret = check_dev_acc(current, bus, dev, func, &pdev)) != 0 )
558 return ret;
560 /* special treatment for some registers */
561 switch (reg)
562 {
563 case PCI_BASE_ADDRESS_0:
564 ret = do_base_address_access(pdev, ACC_WRITE, 0, len, &val);
565 break;
567 case PCI_BASE_ADDRESS_1:
568 ret = do_base_address_access(pdev, ACC_WRITE, 1, len, &val);
569 break;
571 case PCI_BASE_ADDRESS_2:
572 ret = do_base_address_access(pdev, ACC_WRITE, 2, len, &val);
573 break;
575 case PCI_BASE_ADDRESS_3:
576 ret = do_base_address_access(pdev, ACC_WRITE, 3, len, &val);
577 break;
579 case PCI_BASE_ADDRESS_4:
580 ret = do_base_address_access(pdev, ACC_WRITE, 4, len, &val);
581 break;
583 case PCI_BASE_ADDRESS_5:
584 ret = do_base_address_access(pdev, ACC_WRITE, 5, len, &val);
585 break;
587 case PCI_ROM_ADDRESS:
588 ret = do_rom_address_access(pdev, ACC_WRITE, len, &val);
589 break;
591 default:
592 if ( pdev->flags != ACC_WRITE )
593 {
594 INFO("pci write not allowed %02x:%02x:%02x: "
595 "reg=0x%02x len=0x%02x val=0x%08x\n",
596 bus, dev, func, reg, len, val);
597 ret = -EPERM;
598 }
599 else
600 {
601 ret = pci_config_write(0, bus, dev, func, reg, len, val);
602 VERBOSE_INFO("pci write: %02x:%02x:%02x reg=0x%02x len=0x%02x "
603 "val=0x%08x\n", bus, dev, func, reg, len, val);
604 }
605 break;
606 }
608 return ret;
609 }
612 static long pci_probe_root_buses(u32 *busmask)
613 {
614 phys_dev_t *pdev;
615 struct list_head *tmp;
617 memset(busmask, 0, 256/8);
619 list_for_each ( tmp, &current->pcidev_list )
620 {
621 pdev = list_entry(tmp, phys_dev_t, node);
622 set_bit(pdev->dev->bus->number, busmask);
623 }
625 return 0;
626 }
629 /*
630 * Demuxing hypercall.
631 */
632 long do_physdev_op(physdev_op_t *uop)
633 {
634 phys_dev_t *pdev;
635 physdev_op_t op;
636 long ret;
637 int irq;
639 if ( unlikely(copy_from_user(&op, uop, sizeof(op)) != 0) )
640 return -EFAULT;
642 switch ( op.cmd )
643 {
644 case PHYSDEVOP_PCI_CFGREG_READ:
645 ret = pci_cfgreg_read(op.u.pci_cfgreg_read.bus,
646 op.u.pci_cfgreg_read.dev,
647 op.u.pci_cfgreg_read.func,
648 op.u.pci_cfgreg_read.reg,
649 op.u.pci_cfgreg_read.len,
650 &op.u.pci_cfgreg_read.value);
651 break;
653 case PHYSDEVOP_PCI_CFGREG_WRITE:
654 ret = pci_cfgreg_write(op.u.pci_cfgreg_write.bus,
655 op.u.pci_cfgreg_write.dev,
656 op.u.pci_cfgreg_write.func,
657 op.u.pci_cfgreg_write.reg,
658 op.u.pci_cfgreg_write.len,
659 op.u.pci_cfgreg_write.value);
660 break;
662 case PHYSDEVOP_PCI_INITIALISE_DEVICE:
663 if ( (ret = check_dev_acc(current,
664 op.u.pci_initialise_device.bus,
665 op.u.pci_initialise_device.dev,
666 op.u.pci_initialise_device.func,
667 &pdev)) == 0 )
668 pcibios_enable_irq(pdev->dev);
669 break;
671 case PHYSDEVOP_PCI_PROBE_ROOT_BUSES:
672 ret = pci_probe_root_buses(op.u.pci_probe_root_buses.busmask);
673 break;
675 case PHYSDEVOP_IRQ_UNMASK_NOTIFY:
676 ret = pirq_guest_unmask(current);
677 break;
679 case PHYSDEVOP_IRQ_STATUS_QUERY:
680 irq = op.u.irq_status_query.irq;
681 ret = -EINVAL;
682 if ( (irq < 0) || (irq >= NR_IRQS) )
683 break;
684 op.u.irq_status_query.flags = 0;
685 /* Edge-triggered interrupts don't need an explicit unmask downcall. */
686 if ( strstr(irq_desc[irq].handler->typename, "edge") == NULL )
687 op.u.irq_status_query.flags |= PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY;
688 ret = 0;
689 break;
691 default:
692 ret = -EINVAL;
693 break;
694 }
696 copy_to_user(uop, &op, sizeof(op));
697 return ret;
698 }
700 /* Test if boot params specify this device should NOT be visible to DOM0
701 * (e.g. so that another domain can control it instead) */
702 int pcidev_dom0_hidden(struct pci_dev *dev)
703 {
704 extern char opt_physdev_dom0_hide[];
705 char cmp[10] = "(.......)";
707 strncpy(&cmp[1], dev->slot_name, 7);
709 if ( strstr(opt_physdev_dom0_hide, dev->slot_name) == NULL )
710 return 0;
712 return 1;
713 }
716 /* Domain 0 has read access to all devices. */
717 void physdev_init_dom0(struct domain *p)
718 {
719 struct pci_dev *dev;
720 phys_dev_t *pdev;
722 INFO("Give DOM0 read access to all PCI devices\n");
724 pci_for_each_dev(dev)
725 {
726 if ( pcidev_dom0_hidden(dev) )
727 {
728 printk("Hiding PCI device %s from DOM0\n", dev->slot_name);
729 continue;
730 }
732 /* Skip bridges and other peculiarities for now.
733 *
734 * Note that this can prevent the guest from detecting devices
735 * with fn>0 on slots where the fn=0 device is a bridge. We
736 * can identify such slots by looking at the multifunction bit
737 * (top bit of hdr_type, masked out in dev->hdr_type).
738 *
739 * In Linux2.4 we find all devices because the detection code
740 * scans all functions if the read of the fn=0 device's header
741 * type fails.
742 *
743 * In Linux2.6 we set pcibios_scan_all_fns().
744 */
745 if ( (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) &&
746 (dev->hdr_type != PCI_HEADER_TYPE_CARDBUS) )
747 continue;
748 pdev = xmalloc(sizeof(phys_dev_t));
749 pdev->dev = dev;
750 pdev->flags = ACC_WRITE;
751 pdev->state = 0;
752 pdev->owner = p;
753 list_add(&pdev->node, &p->pcidev_list);
754 }
756 set_bit(DF_PHYSDEV, &p->flags);
757 }