ia64/xen-unstable

view xen/arch/x86/io_apic.c @ 9715:9a273aabb839

New IO-APIC ACK method seems to cause problems on some systems
(e.g., Dell 1850). Disable it by default for now, but allow the
new mwethod to be tested by passing boot parameter 'new_ack'
to Xen.

You can tell which ACK method you are using because Xen prints
out "Using old ACK method" or "Using new ACK method" during boot.

This workaround can be removed if/when the problems with the new
ACK method are flushed out.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Fri Apr 14 14:14:24 2006 +0100 (2006-04-14)
parents bb0dc0ae23bb
children b39365343de0
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
23 #include <xen/config.h>
24 #include <xen/lib.h>
25 #include <xen/init.h>
26 #include <xen/irq.h>
27 #include <xen/delay.h>
28 #include <xen/sched.h>
29 #include <xen/acpi.h>
30 #include <xen/keyhandler.h>
31 #include <asm/io.h>
32 #include <asm/mc146818rtc.h>
33 #include <asm/smp.h>
34 #include <asm/desc.h>
35 #include <mach_apic.h>
36 #include <io_ports.h>
38 #define set_irq_info(irq, mask) ((void)0)
39 #define set_native_irq_info(irq, mask) ((void)0)
41 /* Different to Linux: our implementation can be simpler. */
42 #define make_8259A_irq(irq) (io_apic_irqs &= ~(1<<(irq)))
44 int (*ioapic_renumber_irq)(int ioapic, int irq);
45 atomic_t irq_mis_count;
47 /* Where if anywhere is the i8259 connect in external int mode */
48 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
50 static DEFINE_SPINLOCK(ioapic_lock);
52 int skip_ioapic_setup;
54 /*
55 * # of IRQ routing registers
56 */
57 int nr_ioapic_registers[MAX_IO_APICS];
59 int disable_timer_pin_1 __initdata;
61 /*
62 * Rough estimation of how many shared IRQs there are, can
63 * be changed anytime.
64 */
65 #define MAX_PLUS_SHARED_IRQS NR_IRQS
66 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
68 /*
69 * This is performance-critical, we want to do it O(1)
70 *
71 * the indexing order of this array favors 1:1 mappings
72 * between pins and IRQs.
73 */
75 static struct irq_pin_list {
76 int apic, pin, next;
77 } irq_2_pin[PIN_MAP_SIZE];
78 static int irq_2_pin_free_entry = NR_IRQS;
80 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
82 /*
83 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
84 * shared ISA-space IRQs, so we have to support them. We are super
85 * fast in the common case, and fast for shared ISA-space IRQs.
86 */
87 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
88 {
89 struct irq_pin_list *entry = irq_2_pin + irq;
91 while (entry->next) {
92 BUG_ON((entry->apic == apic) && (entry->pin == pin));
93 entry = irq_2_pin + entry->next;
94 }
96 BUG_ON((entry->apic == apic) && (entry->pin == pin));
98 if (entry->pin != -1) {
99 if (irq_2_pin_free_entry >= PIN_MAP_SIZE)
100 panic("io_apic.c: whoops");
101 entry->next = irq_2_pin_free_entry;
102 entry = irq_2_pin + entry->next;
103 irq_2_pin_free_entry = entry->next;
104 entry->next = 0;
105 }
106 entry->apic = apic;
107 entry->pin = pin;
108 }
110 static void remove_pin_at_irq(unsigned int irq, int apic, int pin)
111 {
112 struct irq_pin_list *entry, *prev;
114 for (entry = &irq_2_pin[irq]; ; entry = &irq_2_pin[entry->next]) {
115 if ((entry->apic == apic) && (entry->pin == pin))
116 break;
117 if (!entry->next)
118 BUG();
119 }
121 entry->pin = entry->apic = -1;
123 if (entry != &irq_2_pin[irq]) {
124 /* Removed entry is not at head of list. */
125 prev = &irq_2_pin[irq];
126 while (&irq_2_pin[prev->next] != entry)
127 prev = &irq_2_pin[prev->next];
128 prev->next = entry->next;
129 entry->next = irq_2_pin_free_entry;
130 irq_2_pin_free_entry = entry - irq_2_pin;
131 } else if (entry->next != 0) {
132 /* Removed entry is at head of multi-item list. */
133 prev = entry;
134 entry = &irq_2_pin[entry->next];
135 *prev = *entry;
136 entry->pin = entry->apic = -1;
137 entry->next = irq_2_pin_free_entry;
138 irq_2_pin_free_entry = entry - irq_2_pin;
139 }
140 }
142 /*
143 * Reroute an IRQ to a different pin.
144 */
145 static void __init replace_pin_at_irq(unsigned int irq,
146 int oldapic, int oldpin,
147 int newapic, int newpin)
148 {
149 struct irq_pin_list *entry = irq_2_pin + irq;
151 while (1) {
152 if (entry->apic == oldapic && entry->pin == oldpin) {
153 entry->apic = newapic;
154 entry->pin = newpin;
155 }
156 if (!entry->next)
157 break;
158 entry = irq_2_pin + entry->next;
159 }
160 }
162 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
163 {
164 struct irq_pin_list *entry = irq_2_pin + irq;
165 unsigned int pin, reg;
167 for (;;) {
168 pin = entry->pin;
169 if (pin == -1)
170 break;
171 reg = io_apic_read(entry->apic, 0x10 + pin*2);
172 reg &= ~disable;
173 reg |= enable;
174 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
175 if (!entry->next)
176 break;
177 entry = irq_2_pin + entry->next;
178 }
179 }
181 /* mask = 1 */
182 static void __mask_IO_APIC_irq (unsigned int irq)
183 {
184 __modify_IO_APIC_irq(irq, 0x00010000, 0);
185 }
187 /* mask = 0 */
188 static void __unmask_IO_APIC_irq (unsigned int irq)
189 {
190 __modify_IO_APIC_irq(irq, 0, 0x00010000);
191 }
193 /* trigger = 0 */
194 static void __edge_IO_APIC_irq (unsigned int irq)
195 {
196 __modify_IO_APIC_irq(irq, 0, 0x00008000);
197 }
199 /* trigger = 1 */
200 static void __level_IO_APIC_irq (unsigned int irq)
201 {
202 __modify_IO_APIC_irq(irq, 0x00008000, 0);
203 }
205 /* mask = 1, trigger = 0 */
206 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
207 {
208 __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
209 }
211 /* mask = 0, trigger = 1 */
212 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
213 {
214 __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
215 }
217 static void mask_IO_APIC_irq (unsigned int irq)
218 {
219 unsigned long flags;
221 spin_lock_irqsave(&ioapic_lock, flags);
222 __mask_IO_APIC_irq(irq);
223 spin_unlock_irqrestore(&ioapic_lock, flags);
224 }
226 static void unmask_IO_APIC_irq (unsigned int irq)
227 {
228 unsigned long flags;
230 spin_lock_irqsave(&ioapic_lock, flags);
231 __unmask_IO_APIC_irq(irq);
232 spin_unlock_irqrestore(&ioapic_lock, flags);
233 }
235 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
236 {
237 struct IO_APIC_route_entry entry;
238 unsigned long flags;
240 /* Check delivery_mode to be sure we're not clearing an SMI pin */
241 spin_lock_irqsave(&ioapic_lock, flags);
242 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
243 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
244 spin_unlock_irqrestore(&ioapic_lock, flags);
245 if (entry.delivery_mode == dest_SMI)
246 return;
248 /*
249 * Disable it in the IO-APIC irq-routing table:
250 */
251 memset(&entry, 0, sizeof(entry));
252 entry.mask = 1;
253 spin_lock_irqsave(&ioapic_lock, flags);
254 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
255 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
256 spin_unlock_irqrestore(&ioapic_lock, flags);
257 }
259 static void clear_IO_APIC (void)
260 {
261 int apic, pin;
263 for (apic = 0; apic < nr_ioapics; apic++)
264 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
265 clear_IO_APIC_pin(apic, pin);
266 }
268 #ifdef CONFIG_SMP
269 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
270 {
271 unsigned long flags;
272 int pin;
273 struct irq_pin_list *entry = irq_2_pin + irq;
274 unsigned int apicid_value;
275 cpumask_t tmp;
277 cpus_and(tmp, cpumask, cpu_online_map);
278 if (cpus_empty(tmp))
279 tmp = TARGET_CPUS;
281 cpus_and(cpumask, tmp, CPU_MASK_ALL);
283 apicid_value = cpu_mask_to_apicid(cpumask);
284 /* Prepare to do the io_apic_write */
285 apicid_value = apicid_value << 24;
286 spin_lock_irqsave(&ioapic_lock, flags);
287 for (;;) {
288 pin = entry->pin;
289 if (pin == -1)
290 break;
291 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
292 if (!entry->next)
293 break;
294 entry = irq_2_pin + entry->next;
295 }
296 set_irq_info(irq, cpumask);
297 spin_unlock_irqrestore(&ioapic_lock, flags);
298 }
299 #endif /* CONFIG_SMP */
301 /*
302 * Find the IRQ entry number of a certain pin.
303 */
304 static int find_irq_entry(int apic, int pin, int type)
305 {
306 int i;
308 for (i = 0; i < mp_irq_entries; i++)
309 if (mp_irqs[i].mpc_irqtype == type &&
310 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
311 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
312 mp_irqs[i].mpc_dstirq == pin)
313 return i;
315 return -1;
316 }
318 /*
319 * Find the pin to which IRQ[irq] (ISA) is connected
320 */
321 static int __init find_isa_irq_pin(int irq, int type)
322 {
323 int i;
325 for (i = 0; i < mp_irq_entries; i++) {
326 int lbus = mp_irqs[i].mpc_srcbus;
328 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
329 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
330 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
331 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
332 ) &&
333 (mp_irqs[i].mpc_irqtype == type) &&
334 (mp_irqs[i].mpc_srcbusirq == irq))
336 return mp_irqs[i].mpc_dstirq;
337 }
338 return -1;
339 }
341 static int __init find_isa_irq_apic(int irq, int type)
342 {
343 int i;
345 for (i = 0; i < mp_irq_entries; i++) {
346 int lbus = mp_irqs[i].mpc_srcbus;
348 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
349 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
350 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
351 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
352 ) &&
353 (mp_irqs[i].mpc_irqtype == type) &&
354 (mp_irqs[i].mpc_srcbusirq == irq))
355 break;
356 }
357 if (i < mp_irq_entries) {
358 int apic;
359 for(apic = 0; apic < nr_ioapics; apic++) {
360 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
361 return apic;
362 }
363 }
365 return -1;
366 }
368 /*
369 * Find a specific PCI IRQ entry.
370 * Not an __init, possibly needed by modules
371 */
372 static int pin_2_irq(int idx, int apic, int pin);
374 /*
375 * This function currently is only a helper for the i386 smp boot process where
376 * we need to reprogram the ioredtbls to cater for the cpus which have come online
377 * so mask in all cases should simply be TARGET_CPUS
378 */
379 #ifdef CONFIG_SMP
380 void __init setup_ioapic_dest(void)
381 {
382 int pin, ioapic, irq, irq_entry;
384 if (skip_ioapic_setup == 1)
385 return;
387 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
388 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
389 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
390 if (irq_entry == -1)
391 continue;
392 irq = pin_2_irq(irq_entry, ioapic, pin);
393 set_ioapic_affinity_irq(irq, TARGET_CPUS);
394 }
396 }
397 }
398 #endif
400 /*
401 * EISA Edge/Level control register, ELCR
402 */
403 static int EISA_ELCR(unsigned int irq)
404 {
405 if (irq < 16) {
406 unsigned int port = 0x4d0 + (irq >> 3);
407 return (inb(port) >> (irq & 7)) & 1;
408 }
409 apic_printk(APIC_VERBOSE, KERN_INFO
410 "Broken MPtable reports ISA irq %d\n", irq);
411 return 0;
412 }
414 /* EISA interrupts are always polarity zero and can be edge or level
415 * trigger depending on the ELCR value. If an interrupt is listed as
416 * EISA conforming in the MP table, that means its trigger type must
417 * be read in from the ELCR */
419 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
420 #define default_EISA_polarity(idx) (0)
422 /* ISA interrupts are always polarity zero edge triggered,
423 * when listed as conforming in the MP table. */
425 #define default_ISA_trigger(idx) (0)
426 #define default_ISA_polarity(idx) (0)
428 /* PCI interrupts are always polarity one level triggered,
429 * when listed as conforming in the MP table. */
431 #define default_PCI_trigger(idx) (1)
432 #define default_PCI_polarity(idx) (1)
434 /* MCA interrupts are always polarity zero level triggered,
435 * when listed as conforming in the MP table. */
437 #define default_MCA_trigger(idx) (1)
438 #define default_MCA_polarity(idx) (0)
440 /* NEC98 interrupts are always polarity zero edge triggered,
441 * when listed as conforming in the MP table. */
443 #define default_NEC98_trigger(idx) (0)
444 #define default_NEC98_polarity(idx) (0)
446 static int __init MPBIOS_polarity(int idx)
447 {
448 int bus = mp_irqs[idx].mpc_srcbus;
449 int polarity;
451 /*
452 * Determine IRQ line polarity (high active or low active):
453 */
454 switch (mp_irqs[idx].mpc_irqflag & 3)
455 {
456 case 0: /* conforms, ie. bus-type dependent polarity */
457 {
458 switch (mp_bus_id_to_type[bus])
459 {
460 case MP_BUS_ISA: /* ISA pin */
461 {
462 polarity = default_ISA_polarity(idx);
463 break;
464 }
465 case MP_BUS_EISA: /* EISA pin */
466 {
467 polarity = default_EISA_polarity(idx);
468 break;
469 }
470 case MP_BUS_PCI: /* PCI pin */
471 {
472 polarity = default_PCI_polarity(idx);
473 break;
474 }
475 case MP_BUS_MCA: /* MCA pin */
476 {
477 polarity = default_MCA_polarity(idx);
478 break;
479 }
480 case MP_BUS_NEC98: /* NEC 98 pin */
481 {
482 polarity = default_NEC98_polarity(idx);
483 break;
484 }
485 default:
486 {
487 printk(KERN_WARNING "broken BIOS!!\n");
488 polarity = 1;
489 break;
490 }
491 }
492 break;
493 }
494 case 1: /* high active */
495 {
496 polarity = 0;
497 break;
498 }
499 case 2: /* reserved */
500 {
501 printk(KERN_WARNING "broken BIOS!!\n");
502 polarity = 1;
503 break;
504 }
505 case 3: /* low active */
506 {
507 polarity = 1;
508 break;
509 }
510 default: /* invalid */
511 {
512 printk(KERN_WARNING "broken BIOS!!\n");
513 polarity = 1;
514 break;
515 }
516 }
517 return polarity;
518 }
520 static int MPBIOS_trigger(int idx)
521 {
522 int bus = mp_irqs[idx].mpc_srcbus;
523 int trigger;
525 /*
526 * Determine IRQ trigger mode (edge or level sensitive):
527 */
528 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
529 {
530 case 0: /* conforms, ie. bus-type dependent */
531 {
532 switch (mp_bus_id_to_type[bus])
533 {
534 case MP_BUS_ISA: /* ISA pin */
535 {
536 trigger = default_ISA_trigger(idx);
537 break;
538 }
539 case MP_BUS_EISA: /* EISA pin */
540 {
541 trigger = default_EISA_trigger(idx);
542 break;
543 }
544 case MP_BUS_PCI: /* PCI pin */
545 {
546 trigger = default_PCI_trigger(idx);
547 break;
548 }
549 case MP_BUS_MCA: /* MCA pin */
550 {
551 trigger = default_MCA_trigger(idx);
552 break;
553 }
554 case MP_BUS_NEC98: /* NEC 98 pin */
555 {
556 trigger = default_NEC98_trigger(idx);
557 break;
558 }
559 default:
560 {
561 printk(KERN_WARNING "broken BIOS!!\n");
562 trigger = 1;
563 break;
564 }
565 }
566 break;
567 }
568 case 1: /* edge */
569 {
570 trigger = 0;
571 break;
572 }
573 case 2: /* reserved */
574 {
575 printk(KERN_WARNING "broken BIOS!!\n");
576 trigger = 1;
577 break;
578 }
579 case 3: /* level */
580 {
581 trigger = 1;
582 break;
583 }
584 default: /* invalid */
585 {
586 printk(KERN_WARNING "broken BIOS!!\n");
587 trigger = 0;
588 break;
589 }
590 }
591 return trigger;
592 }
594 static inline int irq_polarity(int idx)
595 {
596 return MPBIOS_polarity(idx);
597 }
599 static inline int irq_trigger(int idx)
600 {
601 return MPBIOS_trigger(idx);
602 }
604 static int pin_2_irq(int idx, int apic, int pin)
605 {
606 int irq, i;
607 int bus = mp_irqs[idx].mpc_srcbus;
609 /*
610 * Debugging check, we are in big trouble if this message pops up!
611 */
612 if (mp_irqs[idx].mpc_dstirq != pin)
613 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
615 switch (mp_bus_id_to_type[bus])
616 {
617 case MP_BUS_ISA: /* ISA pin */
618 case MP_BUS_EISA:
619 case MP_BUS_MCA:
620 case MP_BUS_NEC98:
621 {
622 irq = mp_irqs[idx].mpc_srcbusirq;
623 break;
624 }
625 case MP_BUS_PCI: /* PCI pin */
626 {
627 /*
628 * PCI IRQs are mapped in order
629 */
630 i = irq = 0;
631 while (i < apic)
632 irq += nr_ioapic_registers[i++];
633 irq += pin;
635 /*
636 * For MPS mode, so far only needed by ES7000 platform
637 */
638 if (ioapic_renumber_irq)
639 irq = ioapic_renumber_irq(apic, irq);
641 break;
642 }
643 default:
644 {
645 printk(KERN_ERR "unknown bus type %d.\n",bus);
646 irq = 0;
647 break;
648 }
649 }
651 return irq;
652 }
654 static inline int IO_APIC_irq_trigger(int irq)
655 {
656 int apic, idx, pin;
658 for (apic = 0; apic < nr_ioapics; apic++) {
659 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
660 idx = find_irq_entry(apic,pin,mp_INT);
661 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
662 return irq_trigger(idx);
663 }
664 }
665 /*
666 * nonexistent IRQs are edge default
667 */
668 return 0;
669 }
671 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
672 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
674 int assign_irq_vector(int irq)
675 {
676 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
678 BUG_ON(irq >= NR_IRQ_VECTORS);
679 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
680 return IO_APIC_VECTOR(irq);
681 next:
682 current_vector += 8;
684 /* Skip the hypercall vector. */
685 if (current_vector == HYPERCALL_VECTOR)
686 goto next;
688 /* Skip the Linux/BSD fast-trap vector. */
689 if (current_vector == 0x80)
690 goto next;
692 if (current_vector >= FIRST_SYSTEM_VECTOR) {
693 offset++;
694 if (!(offset%8))
695 return -ENOSPC;
696 current_vector = FIRST_DEVICE_VECTOR + offset;
697 }
699 vector_irq[current_vector] = irq;
700 if (irq != AUTO_ASSIGN)
701 IO_APIC_VECTOR(irq) = current_vector;
703 return current_vector;
704 }
706 static struct hw_interrupt_type ioapic_level_type;
707 static struct hw_interrupt_type ioapic_edge_type;
709 #define IOAPIC_AUTO -1
710 #define IOAPIC_EDGE 0
711 #define IOAPIC_LEVEL 1
713 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
714 {
715 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
716 trigger == IOAPIC_LEVEL)
717 irq_desc[vector].handler = &ioapic_level_type;
718 else
719 irq_desc[vector].handler = &ioapic_edge_type;
720 }
722 static void __init setup_IO_APIC_irqs(void)
723 {
724 struct IO_APIC_route_entry entry;
725 int apic, pin, idx, irq, first_notcon = 1, vector;
726 unsigned long flags;
728 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
730 for (apic = 0; apic < nr_ioapics; apic++) {
731 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
733 /*
734 * add it to the IO-APIC irq-routing table:
735 */
736 memset(&entry,0,sizeof(entry));
738 entry.delivery_mode = INT_DELIVERY_MODE;
739 entry.dest_mode = INT_DEST_MODE;
740 entry.mask = 0; /* enable IRQ */
741 entry.dest.logical.logical_dest =
742 cpu_mask_to_apicid(TARGET_CPUS);
744 idx = find_irq_entry(apic,pin,mp_INT);
745 if (idx == -1) {
746 if (first_notcon) {
747 apic_printk(APIC_VERBOSE, KERN_DEBUG
748 " IO-APIC (apicid-pin) %d-%d",
749 mp_ioapics[apic].mpc_apicid,
750 pin);
751 first_notcon = 0;
752 } else
753 apic_printk(APIC_VERBOSE, ", %d-%d",
754 mp_ioapics[apic].mpc_apicid, pin);
755 continue;
756 }
758 entry.trigger = irq_trigger(idx);
759 entry.polarity = irq_polarity(idx);
761 if (irq_trigger(idx)) {
762 entry.trigger = 1;
763 entry.mask = 1;
764 }
766 irq = pin_2_irq(idx, apic, pin);
767 /*
768 * skip adding the timer int on secondary nodes, which causes
769 * a small but painful rift in the time-space continuum
770 */
771 if (multi_timer_check(apic, irq))
772 continue;
773 else
774 add_pin_to_irq(irq, apic, pin);
776 if (!apic && !IO_APIC_IRQ(irq))
777 continue;
779 if (IO_APIC_IRQ(irq)) {
780 vector = assign_irq_vector(irq);
781 entry.vector = vector;
782 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
784 if (!apic && (irq < 16))
785 disable_8259A_irq(irq);
786 }
787 spin_lock_irqsave(&ioapic_lock, flags);
788 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
789 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
790 set_native_irq_info(entry.vector, TARGET_CPUS);
791 spin_unlock_irqrestore(&ioapic_lock, flags);
792 }
793 }
795 if (!first_notcon)
796 apic_printk(APIC_VERBOSE, " not connected.\n");
797 }
799 /*
800 * Set up the 8259A-master output pin:
801 */
802 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
803 {
804 struct IO_APIC_route_entry entry;
805 unsigned long flags;
807 memset(&entry,0,sizeof(entry));
809 disable_8259A_irq(0);
811 /* mask LVT0 */
812 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
814 /*
815 * We use logical delivery to get the timer IRQ
816 * to the first CPU.
817 */
818 entry.dest_mode = INT_DEST_MODE;
819 entry.mask = 0; /* unmask IRQ now */
820 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
821 entry.delivery_mode = INT_DELIVERY_MODE;
822 entry.polarity = 0;
823 entry.trigger = 0;
824 entry.vector = vector;
826 /*
827 * The timer IRQ doesn't have to know that behind the
828 * scene we have a 8259A-master in AEOI mode ...
829 */
830 irq_desc[IO_APIC_VECTOR(0)].handler = &ioapic_edge_type;
832 /*
833 * Add it to the IO-APIC irq-routing table:
834 */
835 spin_lock_irqsave(&ioapic_lock, flags);
836 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
837 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
838 spin_unlock_irqrestore(&ioapic_lock, flags);
840 enable_8259A_irq(0);
841 }
843 static inline void UNEXPECTED_IO_APIC(void)
844 {
845 }
847 void __init __print_IO_APIC(void)
848 {
849 int apic, i;
850 union IO_APIC_reg_00 reg_00;
851 union IO_APIC_reg_01 reg_01;
852 union IO_APIC_reg_02 reg_02;
853 union IO_APIC_reg_03 reg_03;
854 unsigned long flags;
856 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
857 for (i = 0; i < nr_ioapics; i++)
858 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
859 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
861 /*
862 * We are a bit conservative about what we expect. We have to
863 * know about every hardware change ASAP.
864 */
865 printk(KERN_INFO "testing the IO APIC.......................\n");
867 for (apic = 0; apic < nr_ioapics; apic++) {
869 spin_lock_irqsave(&ioapic_lock, flags);
870 reg_00.raw = io_apic_read(apic, 0);
871 reg_01.raw = io_apic_read(apic, 1);
872 if (reg_01.bits.version >= 0x10)
873 reg_02.raw = io_apic_read(apic, 2);
874 if (reg_01.bits.version >= 0x20)
875 reg_03.raw = io_apic_read(apic, 3);
876 spin_unlock_irqrestore(&ioapic_lock, flags);
878 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
879 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
880 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
881 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
882 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
883 if (reg_00.bits.ID >= get_physical_broadcast())
884 UNEXPECTED_IO_APIC();
885 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
886 UNEXPECTED_IO_APIC();
888 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
889 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
890 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
891 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
892 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
893 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
894 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
895 (reg_01.bits.entries != 0x2E) &&
896 (reg_01.bits.entries != 0x3F)
897 )
898 UNEXPECTED_IO_APIC();
900 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
901 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
902 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
903 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
904 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
905 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
906 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
907 )
908 UNEXPECTED_IO_APIC();
909 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
910 UNEXPECTED_IO_APIC();
912 /*
913 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
914 * but the value of reg_02 is read as the previous read register
915 * value, so ignore it if reg_02 == reg_01.
916 */
917 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
918 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
919 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
920 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
921 UNEXPECTED_IO_APIC();
922 }
924 /*
925 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
926 * or reg_03, but the value of reg_0[23] is read as the previous read
927 * register value, so ignore it if reg_03 == reg_0[12].
928 */
929 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
930 reg_03.raw != reg_01.raw) {
931 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
932 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
933 if (reg_03.bits.__reserved_1)
934 UNEXPECTED_IO_APIC();
935 }
937 printk(KERN_DEBUG ".... IRQ redirection table:\n");
939 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
940 " Stat Dest Deli Vect: \n");
942 for (i = 0; i <= reg_01.bits.entries; i++) {
943 struct IO_APIC_route_entry entry;
945 spin_lock_irqsave(&ioapic_lock, flags);
946 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
947 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
948 spin_unlock_irqrestore(&ioapic_lock, flags);
950 printk(KERN_DEBUG " %02x %03X %02X ",
951 i,
952 entry.dest.logical.logical_dest,
953 entry.dest.physical.physical_dest
954 );
956 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
957 entry.mask,
958 entry.trigger,
959 entry.irr,
960 entry.polarity,
961 entry.delivery_status,
962 entry.dest_mode,
963 entry.delivery_mode,
964 entry.vector
965 );
966 }
967 }
968 printk(KERN_INFO "Using vector-based indexing\n");
969 printk(KERN_DEBUG "IRQ to pin mappings:\n");
970 for (i = 0; i < NR_IRQS; i++) {
971 struct irq_pin_list *entry = irq_2_pin + i;
972 if (entry->pin < 0)
973 continue;
974 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
975 for (;;) {
976 printk("-> %d:%d", entry->apic, entry->pin);
977 if (!entry->next)
978 break;
979 entry = irq_2_pin + entry->next;
980 }
981 printk("\n");
982 }
984 printk(KERN_INFO ".................................... done.\n");
986 return;
987 }
989 void print_IO_APIC(void)
990 {
991 if (apic_verbosity != APIC_QUIET)
992 __print_IO_APIC();
993 }
995 void print_IO_APIC_keyhandler(unsigned char key)
996 {
997 __print_IO_APIC();
998 }
1000 static void __init enable_IO_APIC(void)
1002 union IO_APIC_reg_01 reg_01;
1003 int i8259_apic, i8259_pin;
1004 int i, apic;
1005 unsigned long flags;
1007 for (i = 0; i < PIN_MAP_SIZE; i++) {
1008 irq_2_pin[i].pin = -1;
1009 irq_2_pin[i].next = 0;
1012 /* Initialise dynamic irq_2_pin free list. */
1013 for (i = NR_IRQS; i < PIN_MAP_SIZE; i++)
1014 irq_2_pin[i].next = i + 1;
1016 /*
1017 * The number of IO-APIC IRQ registers (== #pins):
1018 */
1019 for (apic = 0; apic < nr_ioapics; apic++) {
1020 spin_lock_irqsave(&ioapic_lock, flags);
1021 reg_01.raw = io_apic_read(apic, 1);
1022 spin_unlock_irqrestore(&ioapic_lock, flags);
1023 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1025 for(apic = 0; apic < nr_ioapics; apic++) {
1026 int pin;
1027 /* See if any of the pins is in ExtINT mode */
1028 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1029 struct IO_APIC_route_entry entry;
1030 spin_lock_irqsave(&ioapic_lock, flags);
1031 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1032 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1033 spin_unlock_irqrestore(&ioapic_lock, flags);
1036 /* If the interrupt line is enabled and in ExtInt mode
1037 * I have found the pin where the i8259 is connected.
1038 */
1039 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1040 ioapic_i8259.apic = apic;
1041 ioapic_i8259.pin = pin;
1042 goto found_i8259;
1046 found_i8259:
1047 /* Look to see what if the MP table has reported the ExtINT */
1048 /* If we could not find the appropriate pin by looking at the ioapic
1049 * the i8259 probably is not connected the ioapic but give the
1050 * mptable a chance anyway.
1051 */
1052 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1053 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1054 /* Trust the MP table if nothing is setup in the hardware */
1055 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1056 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1057 ioapic_i8259.pin = i8259_pin;
1058 ioapic_i8259.apic = i8259_apic;
1060 /* Complain if the MP table and the hardware disagree */
1061 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1062 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1064 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1067 /*
1068 * Do not trust the IO-APIC being empty at bootup
1069 */
1070 clear_IO_APIC();
1073 /*
1074 * Not an __init, needed by the reboot code
1075 */
1076 void disable_IO_APIC(void)
1078 /*
1079 * Clear the IO-APIC before rebooting:
1080 */
1081 clear_IO_APIC();
1083 /*
1084 * If the i8259 is routed through an IOAPIC
1085 * Put that IOAPIC in virtual wire mode
1086 * so legacy interrupts can be delivered.
1087 */
1088 if (ioapic_i8259.pin != -1) {
1089 struct IO_APIC_route_entry entry;
1090 unsigned long flags;
1092 memset(&entry, 0, sizeof(entry));
1093 entry.mask = 0; /* Enabled */
1094 entry.trigger = 0; /* Edge */
1095 entry.irr = 0;
1096 entry.polarity = 0; /* High */
1097 entry.delivery_status = 0;
1098 entry.dest_mode = 0; /* Physical */
1099 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1100 entry.vector = 0;
1101 entry.dest.physical.physical_dest =
1102 GET_APIC_ID(apic_read(APIC_ID));
1104 /*
1105 * Add it to the IO-APIC irq-routing table:
1106 */
1107 spin_lock_irqsave(&ioapic_lock, flags);
1108 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1109 *(((int *)&entry)+1));
1110 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1111 *(((int *)&entry)+0));
1112 spin_unlock_irqrestore(&ioapic_lock, flags);
1114 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1117 /*
1118 * function to set the IO-APIC physical IDs based on the
1119 * values stored in the MPC table.
1121 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1122 */
1124 #ifndef CONFIG_X86_NUMAQ
1125 static void __init setup_ioapic_ids_from_mpc(void)
1127 union IO_APIC_reg_00 reg_00;
1128 physid_mask_t phys_id_present_map;
1129 int apic;
1130 int i;
1131 unsigned char old_id;
1132 unsigned long flags;
1134 /*
1135 * Don't check I/O APIC IDs for xAPIC systems. They have
1136 * no meaning without the serial APIC bus.
1137 */
1138 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 < 15))
1139 return;
1141 /*
1142 * This is broken; anything with a real cpu count has to
1143 * circumvent this idiocy regardless.
1144 */
1145 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1147 /*
1148 * Set the IOAPIC ID to the value stored in the MPC table.
1149 */
1150 for (apic = 0; apic < nr_ioapics; apic++) {
1152 /* Read the register 0 value */
1153 spin_lock_irqsave(&ioapic_lock, flags);
1154 reg_00.raw = io_apic_read(apic, 0);
1155 spin_unlock_irqrestore(&ioapic_lock, flags);
1157 old_id = mp_ioapics[apic].mpc_apicid;
1159 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1160 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1161 apic, mp_ioapics[apic].mpc_apicid);
1162 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1163 reg_00.bits.ID);
1164 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1167 /*
1168 * Sanity check, is the ID really free? Every APIC in a
1169 * system must have a unique ID or we get lots of nice
1170 * 'stuck on smp_invalidate_needed IPI wait' messages.
1171 */
1172 if (check_apicid_used(phys_id_present_map,
1173 mp_ioapics[apic].mpc_apicid)) {
1174 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1175 apic, mp_ioapics[apic].mpc_apicid);
1176 for (i = 0; i < get_physical_broadcast(); i++)
1177 if (!physid_isset(i, phys_id_present_map))
1178 break;
1179 if (i >= get_physical_broadcast())
1180 panic("Max APIC ID exceeded!\n");
1181 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1182 i);
1183 physid_set(i, phys_id_present_map);
1184 mp_ioapics[apic].mpc_apicid = i;
1185 } else {
1186 physid_mask_t tmp;
1187 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1188 apic_printk(APIC_VERBOSE, "Setting %d in the "
1189 "phys_id_present_map\n",
1190 mp_ioapics[apic].mpc_apicid);
1191 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1195 /*
1196 * We need to adjust the IRQ routing table
1197 * if the ID changed.
1198 */
1199 if (old_id != mp_ioapics[apic].mpc_apicid)
1200 for (i = 0; i < mp_irq_entries; i++)
1201 if (mp_irqs[i].mpc_dstapic == old_id)
1202 mp_irqs[i].mpc_dstapic
1203 = mp_ioapics[apic].mpc_apicid;
1205 /*
1206 * Read the right value from the MPC table and
1207 * write it into the ID register.
1208 */
1209 apic_printk(APIC_VERBOSE, KERN_INFO
1210 "...changing IO-APIC physical APIC ID to %d ...",
1211 mp_ioapics[apic].mpc_apicid);
1213 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1214 spin_lock_irqsave(&ioapic_lock, flags);
1215 io_apic_write(apic, 0, reg_00.raw);
1216 spin_unlock_irqrestore(&ioapic_lock, flags);
1218 /*
1219 * Sanity check
1220 */
1221 spin_lock_irqsave(&ioapic_lock, flags);
1222 reg_00.raw = io_apic_read(apic, 0);
1223 spin_unlock_irqrestore(&ioapic_lock, flags);
1224 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1225 printk("could not set ID!\n");
1226 else
1227 apic_printk(APIC_VERBOSE, " ok.\n");
1230 #else
1231 static void __init setup_ioapic_ids_from_mpc(void) { }
1232 #endif
1234 /*
1235 * There is a nasty bug in some older SMP boards, their mptable lies
1236 * about the timer IRQ. We do the following to work around the situation:
1238 * - timer IRQ defaults to IO-APIC IRQ
1239 * - if this function detects that timer IRQs are defunct, then we fall
1240 * back to ISA timer IRQs
1241 */
1242 static int __init timer_irq_works(void)
1244 unsigned long t1 = jiffies;
1246 local_irq_enable();
1247 /* Let ten ticks pass... */
1248 mdelay((10 * 1000) / HZ);
1250 /*
1251 * Expect a few ticks at least, to be sure some possible
1252 * glue logic does not lock up after one or two first
1253 * ticks in a non-ExtINT mode. Also the local APIC
1254 * might have cached one ExtINT interrupt. Finally, at
1255 * least one tick may be lost due to delays.
1256 */
1257 if (jiffies - t1 > 4)
1258 return 1;
1260 return 0;
1263 /*
1264 * In the SMP+IOAPIC case it might happen that there are an unspecified
1265 * number of pending IRQ events unhandled. These cases are very rare,
1266 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1267 * better to do it this way as thus we do not have to be aware of
1268 * 'pending' interrupts in the IRQ path, except at this point.
1269 */
1270 /*
1271 * Edge triggered needs to resend any interrupt
1272 * that was delayed but this is now handled in the device
1273 * independent code.
1274 */
1276 /*
1277 * Starting up a edge-triggered IO-APIC interrupt is
1278 * nasty - we need to make sure that we get the edge.
1279 * If it is already asserted for some reason, we need
1280 * return 1 to indicate that is was pending.
1282 * This is not complete - we should be able to fake
1283 * an edge even if it isn't on the 8259A...
1284 */
1285 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1287 int was_pending = 0;
1288 unsigned long flags;
1290 spin_lock_irqsave(&ioapic_lock, flags);
1291 if (irq < 16) {
1292 disable_8259A_irq(irq);
1293 if (i8259A_irq_pending(irq))
1294 was_pending = 1;
1296 __unmask_IO_APIC_irq(irq);
1297 spin_unlock_irqrestore(&ioapic_lock, flags);
1299 return was_pending;
1302 /*
1303 * Once we have recorded IRQ_PENDING already, we can mask the
1304 * interrupt for real. This prevents IRQ storms from unhandled
1305 * devices.
1306 */
1307 static void ack_edge_ioapic_irq(unsigned int irq)
1309 if ((irq_desc[IO_APIC_VECTOR(irq)].status & (IRQ_PENDING | IRQ_DISABLED))
1310 == (IRQ_PENDING | IRQ_DISABLED))
1311 mask_IO_APIC_irq(irq);
1312 ack_APIC_irq();
1315 /*
1316 * Level triggered interrupts can just be masked,
1317 * and shutting down and starting up the interrupt
1318 * is the same as enabling and disabling them -- except
1319 * with a startup need to return a "was pending" value.
1321 * Level triggered interrupts are special because we
1322 * do not touch any IO-APIC register while handling
1323 * them. We ack the APIC in the end-IRQ handler, not
1324 * in the start-IRQ-handler. Protection against reentrance
1325 * from the same interrupt is still provided, both by the
1326 * generic IRQ layer and by the fact that an unacked local
1327 * APIC does not accept IRQs.
1328 */
1329 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1331 unmask_IO_APIC_irq(irq);
1333 return 0; /* don't check for pending */
1336 static int new_ack;
1337 boolean_param("new_ack", new_ack);
1339 static void mask_and_ack_level_ioapic_irq (unsigned int irq)
1341 unsigned long v;
1342 int i;
1344 if ( new_ack )
1345 return;
1347 mask_IO_APIC_irq(irq);
1348 /*
1349 * It appears there is an erratum which affects at least version 0x11
1350 * of I/O APIC (that's the 82093AA and cores integrated into various
1351 * chipsets). Under certain conditions a level-triggered interrupt is
1352 * erroneously delivered as edge-triggered one but the respective IRR
1353 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1354 * message but it will never arrive and further interrupts are blocked
1355 * from the source. The exact reason is so far unknown, but the
1356 * phenomenon was observed when two consecutive interrupt requests
1357 * from a given source get delivered to the same CPU and the source is
1358 * temporarily disabled in between.
1360 * A workaround is to simulate an EOI message manually. We achieve it
1361 * by setting the trigger mode to edge and then to level when the edge
1362 * trigger mode gets detected in the TMR of a local APIC for a
1363 * level-triggered interrupt. We mask the source for the time of the
1364 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1365 * The idea is from Manfred Spraul. --macro
1366 */
1367 i = IO_APIC_VECTOR(irq);
1369 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1371 ack_APIC_irq();
1373 if (!(v & (1 << (i & 0x1f)))) {
1374 atomic_inc(&irq_mis_count);
1375 spin_lock(&ioapic_lock);
1376 __edge_IO_APIC_irq(irq);
1377 __level_IO_APIC_irq(irq);
1378 spin_unlock(&ioapic_lock);
1382 static void end_level_ioapic_irq (unsigned int irq)
1384 unsigned long v;
1385 int i;
1387 if ( !new_ack )
1389 unmask_IO_APIC_irq(irq);
1390 return;
1393 /*
1394 * It appears there is an erratum which affects at least version 0x11
1395 * of I/O APIC (that's the 82093AA and cores integrated into various
1396 * chipsets). Under certain conditions a level-triggered interrupt is
1397 * erroneously delivered as edge-triggered one but the respective IRR
1398 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1399 * message but it will never arrive and further interrupts are blocked
1400 * from the source. The exact reason is so far unknown, but the
1401 * phenomenon was observed when two consecutive interrupt requests
1402 * from a given source get delivered to the same CPU and the source is
1403 * temporarily disabled in between.
1405 * A workaround is to simulate an EOI message manually. We achieve it
1406 * by setting the trigger mode to edge and then to level when the edge
1407 * trigger mode gets detected in the TMR of a local APIC for a
1408 * level-triggered interrupt. We mask the source for the time of the
1409 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1410 * The idea is from Manfred Spraul. --macro
1411 */
1412 i = IO_APIC_VECTOR(irq);
1414 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1416 ack_APIC_irq();
1418 if (!(v & (1 << (i & 0x1f)))) {
1419 atomic_inc(&irq_mis_count);
1420 spin_lock(&ioapic_lock);
1421 __mask_and_edge_IO_APIC_irq(irq);
1422 __unmask_and_level_IO_APIC_irq(irq);
1423 spin_unlock(&ioapic_lock);
1427 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1429 int irq = vector_to_irq(vector);
1430 return startup_edge_ioapic_irq(irq);
1433 static void ack_edge_ioapic_vector(unsigned int vector)
1435 int irq = vector_to_irq(vector);
1436 ack_edge_ioapic_irq(irq);
1439 static unsigned int startup_level_ioapic_vector(unsigned int vector)
1441 int irq = vector_to_irq(vector);
1442 return startup_level_ioapic_irq (irq);
1445 static void mask_and_ack_level_ioapic_vector(unsigned int vector)
1447 int irq = vector_to_irq(vector);
1448 mask_and_ack_level_ioapic_irq(irq);
1451 static void end_level_ioapic_vector(unsigned int vector)
1453 int irq = vector_to_irq(vector);
1454 end_level_ioapic_irq(irq);
1457 static void mask_IO_APIC_vector(unsigned int vector)
1459 int irq = vector_to_irq(vector);
1460 mask_IO_APIC_irq(irq);
1463 static void unmask_IO_APIC_vector(unsigned int vector)
1465 int irq = vector_to_irq(vector);
1466 unmask_IO_APIC_irq(irq);
1469 static void set_ioapic_affinity_vector(
1470 unsigned int vector, cpumask_t cpu_mask)
1472 int irq = vector_to_irq(vector);
1474 set_native_irq_info(vector, cpu_mask);
1475 set_ioapic_affinity_irq(irq, cpu_mask);
1478 static void disable_edge_ioapic_vector(unsigned int vector)
1482 static void end_edge_ioapic_vector(unsigned int vector)
1486 /*
1487 * Level and edge triggered IO-APIC interrupts need different handling,
1488 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1489 * handled with the level-triggered descriptor, but that one has slightly
1490 * more overhead. Level-triggered interrupts cannot be handled with the
1491 * edge-triggered handler, without risking IRQ storms and other ugly
1492 * races.
1493 */
1494 static struct hw_interrupt_type ioapic_edge_type = {
1495 .typename = "IO-APIC-edge",
1496 .startup = startup_edge_ioapic_vector,
1497 .shutdown = disable_edge_ioapic_vector,
1498 .enable = unmask_IO_APIC_vector,
1499 .disable = disable_edge_ioapic_vector,
1500 .ack = ack_edge_ioapic_vector,
1501 .end = end_edge_ioapic_vector,
1502 .set_affinity = set_ioapic_affinity_vector,
1503 };
1505 static struct hw_interrupt_type ioapic_level_type = {
1506 .typename = "IO-APIC-level",
1507 .startup = startup_level_ioapic_vector,
1508 .shutdown = mask_IO_APIC_vector,
1509 .enable = unmask_IO_APIC_vector,
1510 .disable = mask_IO_APIC_vector,
1511 .ack = mask_and_ack_level_ioapic_vector,
1512 .end = end_level_ioapic_vector,
1513 .set_affinity = set_ioapic_affinity_vector,
1514 };
1516 static inline void init_IO_APIC_traps(void)
1518 int irq;
1519 /* Xen: This is way simpler than the Linux implementation. */
1520 for (irq = 0; irq < 16 ; irq++)
1521 if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq))
1522 make_8259A_irq(irq);
1525 static void enable_lapic_vector(unsigned int vector)
1527 unsigned long v;
1529 v = apic_read(APIC_LVT0);
1530 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1533 static void disable_lapic_vector(unsigned int vector)
1535 unsigned long v;
1537 v = apic_read(APIC_LVT0);
1538 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1541 static void ack_lapic_vector(unsigned int vector)
1543 ack_APIC_irq();
1546 static void end_lapic_vector(unsigned int vector) { /* nothing */ }
1548 static struct hw_interrupt_type lapic_irq_type = {
1549 .typename = "local-APIC-edge",
1550 .startup = NULL, /* startup_irq() not used for IRQ0 */
1551 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1552 .enable = enable_lapic_vector,
1553 .disable = disable_lapic_vector,
1554 .ack = ack_lapic_vector,
1555 .end = end_lapic_vector
1556 };
1558 /*
1559 * This looks a bit hackish but it's about the only one way of sending
1560 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1561 * not support the ExtINT mode, unfortunately. We need to send these
1562 * cycles as some i82489DX-based boards have glue logic that keeps the
1563 * 8259A interrupt line asserted until INTA. --macro
1564 */
1565 static inline void unlock_ExtINT_logic(void)
1567 int apic, pin, i;
1568 struct IO_APIC_route_entry entry0, entry1;
1569 unsigned char save_control, save_freq_select;
1570 unsigned long flags;
1572 pin = find_isa_irq_pin(8, mp_INT);
1573 apic = find_isa_irq_apic(8, mp_INT);
1574 if (pin == -1)
1575 return;
1577 spin_lock_irqsave(&ioapic_lock, flags);
1578 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1579 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1580 spin_unlock_irqrestore(&ioapic_lock, flags);
1581 clear_IO_APIC_pin(apic, pin);
1583 memset(&entry1, 0, sizeof(entry1));
1585 entry1.dest_mode = 0; /* physical delivery */
1586 entry1.mask = 0; /* unmask IRQ now */
1587 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1588 entry1.delivery_mode = dest_ExtINT;
1589 entry1.polarity = entry0.polarity;
1590 entry1.trigger = 0;
1591 entry1.vector = 0;
1593 spin_lock_irqsave(&ioapic_lock, flags);
1594 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1595 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1596 spin_unlock_irqrestore(&ioapic_lock, flags);
1598 save_control = CMOS_READ(RTC_CONTROL);
1599 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1600 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1601 RTC_FREQ_SELECT);
1602 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1604 i = 100;
1605 while (i-- > 0) {
1606 mdelay(10);
1607 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1608 i -= 10;
1611 CMOS_WRITE(save_control, RTC_CONTROL);
1612 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1613 clear_IO_APIC_pin(apic, pin);
1615 spin_lock_irqsave(&ioapic_lock, flags);
1616 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1617 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1618 spin_unlock_irqrestore(&ioapic_lock, flags);
1621 /*
1622 * This code may look a bit paranoid, but it's supposed to cooperate with
1623 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1624 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1625 * fanatically on his truly buggy board.
1626 */
1627 static inline void check_timer(void)
1629 int apic1, pin1, apic2, pin2;
1630 int vector;
1632 /*
1633 * get/set the timer IRQ vector:
1634 */
1635 disable_8259A_irq(0);
1636 vector = assign_irq_vector(0);
1638 irq_desc[IO_APIC_VECTOR(0)].action = irq_desc[LEGACY_VECTOR(0)].action;
1639 irq_desc[IO_APIC_VECTOR(0)].depth = 0;
1640 irq_desc[IO_APIC_VECTOR(0)].status &= ~IRQ_DISABLED;
1642 /*
1643 * Subtle, code in do_timer_interrupt() expects an AEOI
1644 * mode for the 8259A whenever interrupts are routed
1645 * through I/O APICs. Also IRQ0 has to be enabled in
1646 * the 8259A which implies the virtual wire has to be
1647 * disabled in the local APIC.
1648 */
1649 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1650 init_8259A(1);
1651 /* XEN: Ripped out the legacy missed-tick logic, so below is not needed. */
1652 /*timer_ack = 1;*/
1653 /*enable_8259A_irq(0);*/
1655 pin1 = find_isa_irq_pin(0, mp_INT);
1656 apic1 = find_isa_irq_apic(0, mp_INT);
1657 pin2 = ioapic_i8259.pin;
1658 apic2 = ioapic_i8259.apic;
1660 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1661 vector, apic1, pin1, apic2, pin2);
1663 if (pin1 != -1) {
1664 /*
1665 * Ok, does IRQ0 through the IOAPIC work?
1666 */
1667 unmask_IO_APIC_irq(0);
1668 if (timer_irq_works()) {
1669 if (disable_timer_pin_1 > 0)
1670 clear_IO_APIC_pin(apic1, pin1);
1671 return;
1673 clear_IO_APIC_pin(apic1, pin1);
1674 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
1675 "IO-APIC\n");
1678 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1679 if (pin2 != -1) {
1680 printk("\n..... (found pin %d) ...", pin2);
1681 /*
1682 * legacy devices should be connected to IO APIC #0
1683 */
1684 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1685 if (timer_irq_works()) {
1686 printk("works.\n");
1687 if (pin1 != -1)
1688 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1689 else
1690 add_pin_to_irq(0, apic2, pin2);
1691 return;
1693 /*
1694 * Cleanup, just in case ...
1695 */
1696 clear_IO_APIC_pin(apic2, pin2);
1698 printk(" failed.\n");
1700 if (nmi_watchdog == NMI_IO_APIC) {
1701 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1702 nmi_watchdog = 0;
1705 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1707 disable_8259A_irq(0);
1708 irq_desc[vector].handler = &lapic_irq_type;
1709 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1710 enable_8259A_irq(0);
1712 if (timer_irq_works()) {
1713 printk(" works.\n");
1714 return;
1716 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1717 printk(" failed.\n");
1719 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1721 /*timer_ack = 0;*/
1722 init_8259A(0);
1723 make_8259A_irq(0);
1724 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1726 unlock_ExtINT_logic();
1728 if (timer_irq_works()) {
1729 printk(" works.\n");
1730 return;
1732 printk(" failed :(.\n");
1733 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
1734 "report. Then try booting with the 'noapic' option");
1737 /*
1739 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1740 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1741 * Linux doesn't really care, as it's not actually used
1742 * for any interrupt handling anyway.
1743 */
1744 #define PIC_IRQS (1 << PIC_CASCADE_IR)
1746 void __init setup_IO_APIC(void)
1748 enable_IO_APIC();
1750 if (acpi_ioapic)
1751 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1752 else
1753 io_apic_irqs = ~PIC_IRQS;
1755 printk("ENABLING IO-APIC IRQs\n");
1756 printk(" -> Using %s ACK method\n", new_ack ? "new" : "old");
1758 /*
1759 * Set up IO-APIC IRQ routing.
1760 */
1761 if (!acpi_ioapic)
1762 setup_ioapic_ids_from_mpc();
1763 sync_Arb_IDs();
1764 setup_IO_APIC_irqs();
1765 init_IO_APIC_traps();
1766 check_timer();
1767 print_IO_APIC();
1769 register_keyhandler('z', print_IO_APIC_keyhandler, "print ioapic info");
1772 /* --------------------------------------------------------------------------
1773 ACPI-based IOAPIC Configuration
1774 -------------------------------------------------------------------------- */
1776 #ifdef CONFIG_ACPI_BOOT
1778 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1780 union IO_APIC_reg_00 reg_00;
1781 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
1782 physid_mask_t tmp;
1783 unsigned long flags;
1784 int i = 0;
1786 /*
1787 * The P4 platform supports up to 256 APIC IDs on two separate APIC
1788 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1789 * supports up to 16 on one shared APIC bus.
1791 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1792 * advantage of new APIC bus architecture.
1793 */
1795 if (physids_empty(apic_id_map))
1796 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
1798 spin_lock_irqsave(&ioapic_lock, flags);
1799 reg_00.raw = io_apic_read(ioapic, 0);
1800 spin_unlock_irqrestore(&ioapic_lock, flags);
1802 if (apic_id >= get_physical_broadcast()) {
1803 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1804 "%d\n", ioapic, apic_id, reg_00.bits.ID);
1805 apic_id = reg_00.bits.ID;
1808 /*
1809 * Every APIC in a system must have a unique ID or we get lots of nice
1810 * 'stuck on smp_invalidate_needed IPI wait' messages.
1811 */
1812 if (check_apicid_used(apic_id_map, apic_id)) {
1814 for (i = 0; i < get_physical_broadcast(); i++) {
1815 if (!check_apicid_used(apic_id_map, i))
1816 break;
1819 if (i == get_physical_broadcast())
1820 panic("Max apic_id exceeded!\n");
1822 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1823 "trying %d\n", ioapic, apic_id, i);
1825 apic_id = i;
1828 tmp = apicid_to_cpu_present(apic_id);
1829 physids_or(apic_id_map, apic_id_map, tmp);
1831 if (reg_00.bits.ID != apic_id) {
1832 reg_00.bits.ID = apic_id;
1834 spin_lock_irqsave(&ioapic_lock, flags);
1835 io_apic_write(ioapic, 0, reg_00.raw);
1836 reg_00.raw = io_apic_read(ioapic, 0);
1837 spin_unlock_irqrestore(&ioapic_lock, flags);
1839 /* Sanity check */
1840 if (reg_00.bits.ID != apic_id) {
1841 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
1842 return -1;
1846 apic_printk(APIC_VERBOSE, KERN_INFO
1847 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1849 return apic_id;
1853 int __init io_apic_get_version (int ioapic)
1855 union IO_APIC_reg_01 reg_01;
1856 unsigned long flags;
1858 spin_lock_irqsave(&ioapic_lock, flags);
1859 reg_01.raw = io_apic_read(ioapic, 1);
1860 spin_unlock_irqrestore(&ioapic_lock, flags);
1862 return reg_01.bits.version;
1866 int __init io_apic_get_redir_entries (int ioapic)
1868 union IO_APIC_reg_01 reg_01;
1869 unsigned long flags;
1871 spin_lock_irqsave(&ioapic_lock, flags);
1872 reg_01.raw = io_apic_read(ioapic, 1);
1873 spin_unlock_irqrestore(&ioapic_lock, flags);
1875 return reg_01.bits.entries;
1879 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1881 struct IO_APIC_route_entry entry;
1882 unsigned long flags;
1884 if (!IO_APIC_IRQ(irq)) {
1885 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1886 ioapic);
1887 return -EINVAL;
1890 /*
1891 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1892 * Note that we mask (disable) IRQs now -- these get enabled when the
1893 * corresponding device driver registers for this IRQ.
1894 */
1896 memset(&entry,0,sizeof(entry));
1898 entry.delivery_mode = INT_DELIVERY_MODE;
1899 entry.dest_mode = INT_DEST_MODE;
1900 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1901 entry.trigger = edge_level;
1902 entry.polarity = active_high_low;
1903 entry.mask = 1;
1905 /*
1906 * IRQs < 16 are already in the irq_2_pin[] map
1907 */
1908 if (irq >= 16)
1909 add_pin_to_irq(irq, ioapic, pin);
1911 entry.vector = assign_irq_vector(irq);
1913 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
1914 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
1915 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1916 edge_level, active_high_low);
1918 ioapic_register_intr(irq, entry.vector, edge_level);
1920 if (!ioapic && (irq < 16))
1921 disable_8259A_irq(irq);
1923 spin_lock_irqsave(&ioapic_lock, flags);
1924 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1925 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1926 set_native_irq_info(entry.vector, TARGET_CPUS);
1927 spin_unlock_irqrestore(&ioapic_lock, flags);
1929 return 0;
1932 #endif /*CONFIG_ACPI_BOOT*/
1934 static int ioapic_physbase_to_id(unsigned long physbase)
1936 int apic;
1937 for ( apic = 0; apic < nr_ioapics; apic++ )
1938 if ( mp_ioapics[apic].mpc_apicaddr == physbase )
1939 return apic;
1940 return -EINVAL;
1943 int ioapic_guest_read(unsigned long physbase, unsigned int reg, u32 *pval)
1945 int apic;
1946 unsigned long flags;
1948 if ( (apic = ioapic_physbase_to_id(physbase)) < 0 )
1949 return apic;
1951 spin_lock_irqsave(&ioapic_lock, flags);
1952 *pval = io_apic_read(apic, reg);
1953 spin_unlock_irqrestore(&ioapic_lock, flags);
1955 return 0;
1958 #define WARN_BOGUS_WRITE(f, a...) \
1959 DPRINTK("\n%s: apic=%d, pin=%d, old_irq=%d, new_irq=%d\n" \
1960 "%s: old_entry=%08x, new_entry=%08x\n" \
1961 "%s: " f, __FUNCTION__, apic, pin, old_irq, new_irq, \
1962 __FUNCTION__, *(u32 *)&old_rte, *(u32 *)&new_rte, \
1963 __FUNCTION__ , ##a )
1965 int ioapic_guest_write(unsigned long physbase, unsigned int reg, u32 val)
1967 int apic, pin, old_irq = -1, new_irq = -1;
1968 struct IO_APIC_route_entry old_rte = { 0 }, new_rte = { 0 };
1969 unsigned long flags;
1971 if ( (apic = ioapic_physbase_to_id(physbase)) < 0 )
1972 return apic;
1974 /* Only write to the first half of a route entry. */
1975 if ( (reg < 0x10) || (reg & 1) )
1976 return 0;
1978 pin = (reg - 0x10) >> 1;
1980 /* Write first half from guest; second half is target info. */
1981 *(u32 *)&new_rte = val;
1982 new_rte.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1984 /*
1985 * What about weird destination types?
1986 * SMI: Ignore? Ought to be set up by the BIOS.
1987 * NMI: Ignore? Watchdog functionality is Xen's concern.
1988 * INIT: Definitely ignore: probably a guest OS bug.
1989 * ExtINT: Ignore? Linux only asserts this at start of day.
1990 * For now, print a message and return an error. We can fix up on demand.
1991 */
1992 if ( new_rte.delivery_mode > dest_LowestPrio )
1994 printk("ERROR: Attempt to write weird IOAPIC destination mode!\n");
1995 printk(" APIC=%d/%d, lo-reg=%x\n", apic, pin, val);
1996 return -EINVAL;
1999 /*
2000 * The guest does not know physical APIC arrangement (flat vs. cluster).
2001 * Apply genapic conventions for this platform.
2002 */
2003 new_rte.delivery_mode = INT_DELIVERY_MODE;
2004 new_rte.dest_mode = INT_DEST_MODE;
2006 spin_lock_irqsave(&ioapic_lock, flags);
2008 /* Read first (interesting) half of current routing entry. */
2009 *(u32 *)&old_rte = io_apic_read(apic, 0x10 + 2 * pin);
2011 /* No change to the first half of the routing entry? Bail quietly. */
2012 if ( *(u32 *)&old_rte == *(u32 *)&new_rte )
2014 spin_unlock_irqrestore(&ioapic_lock, flags);
2015 return 0;
2018 if ( old_rte.vector >= FIRST_DEVICE_VECTOR )
2019 old_irq = vector_irq[old_rte.vector];
2020 if ( new_rte.vector >= FIRST_DEVICE_VECTOR )
2021 new_irq = vector_irq[new_rte.vector];
2023 if ( (old_irq != new_irq) && (old_irq != -1) && IO_APIC_IRQ(old_irq) )
2025 if ( irq_desc[IO_APIC_VECTOR(old_irq)].action )
2027 WARN_BOGUS_WRITE("Attempt to remove IO-APIC pin of in-use IRQ!\n");
2028 spin_unlock_irqrestore(&ioapic_lock, flags);
2029 return 0;
2032 remove_pin_at_irq(old_irq, apic, pin);
2035 if ( (new_irq != -1) && IO_APIC_IRQ(new_irq) )
2037 if ( irq_desc[IO_APIC_VECTOR(new_irq)].action )
2039 WARN_BOGUS_WRITE("Attempt to %s IO-APIC pin for in-use IRQ!\n",
2040 (old_irq != new_irq) ? "add" : "modify");
2041 spin_unlock_irqrestore(&ioapic_lock, flags);
2042 return 0;
2045 /* Set the correct irq-handling type. */
2046 irq_desc[IO_APIC_VECTOR(new_irq)].handler = new_rte.trigger ?
2047 &ioapic_level_type: &ioapic_edge_type;
2049 if ( old_irq != new_irq )
2050 add_pin_to_irq(new_irq, apic, pin);
2052 /* Mask iff level triggered. */
2053 new_rte.mask = new_rte.trigger;
2055 else if ( !new_rte.mask )
2057 /* This pin leads nowhere but the guest has not masked it. */
2058 WARN_BOGUS_WRITE("Installing bogus unmasked IO-APIC entry!\n");
2059 new_rte.mask = 1;
2063 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&new_rte) + 0));
2064 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&new_rte) + 1));
2066 spin_unlock_irqrestore(&ioapic_lock, flags);
2068 return 0;
2071 void dump_ioapic_irq_info(void)
2073 struct irq_pin_list *entry;
2074 struct IO_APIC_route_entry rte;
2075 unsigned int irq, pin, printed = 0;
2076 unsigned long flags;
2078 for ( irq = 0; irq < NR_IRQS; irq++ )
2080 entry = &irq_2_pin[irq];
2081 if ( entry->pin == -1 )
2082 continue;
2084 if ( !printed++ )
2085 printk("IO-APIC interrupt information:\n");
2087 printk(" IRQ%3d Vec%3d:\n", irq, irq_to_vector(irq));
2089 for ( ; ; )
2091 pin = entry->pin;
2093 printk(" Apic 0x%02x, Pin %2d: ", entry->apic, pin);
2095 spin_lock_irqsave(&ioapic_lock, flags);
2096 *(((int *)&rte) + 0) = io_apic_read(entry->apic, 0x10 + 2 * pin);
2097 *(((int *)&rte) + 1) = io_apic_read(entry->apic, 0x11 + 2 * pin);
2098 spin_unlock_irqrestore(&ioapic_lock, flags);
2100 printk("vector=%u, delivery_mode=%u, dest_mode=%s, "
2101 "delivery_status=%d, polarity=%d, irr=%d, "
2102 "trigger=%s, mask=%d\n",
2103 rte.vector, rte.delivery_mode,
2104 rte.dest_mode ? "logical" : "physical",
2105 rte.delivery_status, rte.polarity, rte.irr,
2106 rte.trigger ? "level" : "edge", rte.mask);
2108 if ( entry->next == 0 )
2109 break;
2110 entry = &irq_2_pin[entry->next];