ia64/xen-unstable

view xen/arch/ia64/vmx/vmx_phy_mode.c @ 16177:98ac6d05aed2

[IA64] Enable switch to PHY_D mmu mode

Last patch for PHY_D mmu mode

Signed-off-by: Tristan Gingold <tgingold@free.fr>
author Alex Williamson <alex.williamson@hp.com>
date Sun Oct 21 15:58:00 2007 -0600 (2007-10-21)
parents 5c56ce7b9892
children 98defc4f3bf9
line source
1 /* -*- Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
2 /*
3 * vmx_phy_mode.c: emulating domain physical mode.
4 * Copyright (c) 2005, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 *
19 * Arun Sharma (arun.sharma@intel.com)
20 * Kun Tian (Kevin Tian) (kevin.tian@intel.com)
21 * Xuefei Xu (Anthony Xu) (anthony.xu@intel.com)
22 */
25 #include <asm/processor.h>
26 #include <asm/gcc_intrin.h>
27 #include <asm/vmx_phy_mode.h>
28 #include <asm/pgtable.h>
29 #include <asm/vmmu.h>
30 #include <asm/debugger.h>
32 #define MODE_IND(psr) \
33 (((psr).it << 2) + ((psr).dt << 1) + (psr).rt)
35 #define SW_BAD 0 /* Bad mode transitition */
36 #define SW_V2P_DT 1 /* Physical emulation is activated */
37 #define SW_V2P_D 2 /* Physical emulation is activated (only for data) */
38 #define SW_P2V 3 /* Exit physical mode emulation */
39 #define SW_SELF 4 /* No mode transition */
40 #define SW_NOP 5 /* Mode transition, but without action required */
42 /*
43 * Special notes:
44 * - Index by it/dt/rt sequence
45 * - Only existing mode transitions are allowed in this table
46 * - If gva happens to be rr0 and rr4, only allowed case is identity
47 * mapping (gva=gpa), or panic! (How?)
48 */
49 static const unsigned char mm_switch_table[8][8] = {
50 /* 2004/09/12(Kevin): Allow switch to self */
51 /*
52 * (it,dt,rt): (0,0,0) -> (1,1,1)
53 * This kind of transition usually occurs in the very early
54 * stage of Linux boot up procedure. Another case is in efi
55 * and pal calls. (see "arch/ia64/kernel/head.S")
56 *
57 * (it,dt,rt): (0,0,0) -> (0,1,1)
58 * This kind of transition is found when OSYa exits efi boot
59 * service. Due to gva = gpa in this case (Same region),
60 * data access can be satisfied though itlb entry for physical
61 * emulation is hit.
62 */
63 {SW_SELF,0, 0, SW_NOP, 0, 0, 0, SW_P2V},
64 {0, 0, 0, 0, 0, 0, 0, 0},
65 {0, 0, 0, 0, 0, 0, 0, 0},
66 /*
67 * (it,dt,rt): (0,1,1) -> (1,1,1)
68 * This kind of transition is found in OSYa.
69 *
70 * (it,dt,rt): (0,1,1) -> (0,0,0)
71 * This kind of transition is found in OSYa
72 */
73 {SW_NOP, 0, 0, SW_SELF,0, 0, 0, SW_P2V},
74 /* (1,0,0)->(1,1,1) */
75 {0, 0, 0, 0, 0, 0, 0, SW_P2V},
76 /*
77 * (it,dt,rt): (1,0,1) -> (1,1,1)
78 * This kind of transition usually occurs when Linux returns
79 * from the low level TLB miss handlers.
80 * (see "arch/ia64/kernel/ivt.S")
81 */
82 {0, 0, 0, 0, 0, SW_SELF,0, SW_P2V},
83 {0, 0, 0, 0, 0, 0, 0, 0},
84 /*
85 * (it,dt,rt): (1,1,1) -> (1,0,1)
86 * This kind of transition usually occurs in Linux low level
87 * TLB miss handler. (see "arch/ia64/kernel/ivt.S")
88 *
89 * (it,dt,rt): (1,1,1) -> (0,0,0)
90 * This kind of transition usually occurs in pal and efi calls,
91 * which requires running in physical mode.
92 * (see "arch/ia64/kernel/head.S")
93 * (1,1,1)->(1,0,0)
94 */
95 {SW_V2P_DT, 0, 0, 0, SW_V2P_D, SW_V2P_D, 0, SW_SELF},
96 };
98 void
99 physical_mode_init(VCPU *vcpu)
100 {
101 vcpu->arch.arch_vmx.mmu_mode = VMX_MMU_PHY_DT;
102 }
104 void
105 physical_tlb_miss(VCPU *vcpu, u64 vadr, int type)
106 {
107 u64 pte;
109 pte = (vadr & _PAGE_PPN_MASK) | PHY_PAGE_WB;
110 thash_vhpt_insert(vcpu, pte, (PAGE_SHIFT << 2), vadr, type);
111 }
113 void
114 vmx_init_all_rr(VCPU *vcpu)
115 {
116 // enable vhpt in guest physical mode
117 vcpu->arch.metaphysical_rid_dt |= 1;
119 VMX(vcpu, vrr[VRN0]) = 0x38;
120 vcpu->arch.metaphysical_saved_rr0 = vrrtomrr(vcpu, 0x38);
121 VMX(vcpu, vrr[VRN1]) = 0x38;
122 VMX(vcpu, vrr[VRN2]) = 0x38;
123 VMX(vcpu, vrr[VRN3]) = 0x38;
124 VMX(vcpu, vrr[VRN4]) = 0x38;
125 vcpu->arch.metaphysical_saved_rr4 = vrrtomrr(vcpu, 0x38);
126 VMX(vcpu, vrr[VRN5]) = 0x38;
127 VMX(vcpu, vrr[VRN6]) = 0x38;
128 VMX(vcpu, vrr[VRN7]) = 0x738;
129 }
131 extern void * pal_vaddr;
133 void
134 vmx_load_all_rr(VCPU *vcpu)
135 {
136 unsigned long psr;
137 unsigned long rr0, rr4;
139 switch (vcpu->arch.arch_vmx.mmu_mode) {
140 case VMX_MMU_VIRTUAL:
141 rr0 = vcpu->arch.metaphysical_saved_rr0;
142 rr4 = vcpu->arch.metaphysical_saved_rr4;
143 break;
144 case VMX_MMU_PHY_DT:
145 rr0 = vcpu->arch.metaphysical_rid_dt;
146 rr4 = vcpu->arch.metaphysical_rid_dt;
147 break;
148 case VMX_MMU_PHY_D:
149 rr0 = vcpu->arch.metaphysical_rid_d;
150 rr4 = vcpu->arch.metaphysical_rid_d;
151 break;
152 default:
153 panic_domain(NULL, "bad mmu mode value");
154 }
156 psr = ia64_clear_ic();
158 ia64_set_rr((VRN0 << VRN_SHIFT), rr0);
159 ia64_dv_serialize_data();
160 ia64_set_rr((VRN4 << VRN_SHIFT), rr4);
161 ia64_dv_serialize_data();
162 ia64_set_rr((VRN1 << VRN_SHIFT), vrrtomrr(vcpu, VMX(vcpu, vrr[VRN1])));
163 ia64_dv_serialize_data();
164 ia64_set_rr((VRN2 << VRN_SHIFT), vrrtomrr(vcpu, VMX(vcpu, vrr[VRN2])));
165 ia64_dv_serialize_data();
166 ia64_set_rr((VRN3 << VRN_SHIFT), vrrtomrr(vcpu, VMX(vcpu, vrr[VRN3])));
167 ia64_dv_serialize_data();
168 ia64_set_rr((VRN5 << VRN_SHIFT), vrrtomrr(vcpu, VMX(vcpu, vrr[VRN5])));
169 ia64_dv_serialize_data();
170 ia64_set_rr((VRN6 << VRN_SHIFT), vrrtomrr(vcpu, VMX(vcpu, vrr[VRN6])));
171 ia64_dv_serialize_data();
172 vmx_switch_rr7(vrrtomrr(vcpu,VMX(vcpu, vrr[VRN7])),
173 (void *)vcpu->arch.vhpt.hash, pal_vaddr);
174 ia64_set_pta(VMX(vcpu, mpta));
175 vmx_ia64_set_dcr(vcpu);
177 ia64_srlz_d();
178 ia64_set_psr(psr);
179 ia64_srlz_i();
180 }
182 void
183 switch_to_physical_rid(VCPU *vcpu)
184 {
185 u64 psr;
186 u64 rr;
188 switch (vcpu->arch.arch_vmx.mmu_mode) {
189 case VMX_MMU_PHY_DT:
190 rr = vcpu->arch.metaphysical_rid_dt;
191 break;
192 case VMX_MMU_PHY_D:
193 rr = vcpu->arch.metaphysical_rid_d;
194 break;
195 default:
196 panic_domain(NULL, "bad mmu mode value");
197 }
199 psr = ia64_clear_ic();
200 ia64_set_rr(VRN0<<VRN_SHIFT, rr);
201 ia64_dv_serialize_data();
202 ia64_set_rr(VRN4<<VRN_SHIFT, rr);
203 ia64_srlz_d();
205 ia64_set_psr(psr);
206 ia64_srlz_i();
207 return;
208 }
210 void
211 switch_to_virtual_rid(VCPU *vcpu)
212 {
213 u64 psr;
215 psr = ia64_clear_ic();
216 ia64_set_rr(VRN0<<VRN_SHIFT, vcpu->arch.metaphysical_saved_rr0);
217 ia64_dv_serialize_data();
218 ia64_set_rr(VRN4<<VRN_SHIFT, vcpu->arch.metaphysical_saved_rr4);
219 ia64_srlz_d();
220 ia64_set_psr(psr);
221 ia64_srlz_i();
222 return;
223 }
225 static int mm_switch_action(IA64_PSR opsr, IA64_PSR npsr)
226 {
227 return mm_switch_table[MODE_IND(opsr)][MODE_IND(npsr)];
228 }
230 void
231 switch_mm_mode(VCPU *vcpu, IA64_PSR old_psr, IA64_PSR new_psr)
232 {
233 int act;
234 act = mm_switch_action(old_psr, new_psr);
235 perfc_incra(vmx_switch_mm_mode, act);
236 switch (act) {
237 case SW_V2P_DT:
238 vcpu->arch.arch_vmx.mmu_mode = VMX_MMU_PHY_DT;
239 switch_to_physical_rid(vcpu);
240 break;
241 case SW_V2P_D:
242 // printk("V -> P_D mode transition: (0x%lx -> 0x%lx)\n",
243 // old_psr.val, new_psr.val);
244 vcpu->arch.arch_vmx.mmu_mode = VMX_MMU_PHY_D;
245 switch_to_physical_rid(vcpu);
246 break;
247 case SW_P2V:
248 // printk("P -> V mode transition: (0x%lx -> 0x%lx)\n",
249 // old_psr.val, new_psr.val);
250 vcpu->arch.arch_vmx.mmu_mode = VMX_MMU_VIRTUAL;
251 switch_to_virtual_rid(vcpu);
252 break;
253 case SW_SELF:
254 printk("Switch to self-0x%lx!!! MM mode doesn't change...\n",
255 old_psr.val);
256 break;
257 case SW_NOP:
258 // printk("No action required for mode transition: (0x%lx -> 0x%lx)\n",
259 // old_psr.val, new_psr.val);
260 break;
261 default:
262 /* Sanity check */
263 panic_domain(vcpu_regs(vcpu),
264 "Unexpected virtual <--> physical mode transition, "
265 "old:%lx, new:%lx\n", old_psr.val, new_psr.val);
266 break;
267 }
268 return;
269 }
271 void
272 check_mm_mode_switch (VCPU *vcpu, IA64_PSR old_psr, IA64_PSR new_psr)
273 {
274 if (old_psr.dt != new_psr.dt ||
275 old_psr.it != new_psr.it ||
276 old_psr.rt != new_psr.rt) {
277 switch_mm_mode(vcpu, old_psr, new_psr);
278 debugger_event(XEN_IA64_DEBUG_ON_MMU);
279 }
280 }
283 /*
284 * In physical mode, insert tc/tr for region 0 and 4 uses
285 * RID[0] and RID[4] which is for physical mode emulation.
286 * However what those inserted tc/tr wants is rid for
287 * virtual mode. So original virtual rid needs to be restored
288 * before insert.
289 *
290 * Operations which required such switch include:
291 * - insertions (itc.*, itr.*)
292 * - purges (ptc.* and ptr.*)
293 * - tpa
294 * - tak
295 * - thash?, ttag?
296 * All above needs actual virtual rid for destination entry.
297 */
299 void
300 prepare_if_physical_mode(VCPU *vcpu)
301 {
302 if (!is_virtual_mode(vcpu))
303 switch_to_virtual_rid(vcpu);
304 return;
305 }
307 /* Recover always follows prepare */
308 void
309 recover_if_physical_mode(VCPU *vcpu)
310 {
311 if (!is_virtual_mode(vcpu))
312 switch_to_physical_rid(vcpu);
313 return;
314 }