ia64/xen-unstable

view xen/common/physdev.c @ 4036:98506ea56438

bitkeeper revision 1.1236.12.18 (422ebdbe7uRYOpXY086XHnR2gRhjaQ)

Fix 'priviledge' typo.
Signed-off-by: Keir Fraser <keir.fraser@cl.cam.ac.uk>
author kaf24@firebug.cl.cam.ac.uk
date Wed Mar 09 09:11:26 2005 +0000 (2005-03-09)
parents 9d3594cbf610
children a13b9052d91d
line source
1 /****************************************************************************
2 * (c) 2004 - Rolf Neugebauer - Intel Research Cambridge
3 * (c) 2004 - Keir Fraser - University of Cambridge
4 ****************************************************************************
5 *
6 * Description: allows a domain to access devices on the PCI bus
7 *
8 * A guest OS may be given access to particular devices on the PCI bus.
9 * For each domain a list of PCI devices is maintained, describing the
10 * access mode for the domain.
11 *
12 * Guests can figure out the virtualised PCI space through normal PCI config
13 * register access. Some of the accesses, in particular write accesses, are
14 * faked. For example the sequence for detecting the IO regions, which requires
15 * writes to determine the size of the region, is faked out by a very simple
16 * state machine, preventing direct writes to the PCI config registers by a
17 * guest.
18 */
20 #include <xen/config.h>
21 #include <xen/init.h>
22 #include <xen/lib.h>
23 #include <xen/types.h>
24 #include <xen/sched.h>
25 #include <xen/pci.h>
26 #include <xen/irq.h>
27 #include <xen/event.h>
28 #include <asm/pci.h>
29 #include <public/xen.h>
30 #include <public/physdev.h>
32 /* Called by PHYSDEV_PCI_INITIALISE_DEVICE to finalise IRQ routing. */
33 extern void pcibios_enable_irq(struct pci_dev *dev);
35 #if 0
36 #define VERBOSE_INFO(_f, _a...) printk( _f , ## _a )
37 #else
38 #define VERBOSE_INFO(_f, _a...) ((void)0)
39 #endif
41 #ifdef VERBOSE
42 #define INFO(_f, _a...) printk( _f, ## _a )
43 #else
44 #define INFO(_f, _a...) ((void)0)
45 #endif
47 #define SLOPPY_CHECKING
49 #define ACC_READ 1
50 #define ACC_WRITE 2
52 /* Upper bounds for PCI-device addressing. */
53 #define PCI_BUSMAX 255
54 #define PCI_DEVMAX 31
55 #define PCI_FUNCMAX 7
56 #define PCI_REGMAX 255
58 /* Bit offsets into state. */
59 #define ST_BASE_ADDRESS 0 /* bits 0-5: are for base address access */
60 #define ST_ROM_ADDRESS 6 /* bit 6: is for rom address access */
62 typedef struct _phys_dev_st {
63 int flags; /* flags for access etc */
64 struct pci_dev *dev; /* the device */
65 struct list_head node; /* link to the list */
66 struct domain *owner; /* 'owner of this device' */
67 int state; /* state for various checks */
68 } phys_dev_t;
71 /* Find a device on a per-domain device list. */
72 static phys_dev_t *find_pdev(struct domain *p, struct pci_dev *dev)
73 {
74 phys_dev_t *t, *res = NULL;
76 list_for_each_entry ( t, &p->pcidev_list, node )
77 {
78 if ( dev == t->dev )
79 {
80 res = t;
81 break;
82 }
83 }
84 return res;
85 }
87 /* Add a device to a per-domain device-access list. */
88 static int add_dev_to_task(struct domain *p, struct pci_dev *dev,
89 int acc)
90 {
91 phys_dev_t *physdev;
93 if ( (physdev = xmalloc(phys_dev_t)) == NULL )
94 {
95 INFO("Error allocating pdev structure.\n");
96 return -ENOMEM;
97 }
99 physdev->dev = dev;
100 physdev->flags = acc;
101 physdev->state = 0;
102 list_add(&physdev->node, &p->pcidev_list);
104 if ( acc == ACC_WRITE )
105 physdev->owner = p;
107 return 0;
108 }
110 /* Remove a device from a per-domain device-access list. */
111 static void remove_dev_from_task(struct domain *p, struct pci_dev *dev)
112 {
113 phys_dev_t *physdev = find_pdev(p, dev);
115 if ( physdev == NULL )
116 BUG();
118 list_del(&physdev->node);
120 xfree(physdev);
121 }
123 static int setup_ioport_memory_access(domid_t dom, struct domain* p,
124 struct exec_domain* ed,
125 struct pci_dev *pdev)
126 {
127 struct exec_domain* edc;
128 int i, j;
130 /* Now, setup access to the IO ports and memory regions for the device. */
131 if ( ed->arch.io_bitmap == NULL )
132 {
133 if ( (ed->arch.io_bitmap = xmalloc_array(u8, IOBMP_BYTES)) == NULL )
134 return -ENOMEM;
136 memset(ed->arch.io_bitmap, 0xFF, IOBMP_BYTES);
138 ed->arch.io_bitmap_sel = ~0ULL;
140 for_each_exec_domain(p, edc) {
141 if (edc == ed)
142 continue;
143 edc->arch.io_bitmap = ed->arch.io_bitmap;
144 }
145 }
147 for ( i = 0; i < DEVICE_COUNT_RESOURCE; i++ )
148 {
149 struct resource *r = &pdev->resource[i];
151 if ( r->flags & IORESOURCE_IO )
152 {
153 /* Give the domain access to the IO ports it needs. Currently,
154 * this will allow all processes in that domain access to those
155 * ports as well. This will do for now, since driver domains don't
156 * run untrusted processes! */
157 INFO("Giving domain %u IO resources (%lx - %lx) "
158 "for device %s\n", dom, r->start, r->end, pdev->slot_name);
159 for ( j = r->start; j < r->end + 1; j++ )
160 {
161 clear_bit(j, ed->arch.io_bitmap);
162 clear_bit(j / IOBMP_BITS_PER_SELBIT, &ed->arch.io_bitmap_sel);
163 }
164 }
165 /* rights to IO memory regions are checked when the domain maps them */
166 }
168 for_each_exec_domain(p, edc) {
169 if (edc == ed)
170 continue;
171 edc->arch.io_bitmap_sel = ed->arch.io_bitmap_sel;
172 }
174 return 0;
175 }
177 /*
178 * physdev_pci_access_modify:
179 * Allow/disallow access to a specific PCI device. Guests should not be
180 * allowed to see bridge devices as it needlessly complicates things (one
181 * possible exception to this is the AGP bridge). If the given device is a
182 * bridge, then the domain should get access to all the leaf devices below
183 * that bridge (XXX this is unimplemented!).
184 */
185 int physdev_pci_access_modify(domid_t dom, int bus, int dev, int func,
186 int enable)
187 {
188 struct domain *p;
189 struct exec_domain *ed;
190 struct pci_dev *pdev;
191 phys_dev_t *physdev;
192 int rc = 0;
193 int oldacc = -1, allocated_physdev = 0;
195 if ( !IS_PRIV(current->domain) )
196 BUG();
198 if ( (bus > PCI_BUSMAX) || (dev > PCI_DEVMAX) || (func > PCI_FUNCMAX) )
199 return -EINVAL;
201 if ( !enable )
202 {
203 INFO("Disallowing access is not yet supported.\n");
204 return -EINVAL;
205 }
207 INFO("physdev_pci_access_modify: %02x:%02x:%02x\n", bus, dev, func);
209 if ( (p = find_domain_by_id(dom)) == NULL )
210 return -ESRCH;
212 ed = p->exec_domain[0]; /* XXX */
214 /* Make the domain privileged. */
215 set_bit(DF_PHYSDEV, &p->d_flags);
216 /* FIXME: MAW for now make the domain REALLY privileged so that it
217 * can run a backend driver (hw access should work OK otherwise) */
218 set_bit(DF_PRIVILEGED, &p->d_flags);
220 /* Grant write access to the specified device. */
221 if ( (pdev = pci_find_slot(bus, PCI_DEVFN(dev, func))) == NULL )
222 {
223 INFO(" dev does not exist\n");
224 rc = -ENODEV;
225 goto clear_privilege;
226 }
228 if ( (physdev = find_pdev(p, pdev)) != NULL) {
229 /* Sevice already on list: update access permissions. */
230 oldacc = physdev->flags;
231 physdev->flags = ACC_WRITE;
232 } else {
233 if ( (rc = add_dev_to_task(p, pdev, ACC_WRITE)) < 0)
234 goto clear_privilege;
235 allocated_physdev = 1;
236 }
238 INFO(" add RW %02x:%02x:%02x\n", pdev->bus->number,
239 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
241 /* Is the device a bridge or cardbus? */
242 if ( pdev->hdr_type != PCI_HEADER_TYPE_NORMAL ) {
243 INFO("XXX can't give access to bridge devices yet\n");
244 rc = -EPERM;
245 goto remove_dev;
246 }
248 if ( (rc = setup_ioport_memory_access(dom, p, ed, pdev)) < 0 )
249 goto remove_dev;
251 put_domain(p);
252 return rc;
254 remove_dev:
255 if (allocated_physdev) {
256 /* new device was added - remove it from the list */
257 remove_dev_from_task(p, pdev);
258 } else {
259 /* device already existed - just undo the access changes */
260 physdev->flags = oldacc;
261 }
263 clear_privilege:
264 clear_bit(DF_PHYSDEV, &p->d_flags);
265 clear_bit(DF_PRIVILEGED, &p->d_flags);
266 put_domain(p);
267 return rc;
268 }
270 /* Check if a domain controls a device with IO memory within frame @pfn.
271 * Returns: 1 if the domain should be allowed to map @pfn, 0 otherwise. */
272 int domain_iomem_in_pfn(struct domain *p, unsigned long pfn)
273 {
274 int ret = 0;
275 phys_dev_t *phys_dev;
277 VERBOSE_INFO("Checking if physdev-capable domain %u needs access to "
278 "pfn %p\n", p->id, pfn);
280 spin_lock(&p->pcidev_lock);
282 list_for_each_entry ( phys_dev, &p->pcidev_list, node )
283 {
284 int i;
285 struct pci_dev *pci_dev = phys_dev->dev;
287 for ( i = 0; (i < DEVICE_COUNT_RESOURCE) && (ret == 0); i++ )
288 {
289 struct resource *r = &pci_dev->resource[i];
291 if ( r->flags & IORESOURCE_MEM )
292 if ( (r->start >> PAGE_SHIFT) == pfn
293 || (r->end >> PAGE_SHIFT) == pfn
294 || ((r->start >> PAGE_SHIFT < pfn)
295 && (r->end >> PAGE_SHIFT > pfn)) )
296 ret = 1;
297 }
299 if ( ret != 0 ) break;
300 }
302 spin_unlock(&p->pcidev_lock);
304 VERBOSE_INFO("Domain %u %s mapping of pfn %p\n",
305 p->id, ret ? "allowed" : "disallowed", pfn);
307 return ret;
308 }
310 /* check if a domain has general access to a device */
311 inline static int check_dev_acc (struct domain *p,
312 int bus, int dev, int func,
313 phys_dev_t **pdev)
314 {
315 struct pci_dev *target_dev;
316 phys_dev_t *target_pdev;
317 unsigned int target_devfn;
319 *pdev = NULL;
321 if ( !IS_CAPABLE_PHYSDEV(p) )
322 return -EPERM; /* no pci access permission */
324 if ( bus > PCI_BUSMAX || dev > PCI_DEVMAX || func > PCI_FUNCMAX )
325 return -EINVAL;
327 VERBOSE_INFO("b=%x d=%x f=%x ", bus, dev, func);
329 /* check target device */
330 target_devfn = PCI_DEVFN(dev, func);
331 target_dev = pci_find_slot(bus, target_devfn);
332 if ( !target_dev )
333 {
334 VERBOSE_INFO("target does not exist\n");
335 return -ENODEV;
336 }
338 /* check access */
339 target_pdev = find_pdev(p, target_dev);
340 if ( !target_pdev )
341 {
342 VERBOSE_INFO("dom has no access to target\n");
343 return -EPERM;
344 }
346 *pdev = target_pdev;
347 return 0;
348 }
350 #ifndef SLOPPY_CHECKING
351 /*
352 * Base address registers contain the base address for IO regions.
353 * The length can be determined by writing all 1s to the register and
354 * reading the value again. The device will zero the lower unused bits.
355 *
356 * to work out the length of the io region a device probe typically does:
357 * 1) a = read_base_addr_reg()
358 * 2) write_base_addr_reg(0xffffffff)
359 * 3) b = read_base_addr_reg() [device zeros lower bits]
360 * 4) write_base_addr_reg(a) [restore original value]
361 * this function fakes out step 2-4. *no* writes are made to the device.
362 *
363 * phys_dev_t contains a bit field (a bit for each base address register).
364 * if the bit for a register is set the guest had writen all 1s to the
365 * register and subsequent read request need to fake out the b.
366 * if the guest restores the original value (step 4 above) the bit is
367 * cleared again. If the guest attempts to "restores" a wrong value an
368 * error is flagged.
369 */
370 static int do_base_address_access(phys_dev_t *pdev, int acc, int idx,
371 int len, u32 *val)
372 {
373 int st_bit, reg = PCI_BASE_ADDRESS_0 + (idx*4), ret = -EINVAL;
374 struct pci_dev *dev = pdev->dev;
375 u32 orig_val, sz;
376 struct resource *res;
378 if ( len != sizeof(u32) )
379 {
380 /* This isn't illegal, but there doesn't seem to be a very good reason
381 * to do it for normal devices (bridges are another matter). Since it
382 * would complicate the code below, we don't support this for now. */
384 /* We could set *val to some value but the guest may well be in trouble
385 * anyway if this write fails. Hopefully the printk will give us a
386 * clue what went wrong. */
387 INFO("Guest %u attempting sub-dword %s to BASE_ADDRESS %d\n",
388 pdev->owner->id, (acc == ACC_READ) ? "read" : "write", idx);
390 return -EPERM;
391 }
393 st_bit = idx + ST_BASE_ADDRESS;
394 res = &(pdev->dev->resource[idx]);
396 if ( acc == ACC_WRITE )
397 {
398 if ( (*val == 0xffffffff) ||
399 ((res->flags & IORESOURCE_IO) && (*val == 0xffff)) )
400 {
401 /* Set bit and return. */
402 set_bit(st_bit, &pdev->state);
403 ret = 0;
404 }
405 else
406 {
407 /* Assume guest wants to set the base address. */
408 clear_bit(st_bit, &pdev->state);
410 /* check if guest tries to restore orig value */
411 ret = pci_read_config_dword(dev, reg, &orig_val);
412 if ( (ret == 0) && (*val != orig_val) )
413 {
414 INFO("Guest attempting update to BASE_ADDRESS %d\n", idx);
415 ret = -EPERM;
416 }
417 }
418 VERBOSE_INFO("fixed pci write: %02x:%02x:%02x reg=0x%02x len=0x%02x"
419 " val=0x%08x %x\n",
420 dev->bus->number, PCI_SLOT(dev->devfn),
421 PCI_FUNC(dev->devfn), reg, len, *val, pdev->state);
422 }
423 else if ( acc == ACC_READ )
424 {
425 ret = pci_read_config_dword(dev, reg, val);
426 if ( (ret == 0) && test_bit(st_bit, &pdev->state) )
427 {
428 /* Cook the value. */
429 sz = res->end - res->start;
430 if ( res->flags & IORESOURCE_MEM )
431 {
432 /* this is written out explicitly for clarity */
433 *val = 0xffffffff;
434 /* bit 0 = 0 */
435 /* bit 21 = memory type */
436 /* bit 3 = prefetchable */
437 /* bit 4-31 width */
438 sz = sz >> 4; /* size in blocks of 16 byte */
439 sz = ~sz; /* invert */
440 *val = *val & (sz << 4); /* and in the size */
441 /* use read values for low 4 bits */
442 *val = *val | (orig_val & 0xf);
443 }
444 else if ( res->flags & IORESOURCE_IO )
445 {
446 *val = 0x0000ffff;
447 /* bit 10 = 01 */
448 /* bit 2-31 width */
449 sz = sz >> 2; /* size in dwords */
450 sz = ~sz & 0x0000ffff;
451 *val = *val & (sz << 2);
452 *val = *val | 0x1;
453 }
454 }
455 VERBOSE_INFO("fixed pci read: %02x:%02x:%02x reg=0x%02x len=0x%02x"
456 " val=0x%08x %x\n",
457 dev->bus->number, PCI_SLOT(dev->devfn),
458 PCI_FUNC(dev->devfn), reg, len, *val, pdev->state);
459 }
461 return ret;
462 }
465 static int do_rom_address_access(phys_dev_t *pdev, int acc, int len, u32 *val)
466 {
467 int st_bit, ret = -EINVAL;
468 struct pci_dev *dev = pdev->dev;
469 u32 orig_val, sz;
470 struct resource *res;
472 if ( len != sizeof(u32) )
473 {
474 INFO("Guest attempting sub-dword %s to ROM_ADDRESS\n",
475 (acc == ACC_READ) ? "read" : "write");
476 return -EPERM;
477 }
479 st_bit = ST_ROM_ADDRESS;
480 res = &(pdev->dev->resource[PCI_ROM_RESOURCE]);
482 if ( acc == ACC_WRITE )
483 {
484 if ( (*val == 0xffffffff) || (*val == 0xfffffffe) )
485 {
486 /* NB. 0xffffffff would be unusual, but we trap it anyway. */
487 set_bit(st_bit, &pdev->state);
488 ret = 0;
489 }
490 else
491 {
492 /* Assume guest wants simply to set the base address. */
493 clear_bit(st_bit, &pdev->state);
495 /* Check if guest tries to restore the original value. */
496 ret = pci_read_config_dword(dev, PCI_ROM_ADDRESS, &orig_val);
497 if ( (ret == 0) && (*val != orig_val) )
498 {
499 if ( (*val != 0x00000000) )
500 {
501 INFO("caution: guest tried to change rom address.\n");
502 ret = -EPERM;
503 }
504 else
505 {
506 INFO("guest disabled rom access for %02x:%02x:%02x\n",
507 dev->bus->number, PCI_SLOT(dev->devfn),
508 PCI_FUNC(dev->devfn));
509 }
510 }
511 }
512 VERBOSE_INFO("fixed pci write: %02x:%02x:%02x reg=0x%02x len=0x%02x"
513 " val=0x%08x %x\n",
514 dev->bus->number, PCI_SLOT(dev->devfn),
515 PCI_FUNC(dev->devfn), PCI_ROM_ADDRESS, len, *val, pdev->state);
516 }
517 else if ( acc == ACC_READ )
518 {
519 ret = pci_read_config_dword(dev, PCI_ROM_ADDRESS, val);
520 if ( (ret == 0) && test_bit(st_bit, &pdev->state) )
521 {
522 /* Cook the value. */
523 sz = res->end - res->start;
524 *val = 0xffffffff;
525 /* leave bit 0 untouched */
526 /* bit 1-10 reserved, harwired to 0 */
527 sz = sz >> 11; /* size is in 2KB blocks */
528 sz = ~sz;
529 *val = *val & (sz << 11);
530 *val = *val | (orig_val & 0x1);
531 }
532 VERBOSE_INFO("fixed pci read: %02x:%02x:%02x reg=0x%02x len=0x%02x"
533 " val=0x%08x %x\n",
534 dev->bus->number, PCI_SLOT(dev->devfn),
535 PCI_FUNC(dev->devfn), PCI_ROM_ADDRESS, len, *val, pdev->state);
536 }
538 return ret;
540 }
541 #endif /* SLOPPY_CHECKING */
543 /*
544 * Handle a PCI config space read access if the domain has access privileges.
545 */
546 static long pci_cfgreg_read(int bus, int dev, int func, int reg,
547 int len, u32 *val)
548 {
549 int ret;
550 phys_dev_t *pdev;
552 if ( (ret = check_dev_acc(current->domain, bus, dev, func, &pdev)) != 0 )
553 {
554 /* PCI spec states that reads from non-existent devices should return
555 * all 1s. In this case the domain has no read access, which should
556 * also look like the device is non-existent. */
557 *val = 0xFFFFFFFF;
558 return ret;
559 }
561 /* Fake out read requests for some registers. */
562 switch ( reg )
563 {
564 #ifndef SLOPPY_CHECKING
565 case PCI_BASE_ADDRESS_0:
566 ret = do_base_address_access(pdev, ACC_READ, 0, len, val);
567 break;
569 case PCI_BASE_ADDRESS_1:
570 ret = do_base_address_access(pdev, ACC_READ, 1, len, val);
571 break;
573 case PCI_BASE_ADDRESS_2:
574 ret = do_base_address_access(pdev, ACC_READ, 2, len, val);
575 break;
577 case PCI_BASE_ADDRESS_3:
578 ret = do_base_address_access(pdev, ACC_READ, 3, len, val);
579 break;
581 case PCI_BASE_ADDRESS_4:
582 ret = do_base_address_access(pdev, ACC_READ, 4, len, val);
583 break;
585 case PCI_BASE_ADDRESS_5:
586 ret = do_base_address_access(pdev, ACC_READ, 5, len, val);
587 break;
589 case PCI_ROM_ADDRESS:
590 ret = do_rom_address_access(pdev, ACC_READ, len, val);
591 break;
592 #endif
594 case PCI_INTERRUPT_LINE:
595 *val = pdev->dev->irq;
596 ret = 0;
597 break;
599 default:
600 ret = pci_config_read(0, bus, dev, func, reg, len, val);
601 VERBOSE_INFO("pci read : %02x:%02x:%02x reg=0x%02x len=0x%02x "
602 "val=0x%08x\n", bus, dev, func, reg, len, *val);
603 break;
604 }
606 return ret;
607 }
610 /*
611 * Handle a PCI config space write access if the domain has access privileges.
612 */
613 static long pci_cfgreg_write(int bus, int dev, int func, int reg,
614 int len, u32 val)
615 {
616 int ret;
617 phys_dev_t *pdev;
619 if ( (ret = check_dev_acc(current->domain, bus, dev, func, &pdev)) != 0 )
620 return ret;
622 /* special treatment for some registers */
623 switch (reg)
624 {
625 #ifndef SLOPPY_CHECKING
626 case PCI_BASE_ADDRESS_0:
627 ret = do_base_address_access(pdev, ACC_WRITE, 0, len, &val);
628 break;
630 case PCI_BASE_ADDRESS_1:
631 ret = do_base_address_access(pdev, ACC_WRITE, 1, len, &val);
632 break;
634 case PCI_BASE_ADDRESS_2:
635 ret = do_base_address_access(pdev, ACC_WRITE, 2, len, &val);
636 break;
638 case PCI_BASE_ADDRESS_3:
639 ret = do_base_address_access(pdev, ACC_WRITE, 3, len, &val);
640 break;
642 case PCI_BASE_ADDRESS_4:
643 ret = do_base_address_access(pdev, ACC_WRITE, 4, len, &val);
644 break;
646 case PCI_BASE_ADDRESS_5:
647 ret = do_base_address_access(pdev, ACC_WRITE, 5, len, &val);
648 break;
650 case PCI_ROM_ADDRESS:
651 ret = do_rom_address_access(pdev, ACC_WRITE, len, &val);
652 break;
653 #endif
655 default:
656 if ( pdev->flags != ACC_WRITE )
657 {
658 INFO("pci write not allowed %02x:%02x:%02x: "
659 "reg=0x%02x len=0x%02x val=0x%08x\n",
660 bus, dev, func, reg, len, val);
661 ret = -EPERM;
662 }
663 else
664 {
665 ret = pci_config_write(0, bus, dev, func, reg, len, val);
666 VERBOSE_INFO("pci write: %02x:%02x:%02x reg=0x%02x len=0x%02x "
667 "val=0x%08x\n", bus, dev, func, reg, len, val);
668 }
669 break;
670 }
672 return ret;
673 }
676 static long pci_probe_root_buses(u32 *busmask)
677 {
678 phys_dev_t *pdev;
680 memset(busmask, 0, 256/8);
682 list_for_each_entry ( pdev, &current->domain->pcidev_list, node )
683 set_bit(pdev->dev->bus->number, busmask);
685 return 0;
686 }
689 /*
690 * Demuxing hypercall.
691 */
692 long do_physdev_op(physdev_op_t *uop)
693 {
694 phys_dev_t *pdev;
695 physdev_op_t op;
696 long ret;
697 int irq;
699 if ( unlikely(copy_from_user(&op, uop, sizeof(op)) != 0) )
700 return -EFAULT;
702 switch ( op.cmd )
703 {
704 case PHYSDEVOP_PCI_CFGREG_READ:
705 ret = pci_cfgreg_read(op.u.pci_cfgreg_read.bus,
706 op.u.pci_cfgreg_read.dev,
707 op.u.pci_cfgreg_read.func,
708 op.u.pci_cfgreg_read.reg,
709 op.u.pci_cfgreg_read.len,
710 &op.u.pci_cfgreg_read.value);
711 break;
713 case PHYSDEVOP_PCI_CFGREG_WRITE:
714 ret = pci_cfgreg_write(op.u.pci_cfgreg_write.bus,
715 op.u.pci_cfgreg_write.dev,
716 op.u.pci_cfgreg_write.func,
717 op.u.pci_cfgreg_write.reg,
718 op.u.pci_cfgreg_write.len,
719 op.u.pci_cfgreg_write.value);
720 break;
722 case PHYSDEVOP_PCI_INITIALISE_DEVICE:
723 if ( (ret = check_dev_acc(current->domain,
724 op.u.pci_initialise_device.bus,
725 op.u.pci_initialise_device.dev,
726 op.u.pci_initialise_device.func,
727 &pdev)) == 0 )
728 pcibios_enable_irq(pdev->dev);
729 break;
731 case PHYSDEVOP_PCI_PROBE_ROOT_BUSES:
732 ret = pci_probe_root_buses(op.u.pci_probe_root_buses.busmask);
733 break;
735 case PHYSDEVOP_IRQ_UNMASK_NOTIFY:
736 ret = pirq_guest_unmask(current->domain);
737 break;
739 case PHYSDEVOP_IRQ_STATUS_QUERY:
740 irq = op.u.irq_status_query.irq;
741 ret = -EINVAL;
742 if ( (irq < 0) || (irq >= NR_IRQS) )
743 break;
744 op.u.irq_status_query.flags = 0;
745 /* Edge-triggered interrupts don't need an explicit unmask downcall. */
746 if ( strstr(irq_desc[irq].handler->typename, "edge") == NULL )
747 op.u.irq_status_query.flags |= PHYSDEVOP_IRQ_NEEDS_UNMASK_NOTIFY;
748 ret = 0;
749 break;
751 default:
752 ret = -EINVAL;
753 break;
754 }
756 if (copy_to_user(uop, &op, sizeof(op)))
757 ret = -EFAULT;
759 return ret;
760 }
762 /* opt_physdev_dom0_hide: list of PCI slots to hide from domain 0. */
763 /* Format is '(%02x:%02x.%1x)(%02x:%02x.%1x)' and so on. */
764 static char opt_physdev_dom0_hide[200] = "";
765 string_param("physdev_dom0_hide", opt_physdev_dom0_hide);
767 /* Test if boot params specify this device should NOT be visible to DOM0
768 * (e.g. so that another domain can control it instead) */
769 static int pcidev_dom0_hidden(struct pci_dev *dev)
770 {
771 char cmp[10] = "(.......)";
773 strncpy(&cmp[1], dev->slot_name, 7);
775 if ( strstr(opt_physdev_dom0_hide, dev->slot_name) == NULL )
776 return 0;
778 return 1;
779 }
782 /* Domain 0 has read access to all devices. */
783 void physdev_init_dom0(struct domain *p)
784 {
785 struct pci_dev *dev;
786 phys_dev_t *pdev;
788 INFO("Give DOM0 read access to all PCI devices\n");
790 pci_for_each_dev(dev)
791 {
792 if ( pcidev_dom0_hidden(dev) )
793 {
794 printk("Hiding PCI device %s from DOM0\n", dev->slot_name);
795 continue;
796 }
798 /* Skip bridges and other peculiarities for now.
799 *
800 * Note that this can prevent the guest from detecting devices
801 * with fn>0 on slots where the fn=0 device is a bridge. We
802 * can identify such slots by looking at the multifunction bit
803 * (top bit of hdr_type, masked out in dev->hdr_type).
804 *
805 * In Linux2.4 we find all devices because the detection code
806 * scans all functions if the read of the fn=0 device's header
807 * type fails.
808 *
809 * In Linux2.6 we set pcibios_scan_all_fns().
810 */
811 if ( (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) &&
812 (dev->hdr_type != PCI_HEADER_TYPE_CARDBUS) )
813 continue;
815 if ( (pdev = xmalloc(phys_dev_t)) == NULL ) {
816 INFO("failed to allocate physical device structure!\n");
817 break;
818 }
820 pdev->dev = dev;
821 pdev->flags = ACC_WRITE;
822 pdev->state = 0;
823 pdev->owner = p;
824 list_add(&pdev->node, &p->pcidev_list);
825 }
827 set_bit(DF_PHYSDEV, &p->d_flags);
828 }
831 /*
832 * Local variables:
833 * mode: C
834 * c-set-style: "BSD"
835 * c-basic-offset: 4
836 * tab-width: 4
837 * indent-tabs-mode: nil
838 * End:
839 */