ia64/xen-unstable

view xen/drivers/char/ns16550.c @ 18487:982e6fce0e47

Check the existence of serial port before using

Signed-off-by: Huacai Chen <huacai.chen@intel.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Sep 12 11:43:47 2008 +0100 (2008-09-12)
parents 537b8edb1efa
children 50aaffd8f87c
line source
1 /******************************************************************************
2 * ns16550.c
3 *
4 * Driver for 16550-series UARTs. This driver is to be kept within Xen as
5 * it permits debugging of seriously-toasted machines (e.g., in situations
6 * where a device driver within a guest OS would be inaccessible).
7 *
8 * Copyright (c) 2003-2005, K A Fraser
9 */
11 #include <xen/config.h>
12 #include <xen/console.h>
13 #include <xen/init.h>
14 #include <xen/irq.h>
15 #include <xen/sched.h>
16 #include <xen/serial.h>
17 #include <xen/iocap.h>
18 #include <asm/io.h>
20 /*
21 * Configure serial port with a string <baud>,DPS,<io-base>,<irq>.
22 * The tail of the string can be omitted if platform defaults are sufficient.
23 * If the baud rate is pre-configured, perhaps by a bootloader, then 'auto'
24 * can be specified in place of a numeric baud rate.
25 */
26 static char opt_com1[30] = "", opt_com2[30] = "";
27 string_param("com1", opt_com1);
28 string_param("com2", opt_com2);
30 static struct ns16550 {
31 int baud, data_bits, parity, stop_bits, irq;
32 unsigned long io_base; /* I/O port or memory-mapped I/O address. */
33 char *remapped_io_base; /* Remapped virtual address of mmap I/O. */
34 /* UART with IRQ line: interrupt-driven I/O. */
35 struct irqaction irqaction;
36 /* UART with no IRQ line: periodically-polled I/O. */
37 struct timer timer;
38 unsigned int timeout_ms;
39 } ns16550_com[2] = { { 0 } };
41 /* Register offsets */
42 #define RBR 0x00 /* receive buffer */
43 #define THR 0x00 /* transmit holding */
44 #define IER 0x01 /* interrupt enable */
45 #define IIR 0x02 /* interrupt identity */
46 #define FCR 0x02 /* FIFO control */
47 #define LCR 0x03 /* line control */
48 #define MCR 0x04 /* Modem control */
49 #define LSR 0x05 /* line status */
50 #define MSR 0x06 /* Modem status */
51 #define DLL 0x00 /* divisor latch (ls) (DLAB=1) */
52 #define DLM 0x01 /* divisor latch (ms) (DLAB=1) */
54 /* Interrupt Enable Register */
55 #define IER_ERDAI 0x01 /* rx data recv'd */
56 #define IER_ETHREI 0x02 /* tx reg. empty */
57 #define IER_ELSI 0x04 /* rx line status */
58 #define IER_EMSI 0x08 /* MODEM status */
60 /* Interrupt Identification Register */
61 #define IIR_NOINT 0x01 /* no interrupt pending */
62 #define IIR_IMASK 0x06 /* interrupt identity: */
63 #define IIR_LSI 0x06 /* - rx line status */
64 #define IIR_RDAI 0x04 /* - rx data recv'd */
65 #define IIR_THREI 0x02 /* - tx reg. empty */
66 #define IIR_MSI 0x00 /* - MODEM status */
68 /* FIFO Control Register */
69 #define FCR_ENABLE 0x01 /* enable FIFO */
70 #define FCR_CLRX 0x02 /* clear Rx FIFO */
71 #define FCR_CLTX 0x04 /* clear Tx FIFO */
72 #define FCR_DMA 0x10 /* enter DMA mode */
73 #define FCR_TRG1 0x00 /* Rx FIFO trig lev 1 */
74 #define FCR_TRG4 0x40 /* Rx FIFO trig lev 4 */
75 #define FCR_TRG8 0x80 /* Rx FIFO trig lev 8 */
76 #define FCR_TRG14 0xc0 /* Rx FIFO trig lev 14 */
78 /* Line Control Register */
79 #define LCR_DLAB 0x80 /* Divisor Latch Access */
81 /* Modem Control Register */
82 #define MCR_DTR 0x01 /* Data Terminal Ready */
83 #define MCR_RTS 0x02 /* Request to Send */
84 #define MCR_OUT2 0x08 /* OUT2: interrupt mask */
85 #define MCR_LOOP 0x10 /* Enable loopback test mode */
87 /* Line Status Register */
88 #define LSR_DR 0x01 /* Data ready */
89 #define LSR_OE 0x02 /* Overrun */
90 #define LSR_PE 0x04 /* Parity error */
91 #define LSR_FE 0x08 /* Framing error */
92 #define LSR_BI 0x10 /* Break */
93 #define LSR_THRE 0x20 /* Xmit hold reg empty */
94 #define LSR_TEMT 0x40 /* Xmitter empty */
95 #define LSR_ERR 0x80 /* Error */
97 /* These parity settings can be ORed directly into the LCR. */
98 #define PARITY_NONE (0<<3)
99 #define PARITY_ODD (1<<3)
100 #define PARITY_EVEN (3<<3)
101 #define PARITY_MARK (5<<3)
102 #define PARITY_SPACE (7<<3)
104 /* Frequency of external clock source. This definition assumes PC platform. */
105 #define UART_CLOCK_HZ 1843200
107 static char ns_read_reg(struct ns16550 *uart, int reg)
108 {
109 if ( uart->remapped_io_base == NULL )
110 return inb(uart->io_base + reg);
111 return readb(uart->remapped_io_base + reg);
112 }
114 static void ns_write_reg(struct ns16550 *uart, int reg, char c)
115 {
116 if ( uart->remapped_io_base == NULL )
117 return outb(c, uart->io_base + reg);
118 writeb(c, uart->remapped_io_base + reg);
119 }
121 static void ns16550_interrupt(
122 int irq, void *dev_id, struct cpu_user_regs *regs)
123 {
124 struct serial_port *port = dev_id;
125 struct ns16550 *uart = port->uart;
127 while ( !(ns_read_reg(uart, IIR) & IIR_NOINT) )
128 {
129 char lsr = ns_read_reg(uart, LSR);
130 if ( lsr & LSR_THRE )
131 serial_tx_interrupt(port, regs);
132 if ( lsr & LSR_DR )
133 serial_rx_interrupt(port, regs);
134 }
135 }
137 static void ns16550_poll(void *data)
138 {
139 struct serial_port *port = data;
140 struct ns16550 *uart = port->uart;
141 struct cpu_user_regs *regs = guest_cpu_user_regs();
143 while ( ns_read_reg(uart, LSR) & LSR_DR )
144 serial_rx_interrupt(port, regs);
146 if ( ns_read_reg(uart, LSR) & LSR_THRE )
147 serial_tx_interrupt(port, regs);
149 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
150 }
152 static int ns16550_tx_empty(struct serial_port *port)
153 {
154 struct ns16550 *uart = port->uart;
155 return !!(ns_read_reg(uart, LSR) & LSR_THRE);
156 }
158 static void ns16550_putc(struct serial_port *port, char c)
159 {
160 struct ns16550 *uart = port->uart;
161 ns_write_reg(uart, THR, c);
162 }
164 static int ns16550_getc(struct serial_port *port, char *pc)
165 {
166 struct ns16550 *uart = port->uart;
168 if ( !(ns_read_reg(uart, LSR) & LSR_DR) )
169 return 0;
171 *pc = ns_read_reg(uart, RBR);
172 return 1;
173 }
175 static void __devinit ns16550_init_preirq(struct serial_port *port)
176 {
177 struct ns16550 *uart = port->uart;
178 unsigned char lcr;
179 unsigned int divisor;
181 /* I/O ports are distinguished by their size (16 bits). */
182 if ( uart->io_base >= 0x10000 )
183 uart->remapped_io_base = (char *)ioremap(uart->io_base, 8);
185 lcr = (uart->data_bits - 5) | ((uart->stop_bits - 1) << 2) | uart->parity;
187 /* No interrupts. */
188 ns_write_reg(uart, IER, 0);
190 /* Line control and baud-rate generator. */
191 ns_write_reg(uart, LCR, lcr | LCR_DLAB);
192 if ( uart->baud != BAUD_AUTO )
193 {
194 /* Baud rate specified: program it into the divisor latch. */
195 divisor = UART_CLOCK_HZ / (uart->baud * 16);
196 ns_write_reg(uart, DLL, (char)divisor);
197 ns_write_reg(uart, DLM, (char)(divisor >> 8));
198 }
199 else
200 {
201 /* Baud rate already set: read it out from the divisor latch. */
202 divisor = ns_read_reg(uart, DLL);
203 divisor |= ns_read_reg(uart, DLM) << 8;
204 uart->baud = UART_CLOCK_HZ / (divisor * 16);
205 }
206 ns_write_reg(uart, LCR, lcr);
208 /* No flow ctrl: DTR and RTS are both wedged high to keep remote happy. */
209 ns_write_reg(uart, MCR, MCR_DTR | MCR_RTS);
211 /* Enable and clear the FIFOs. Set a large trigger threshold. */
212 ns_write_reg(uart, FCR, FCR_ENABLE | FCR_CLRX | FCR_CLTX | FCR_TRG14);
214 /* Check this really is a 16550+. Otherwise we have no FIFOs. */
215 if ( (ns_read_reg(uart, IIR) & 0xc0) == 0xc0 )
216 port->tx_fifo_size = 16;
217 }
219 static void __devinit ns16550_init_postirq(struct serial_port *port)
220 {
221 struct ns16550 *uart = port->uart;
222 int rc, bits;
224 if ( uart->irq < 0 )
225 return;
227 serial_async_transmit(port);
229 if ( uart->irq == 0 )
230 {
231 /* Polled mode. Calculate time to fill RX FIFO and/or empty TX FIFO. */
232 bits = uart->data_bits + uart->stop_bits + !!uart->parity;
233 uart->timeout_ms = max_t(
234 unsigned int, 1, (bits * port->tx_fifo_size * 1000) / uart->baud);
235 init_timer(&uart->timer, ns16550_poll, port, 0);
236 set_timer(&uart->timer, NOW() + MILLISECS(uart->timeout_ms));
237 }
238 else
239 {
240 uart->irqaction.handler = ns16550_interrupt;
241 uart->irqaction.name = "ns16550";
242 uart->irqaction.dev_id = port;
243 if ( (rc = setup_irq(uart->irq, &uart->irqaction)) != 0 )
244 printk("ERROR: Failed to allocate ns16550 IRQ %d\n", uart->irq);
246 /* Master interrupt enable; also keep DTR/RTS asserted. */
247 ns_write_reg(uart, MCR, MCR_OUT2 | MCR_DTR | MCR_RTS);
249 /* Enable receive and transmit interrupts. */
250 ns_write_reg(uart, IER, IER_ERDAI | IER_ETHREI);
251 }
252 }
254 #ifdef CONFIG_X86
255 static void __init ns16550_endboot(struct serial_port *port)
256 {
257 struct ns16550 *uart = port->uart;
258 if ( ioports_deny_access(dom0, uart->io_base, uart->io_base + 7) != 0 )
259 BUG();
260 }
261 #else
262 #define ns16550_endboot NULL
263 #endif
265 static int ns16550_irq(struct serial_port *port)
266 {
267 struct ns16550 *uart = port->uart;
268 return ((uart->irq > 0) ? uart->irq : -1);
269 }
271 static struct uart_driver ns16550_driver = {
272 .init_preirq = ns16550_init_preirq,
273 .init_postirq = ns16550_init_postirq,
274 .endboot = ns16550_endboot,
275 .tx_empty = ns16550_tx_empty,
276 .putc = ns16550_putc,
277 .getc = ns16550_getc,
278 .irq = ns16550_irq
279 };
281 static int __init parse_parity_char(int c)
282 {
283 switch ( c )
284 {
285 case 'n':
286 return PARITY_NONE;
287 case 'o':
288 return PARITY_ODD;
289 case 'e':
290 return PARITY_EVEN;
291 case 'm':
292 return PARITY_MARK;
293 case 's':
294 return PARITY_SPACE;
295 }
296 return 0;
297 }
299 static int check_existence(struct ns16550 *uart)
300 {
301 unsigned char status, scratch, scratch2, scratch3;
303 /*
304 * Do a simple existence test first; if we fail this,
305 * there's no point trying anything else.
306 */
307 scratch = ns_read_reg(uart, IER);
308 ns_write_reg(uart, IER, 0);
310 /*
311 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
312 * 16C754B) allow only to modify them if an EFR bit is set.
313 */
314 scratch2 = ns_read_reg(uart, IER) & 0x0f;
315 ns_write_reg(uart, IER, 0x0F);
316 scratch3 = ns_read_reg(uart, IER) & 0x0f;
317 ns_write_reg(uart, IER, scratch);
318 if ( (scratch2 != 0) || (scratch3 != 0x0F) )
319 return 0;
321 /*
322 * Check to see if a UART is really there.
323 * Use loopback test mode.
324 */
325 ns_write_reg(uart, MCR, MCR_LOOP | 0x0A);
326 status = ns_read_reg(uart, MSR) & 0xF0;
327 return (status == 0x90);
328 }
330 #define PARSE_ERR(_f, _a...) \
331 do { \
332 printk( "ERROR: " _f "\n" , ## _a ); \
333 return; \
334 } while ( 0 )
336 static void __init ns16550_parse_port_config(
337 struct ns16550 *uart, const char *conf)
338 {
339 int baud;
341 /* No user-specified configuration? */
342 if ( (conf == NULL) || (*conf == '\0') )
343 {
344 /* Some platforms may automatically probe the UART configuartion. */
345 if ( uart->baud != 0 )
346 goto config_parsed;
347 return;
348 }
350 if ( strncmp(conf, "auto", 4) == 0 )
351 {
352 uart->baud = BAUD_AUTO;
353 conf += 4;
354 }
355 else if ( (baud = simple_strtoul(conf, &conf, 10)) != 0 )
356 uart->baud = baud;
358 if ( *conf != ',' )
359 goto config_parsed;
360 conf++;
362 uart->data_bits = simple_strtoul(conf, &conf, 10);
364 uart->parity = parse_parity_char(*conf);
365 conf++;
367 uart->stop_bits = simple_strtoul(conf, &conf, 10);
369 if ( *conf == ',' )
370 {
371 conf++;
372 uart->io_base = simple_strtoul(conf, &conf, 0);
374 if ( *conf == ',' )
375 {
376 conf++;
377 uart->irq = simple_strtoul(conf, &conf, 10);
378 }
379 }
381 config_parsed:
382 /* Sanity checks. */
383 if ( (uart->baud != BAUD_AUTO) &&
384 ((uart->baud < 1200) || (uart->baud > 115200)) )
385 PARSE_ERR("Baud rate %d outside supported range.", uart->baud);
386 if ( (uart->data_bits < 5) || (uart->data_bits > 8) )
387 PARSE_ERR("%d data bits are unsupported.", uart->data_bits);
388 if ( (uart->stop_bits < 1) || (uart->stop_bits > 2) )
389 PARSE_ERR("%d stop bits are unsupported.", uart->stop_bits);
390 if ( uart->io_base == 0 )
391 PARSE_ERR("I/O base address must be specified.");
392 if ( !check_existence(uart) )
393 PARSE_ERR("16550-compatible serial UART not present");
395 /* Register with generic serial driver. */
396 serial_register_uart(uart - ns16550_com, &ns16550_driver, uart);
397 }
399 void __init ns16550_init(int index, struct ns16550_defaults *defaults)
400 {
401 struct ns16550 *uart;
403 if ( (index < 0) || (index > 1) )
404 return;
406 uart = &ns16550_com[index];
408 uart->baud = (defaults->baud ? :
409 console_has((index == 0) ? "com1" : "com2")
410 ? BAUD_AUTO : 0);
411 uart->data_bits = defaults->data_bits;
412 uart->parity = parse_parity_char(defaults->parity);
413 uart->stop_bits = defaults->stop_bits;
414 uart->irq = defaults->irq;
415 uart->io_base = defaults->io_base;
417 ns16550_parse_port_config(uart, (index == 0) ? opt_com1 : opt_com2);
418 }
420 /*
421 * Local variables:
422 * mode: C
423 * c-set-style: "BSD"
424 * c-basic-offset: 4
425 * tab-width: 4
426 * indent-tabs-mode: nil
427 * End:
428 */