ia64/xen-unstable

view xen/arch/x86/hvm/vlapic.c @ 16620:966a6d3b7408

SVM: Treat the vlapic's tpr as the master copy and sync the vtpr to it
before every vm entry. This fixes HVM save/restore/migrate, as the
vtpr value was only being synced on guest TPR writes before.

Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Dec 14 11:50:24 2007 +0000 (2007-12-14)
parents 3ee37b6279b7
children 181483b8e959
line source
1 /*
2 * vlapic.c: virtualize LAPIC for HVM vcpus.
3 *
4 * Copyright (c) 2004, Intel Corporation.
5 * Copyright (c) 2006 Keir Fraser, XenSource Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
18 * Place - Suite 330, Boston, MA 02111-1307 USA.
19 */
21 #include <xen/config.h>
22 #include <xen/types.h>
23 #include <xen/mm.h>
24 #include <xen/xmalloc.h>
25 #include <xen/domain_page.h>
26 #include <asm/page.h>
27 #include <xen/event.h>
28 #include <xen/trace.h>
29 #include <asm/hvm/hvm.h>
30 #include <asm/hvm/io.h>
31 #include <asm/hvm/support.h>
32 #include <xen/lib.h>
33 #include <xen/sched.h>
34 #include <asm/current.h>
35 #include <asm/hvm/vmx/vmx.h>
36 #include <public/hvm/ioreq.h>
37 #include <public/hvm/params.h>
39 #define VLAPIC_VERSION 0x00050014
40 #define VLAPIC_LVT_NUM 6
42 /* vlapic's frequence is 100 MHz */
43 #define APIC_BUS_CYCLE_NS 10
45 #define LVT_MASK \
46 APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK
48 #define LINT_MASK \
49 LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY |\
50 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER
52 static unsigned int vlapic_lvt_mask[VLAPIC_LVT_NUM] =
53 {
54 /* LVTT */
55 LVT_MASK | APIC_LVT_TIMER_PERIODIC,
56 /* LVTTHMR */
57 LVT_MASK | APIC_MODE_MASK,
58 /* LVTPC */
59 LVT_MASK | APIC_MODE_MASK,
60 /* LVT0-1 */
61 LINT_MASK, LINT_MASK,
62 /* LVTERR */
63 LVT_MASK
64 };
66 /* Following could belong in apicdef.h */
67 #define APIC_SHORT_MASK 0xc0000
68 #define APIC_DEST_NOSHORT 0x0
69 #define APIC_DEST_MASK 0x800
71 #define vlapic_lvt_vector(vlapic, lvt_type) \
72 (vlapic_get_reg(vlapic, lvt_type) & APIC_VECTOR_MASK)
74 #define vlapic_lvt_dm(vlapic, lvt_type) \
75 (vlapic_get_reg(vlapic, lvt_type) & APIC_MODE_MASK)
77 #define vlapic_lvtt_period(vlapic) \
78 (vlapic_get_reg(vlapic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC)
81 /*
82 * Generic APIC bitmap vector update & search routines.
83 */
85 #define VEC_POS(v) ((v)%32)
86 #define REG_POS(v) (((v)/32)* 0x10)
87 #define vlapic_test_and_set_vector(vec, bitmap) \
88 test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec))
89 #define vlapic_test_and_clear_vector(vec, bitmap) \
90 test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec))
91 #define vlapic_set_vector(vec, bitmap) \
92 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec))
93 #define vlapic_clear_vector(vec, bitmap) \
94 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec))
96 static int vlapic_find_highest_vector(void *bitmap)
97 {
98 uint32_t *word = bitmap;
99 int word_offset = MAX_VECTOR / 32;
101 /* Work backwards through the bitmap (first 32-bit word in every four). */
102 while ( (word_offset != 0) && (word[(--word_offset)*4] == 0) )
103 continue;
105 return (fls(word[word_offset*4]) - 1) + (word_offset * 32);
106 }
109 /*
110 * IRR-specific bitmap update & search routines.
111 */
113 static int vlapic_test_and_set_irr(int vector, struct vlapic *vlapic)
114 {
115 return vlapic_test_and_set_vector(vector, &vlapic->regs->data[APIC_IRR]);
116 }
118 static void vlapic_clear_irr(int vector, struct vlapic *vlapic)
119 {
120 vlapic_clear_vector(vector, &vlapic->regs->data[APIC_IRR]);
121 }
123 static int vlapic_find_highest_irr(struct vlapic *vlapic)
124 {
125 return vlapic_find_highest_vector(&vlapic->regs->data[APIC_IRR]);
126 }
128 int vlapic_set_irq(struct vlapic *vlapic, uint8_t vec, uint8_t trig)
129 {
130 int ret;
132 ret = !vlapic_test_and_set_irr(vec, vlapic);
133 if ( trig )
134 vlapic_set_vector(vec, &vlapic->regs->data[APIC_TMR]);
136 /* We may need to wake up target vcpu, besides set pending bit here */
137 return ret;
138 }
140 static int vlapic_find_highest_isr(struct vlapic *vlapic)
141 {
142 return vlapic_find_highest_vector(&vlapic->regs->data[APIC_ISR]);
143 }
145 uint32_t vlapic_get_ppr(struct vlapic *vlapic)
146 {
147 uint32_t tpr, isrv, ppr;
148 int isr;
150 tpr = vlapic_get_reg(vlapic, APIC_TASKPRI);
151 isr = vlapic_find_highest_isr(vlapic);
152 isrv = (isr != -1) ? isr : 0;
154 if ( (tpr & 0xf0) >= (isrv & 0xf0) )
155 ppr = tpr & 0xff;
156 else
157 ppr = isrv & 0xf0;
159 HVM_DBG_LOG(DBG_LEVEL_VLAPIC_INTERRUPT,
160 "vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
161 vlapic, ppr, isr, isrv);
163 return ppr;
164 }
166 int vlapic_match_logical_addr(struct vlapic *vlapic, uint8_t mda)
167 {
168 int result = 0;
169 uint8_t logical_id;
171 logical_id = GET_APIC_LOGICAL_ID(vlapic_get_reg(vlapic, APIC_LDR));
173 switch ( vlapic_get_reg(vlapic, APIC_DFR) )
174 {
175 case APIC_DFR_FLAT:
176 if ( logical_id & mda )
177 result = 1;
178 break;
179 case APIC_DFR_CLUSTER:
180 if ( ((logical_id >> 4) == (mda >> 0x4)) && (logical_id & mda & 0xf) )
181 result = 1;
182 break;
183 default:
184 gdprintk(XENLOG_WARNING, "Bad DFR value for lapic of vcpu %d: %08x\n",
185 vlapic_vcpu(vlapic)->vcpu_id,
186 vlapic_get_reg(vlapic, APIC_DFR));
187 break;
188 }
190 return result;
191 }
193 static int vlapic_match_dest(struct vcpu *v, struct vlapic *source,
194 int short_hand, int dest, int dest_mode)
195 {
196 int result = 0;
197 struct vlapic *target = vcpu_vlapic(v);
199 HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "target %p, source %p, dest 0x%x, "
200 "dest_mode 0x%x, short_hand 0x%x",
201 target, source, dest, dest_mode, short_hand);
203 switch ( short_hand )
204 {
205 case APIC_DEST_NOSHORT:
206 if ( dest_mode == 0 )
207 {
208 /* Physical mode. */
209 if ( (dest == 0xFF) || (dest == VLAPIC_ID(target)) )
210 result = 1;
211 }
212 else
213 {
214 /* Logical mode. */
215 result = vlapic_match_logical_addr(target, dest);
216 }
217 break;
219 case APIC_DEST_SELF:
220 if ( target == source )
221 result = 1;
222 break;
224 case APIC_DEST_ALLINC:
225 result = 1;
226 break;
228 case APIC_DEST_ALLBUT:
229 if ( target != source )
230 result = 1;
231 break;
233 default:
234 gdprintk(XENLOG_WARNING, "Bad dest shorthand value %x\n", short_hand);
235 break;
236 }
238 return result;
239 }
241 /* Add a pending IRQ into lapic. */
242 static int vlapic_accept_irq(struct vcpu *v, int delivery_mode,
243 int vector, int level, int trig_mode)
244 {
245 int result = 0;
246 struct vlapic *vlapic = vcpu_vlapic(v);
248 switch ( delivery_mode )
249 {
250 case APIC_DM_FIXED:
251 case APIC_DM_LOWEST:
252 /* FIXME add logic for vcpu on reset */
253 if ( unlikely(!vlapic_enabled(vlapic)) )
254 break;
256 if ( vlapic_test_and_set_irr(vector, vlapic) && trig_mode )
257 {
258 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
259 "level trig mode repeatedly for vector %d", vector);
260 break;
261 }
263 if ( trig_mode )
264 {
265 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
266 "level trig mode for vector %d", vector);
267 vlapic_set_vector(vector, &vlapic->regs->data[APIC_TMR]);
268 }
270 vcpu_kick(v);
272 result = 1;
273 break;
275 case APIC_DM_REMRD:
276 gdprintk(XENLOG_WARNING, "Ignoring delivery mode 3\n");
277 break;
279 case APIC_DM_SMI:
280 gdprintk(XENLOG_WARNING, "Ignoring guest SMI\n");
281 break;
283 case APIC_DM_NMI:
284 if ( !test_and_set_bool(v->nmi_pending) )
285 vcpu_kick(v);
286 break;
288 case APIC_DM_INIT:
289 /* No work on INIT de-assert for P4-type APIC. */
290 if ( trig_mode && !(level & APIC_INT_ASSERT) )
291 break;
292 /* FIXME How to check the situation after vcpu reset? */
293 if ( v->is_initialised )
294 hvm_vcpu_reset(v);
295 v->arch.hvm_vcpu.init_sipi_sipi_state =
296 HVM_VCPU_INIT_SIPI_SIPI_STATE_WAIT_SIPI;
297 result = 1;
298 break;
300 case APIC_DM_STARTUP:
301 if ( v->arch.hvm_vcpu.init_sipi_sipi_state ==
302 HVM_VCPU_INIT_SIPI_SIPI_STATE_NORM )
303 break;
305 v->arch.hvm_vcpu.init_sipi_sipi_state =
306 HVM_VCPU_INIT_SIPI_SIPI_STATE_NORM;
308 if ( v->is_initialised )
309 {
310 gdprintk(XENLOG_ERR, "SIPI for initialized vcpu %x\n", v->vcpu_id);
311 goto exit_and_crash;
312 }
314 if ( hvm_bringup_ap(v->vcpu_id, vector) != 0 )
315 result = 0;
316 break;
318 default:
319 gdprintk(XENLOG_ERR, "TODO: unsupported delivery mode %x\n",
320 delivery_mode);
321 goto exit_and_crash;
322 }
324 return result;
326 exit_and_crash:
327 domain_crash(v->domain);
328 return 0;
329 }
331 /* This function is used by both ioapic and lapic.The bitmap is for vcpu_id. */
332 struct vlapic *apic_round_robin(
333 struct domain *d, uint8_t vector, uint32_t bitmap)
334 {
335 int next, old;
336 struct vlapic *target = NULL;
338 old = next = d->arch.hvm_domain.irq.round_robin_prev_vcpu;
340 do {
341 if ( ++next == MAX_VIRT_CPUS )
342 next = 0;
343 if ( (d->vcpu[next] == NULL) || !test_bit(next, &bitmap) )
344 continue;
345 target = vcpu_vlapic(d->vcpu[next]);
346 if ( vlapic_enabled(target) )
347 break;
348 target = NULL;
349 } while ( next != old );
351 d->arch.hvm_domain.irq.round_robin_prev_vcpu = next;
353 return target;
354 }
356 void vlapic_EOI_set(struct vlapic *vlapic)
357 {
358 int vector = vlapic_find_highest_isr(vlapic);
360 /* Some EOI writes may not have a matching to an in-service interrupt. */
361 if ( vector == -1 )
362 return;
364 vlapic_clear_vector(vector, &vlapic->regs->data[APIC_ISR]);
366 if ( vlapic_test_and_clear_vector(vector, &vlapic->regs->data[APIC_TMR]) )
367 vioapic_update_EOI(vlapic_domain(vlapic), vector);
368 }
370 static void vlapic_ipi(struct vlapic *vlapic)
371 {
372 uint32_t icr_low = vlapic_get_reg(vlapic, APIC_ICR);
373 uint32_t icr_high = vlapic_get_reg(vlapic, APIC_ICR2);
375 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
376 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
377 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
378 unsigned int level = icr_low & APIC_INT_ASSERT;
379 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
380 unsigned int delivery_mode =icr_low & APIC_MODE_MASK;
381 unsigned int vector = icr_low & APIC_VECTOR_MASK;
383 struct vlapic *target;
384 struct vcpu *v;
385 uint32_t lpr_map = 0;
387 HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "icr_high 0x%x, icr_low 0x%x, "
388 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
389 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x",
390 icr_high, icr_low, short_hand, dest,
391 trig_mode, level, dest_mode, delivery_mode, vector);
393 for_each_vcpu ( vlapic_domain(vlapic), v )
394 {
395 if ( vlapic_match_dest(v, vlapic, short_hand, dest, dest_mode) )
396 {
397 if ( delivery_mode == APIC_DM_LOWEST )
398 __set_bit(v->vcpu_id, &lpr_map);
399 else
400 vlapic_accept_irq(v, delivery_mode,
401 vector, level, trig_mode);
402 }
403 }
405 if ( delivery_mode == APIC_DM_LOWEST )
406 {
407 target = apic_round_robin(vlapic_domain(v), vector, lpr_map);
408 if ( target != NULL )
409 vlapic_accept_irq(vlapic_vcpu(target), delivery_mode,
410 vector, level, trig_mode);
411 }
412 }
414 static uint32_t vlapic_get_tmcct(struct vlapic *vlapic)
415 {
416 struct vcpu *v = current;
417 uint32_t tmcct, tmict = vlapic_get_reg(vlapic, APIC_TMICT);
418 uint64_t counter_passed;
420 counter_passed = ((hvm_get_guest_time(v) - vlapic->timer_last_update)
421 * 1000000000ULL / ticks_per_sec(v)
422 / APIC_BUS_CYCLE_NS / vlapic->hw.timer_divisor);
423 tmcct = tmict - counter_passed;
425 HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER,
426 "timer initial count %d, timer current count %d, "
427 "offset %"PRId64,
428 tmict, tmcct, counter_passed);
430 return tmcct;
431 }
433 static void vlapic_set_tdcr(struct vlapic *vlapic, unsigned int val)
434 {
435 /* Only bits 0, 1 and 3 are settable; others are MBZ. */
436 val &= 0xb;
437 vlapic_set_reg(vlapic, APIC_TDCR, val);
439 /* Update the demangled hw.timer_divisor. */
440 val = ((val & 3) | ((val & 8) >> 1)) + 1;
441 vlapic->hw.timer_divisor = 1 << (val & 7);
443 HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER,
444 "timer_divisor: %d", vlapic->hw.timer_divisor);
445 }
447 static void vlapic_read_aligned(
448 struct vlapic *vlapic, unsigned int offset, unsigned int *result)
449 {
450 switch ( offset )
451 {
452 case APIC_PROCPRI:
453 *result = vlapic_get_ppr(vlapic);
454 break;
456 case APIC_TMCCT: /* Timer CCR */
457 *result = vlapic_get_tmcct(vlapic);
458 break;
460 default:
461 *result = vlapic_get_reg(vlapic, offset);
462 break;
463 }
464 }
466 static unsigned long vlapic_read(struct vcpu *v, unsigned long address,
467 unsigned long len)
468 {
469 unsigned int alignment;
470 unsigned int tmp;
471 unsigned long result;
472 struct vlapic *vlapic = vcpu_vlapic(v);
473 unsigned int offset = address - vlapic_base_address(vlapic);
475 if ( offset > APIC_TDCR )
476 return 0;
478 alignment = offset & 0x3;
480 vlapic_read_aligned(vlapic, offset & ~0x3, &tmp);
481 switch ( len )
482 {
483 case 1:
484 result = *((unsigned char *)&tmp + alignment);
485 break;
487 case 2:
488 if ( alignment == 3 )
489 goto unaligned_exit_and_crash;
490 result = *(unsigned short *)((unsigned char *)&tmp + alignment);
491 break;
493 case 4:
494 if ( alignment != 0 )
495 goto unaligned_exit_and_crash;
496 result = *(unsigned int *)((unsigned char *)&tmp + alignment);
497 break;
499 default:
500 gdprintk(XENLOG_ERR, "Local APIC read with len=0x%lx, "
501 "should be 4 instead.\n", len);
502 goto exit_and_crash;
503 }
505 HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "offset 0x%x with length 0x%lx, "
506 "and the result is 0x%lx", offset, len, result);
508 return result;
510 unaligned_exit_and_crash:
511 gdprintk(XENLOG_ERR, "Unaligned LAPIC read len=0x%lx at offset=0x%x.\n",
512 len, offset);
513 exit_and_crash:
514 domain_crash(v->domain);
515 return 0;
516 }
518 void vlapic_pt_cb(struct vcpu *v, void *data)
519 {
520 *(s_time_t *)data = hvm_get_guest_time(v);
521 }
523 static void vlapic_write(struct vcpu *v, unsigned long address,
524 unsigned long len, unsigned long val)
525 {
526 struct vlapic *vlapic = vcpu_vlapic(v);
527 unsigned int offset = address - vlapic_base_address(vlapic);
529 if ( offset != 0xb0 )
530 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
531 "offset 0x%x with length 0x%lx, and value is 0x%lx",
532 offset, len, val);
534 /*
535 * According to the IA32 Manual, all accesses should be 32 bits.
536 * Some OSes do 8- or 16-byte accesses, however.
537 */
538 val &= 0xffffffff;
539 if ( len != 4 )
540 {
541 unsigned int tmp;
542 unsigned char alignment;
544 gdprintk(XENLOG_INFO, "Notice: Local APIC write with len = %lx\n",len);
546 alignment = offset & 0x3;
547 tmp = vlapic_read(v, offset & ~0x3, 4);
549 switch ( len )
550 {
551 case 1:
552 val = (tmp & ~(0xff << (8*alignment))) |
553 ((val & 0xff) << (8*alignment));
554 break;
556 case 2:
557 if ( alignment & 1 )
558 {
559 gdprintk(XENLOG_ERR, "Uneven alignment error for "
560 "2-byte vlapic access\n");
561 goto exit_and_crash;
562 }
564 val = (tmp & ~(0xffff << (8*alignment))) |
565 ((val & 0xffff) << (8*alignment));
566 break;
568 default:
569 gdprintk(XENLOG_ERR, "Local APIC write with len = %lx, "
570 "should be 4 instead\n", len);
571 exit_and_crash:
572 domain_crash(v->domain);
573 return;
574 }
575 }
577 offset &= 0xff0;
579 switch ( offset )
580 {
581 case APIC_TASKPRI:
582 vlapic_set_reg(vlapic, APIC_TASKPRI, val & 0xff);
583 break;
585 case APIC_EOI:
586 vlapic_EOI_set(vlapic);
587 break;
589 case APIC_LDR:
590 vlapic_set_reg(vlapic, APIC_LDR, val & APIC_LDR_MASK);
591 break;
593 case APIC_DFR:
594 vlapic_set_reg(vlapic, APIC_DFR, val | 0x0FFFFFFF);
595 break;
597 case APIC_SPIV:
598 vlapic_set_reg(vlapic, APIC_SPIV, val & 0x3ff);
600 if ( !(val & APIC_SPIV_APIC_ENABLED) )
601 {
602 int i;
603 uint32_t lvt_val;
605 vlapic->hw.disabled |= VLAPIC_SW_DISABLED;
607 for ( i = 0; i < VLAPIC_LVT_NUM; i++ )
608 {
609 lvt_val = vlapic_get_reg(vlapic, APIC_LVTT + 0x10 * i);
610 vlapic_set_reg(vlapic, APIC_LVTT + 0x10 * i,
611 lvt_val | APIC_LVT_MASKED);
612 }
613 }
614 else
615 vlapic->hw.disabled &= ~VLAPIC_SW_DISABLED;
616 break;
618 case APIC_ESR:
619 /* Nothing to do. */
620 break;
622 case APIC_ICR:
623 /* No delay here, so we always clear the pending bit*/
624 vlapic_set_reg(vlapic, APIC_ICR, val & ~(1 << 12));
625 vlapic_ipi(vlapic);
626 break;
628 case APIC_ICR2:
629 vlapic_set_reg(vlapic, APIC_ICR2, val & 0xff000000);
630 break;
632 case APIC_LVTT: /* LVT Timer Reg */
633 vlapic->pt.irq = val & APIC_VECTOR_MASK;
634 case APIC_LVTTHMR: /* LVT Thermal Monitor */
635 case APIC_LVTPC: /* LVT Performance Counter */
636 case APIC_LVT0: /* LVT LINT0 Reg */
637 case APIC_LVT1: /* LVT Lint1 Reg */
638 case APIC_LVTERR: /* LVT Error Reg */
639 if ( vlapic_sw_disabled(vlapic) )
640 val |= APIC_LVT_MASKED;
641 val &= vlapic_lvt_mask[(offset - APIC_LVTT) >> 4];
642 vlapic_set_reg(vlapic, offset, val);
643 break;
645 case APIC_TMICT:
646 {
647 uint64_t period = (uint64_t)APIC_BUS_CYCLE_NS *
648 (uint32_t)val * vlapic->hw.timer_divisor;
650 vlapic_set_reg(vlapic, APIC_TMICT, val);
651 create_periodic_time(current, &vlapic->pt, period, vlapic->pt.irq,
652 !vlapic_lvtt_period(vlapic), vlapic_pt_cb,
653 &vlapic->timer_last_update);
654 vlapic->timer_last_update = vlapic->pt.last_plt_gtime;
656 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
657 "bus cycle is %uns, "
658 "initial count %lu, period %"PRIu64"ns",
659 APIC_BUS_CYCLE_NS, val, period);
660 }
661 break;
663 case APIC_TDCR:
664 vlapic_set_tdcr(vlapic, val & 0xb);
665 HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER, "timer divisor is 0x%x",
666 vlapic->hw.timer_divisor);
667 break;
669 default:
670 gdprintk(XENLOG_DEBUG,
671 "Local APIC Write to read-only register 0x%x\n", offset);
672 break;
673 }
674 }
676 static int vlapic_range(struct vcpu *v, unsigned long addr)
677 {
678 struct vlapic *vlapic = vcpu_vlapic(v);
679 unsigned long offset = addr - vlapic_base_address(vlapic);
680 return (!vlapic_hw_disabled(vlapic) && (offset < PAGE_SIZE));
681 }
683 struct hvm_mmio_handler vlapic_mmio_handler = {
684 .check_handler = vlapic_range,
685 .read_handler = vlapic_read,
686 .write_handler = vlapic_write
687 };
689 void vlapic_msr_set(struct vlapic *vlapic, uint64_t value)
690 {
691 if ( (vlapic->hw.apic_base_msr ^ value) & MSR_IA32_APICBASE_ENABLE )
692 {
693 if ( value & MSR_IA32_APICBASE_ENABLE )
694 {
695 vlapic_reset(vlapic);
696 vlapic->hw.disabled &= ~VLAPIC_HW_DISABLED;
697 }
698 else
699 {
700 vlapic->hw.disabled |= VLAPIC_HW_DISABLED;
701 }
702 }
704 vlapic->hw.apic_base_msr = value;
706 vmx_vlapic_msr_changed(vlapic_vcpu(vlapic));
708 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
709 "apic base msr is 0x%016"PRIx64, vlapic->hw.apic_base_msr);
710 }
712 int vlapic_accept_pic_intr(struct vcpu *v)
713 {
714 struct vlapic *vlapic = vcpu_vlapic(v);
715 uint32_t lvt0 = vlapic_get_reg(vlapic, APIC_LVT0);
717 /*
718 * Only CPU0 is wired to the 8259A. INTA cycles occur if LINT0 is set up
719 * accept ExtInts, or if the LAPIC is disabled (so LINT0 behaves as INTR).
720 */
721 return ((v->vcpu_id == 0) &&
722 (((lvt0 & (APIC_MODE_MASK|APIC_LVT_MASKED)) == APIC_DM_EXTINT) ||
723 vlapic_hw_disabled(vlapic)));
724 }
726 int vlapic_has_pending_irq(struct vcpu *v)
727 {
728 struct vlapic *vlapic = vcpu_vlapic(v);
729 int irr, isr;
731 if ( !vlapic_enabled(vlapic) )
732 return -1;
734 irr = vlapic_find_highest_irr(vlapic);
735 if ( irr == -1 )
736 return -1;
738 isr = vlapic_find_highest_isr(vlapic);
739 isr = (isr != -1) ? isr : 0;
740 if ( (isr & 0xf0) >= (irr & 0xf0) )
741 return -1;
743 return irr;
744 }
746 int vlapic_ack_pending_irq(struct vcpu *v, int vector)
747 {
748 struct vlapic *vlapic = vcpu_vlapic(v);
750 vlapic_set_vector(vector, &vlapic->regs->data[APIC_ISR]);
751 vlapic_clear_irr(vector, vlapic);
753 return 1;
754 }
756 /* Reset the VLPAIC back to its power-on/reset state. */
757 void vlapic_reset(struct vlapic *vlapic)
758 {
759 struct vcpu *v = vlapic_vcpu(vlapic);
760 int i;
762 vlapic_set_reg(vlapic, APIC_ID, (v->vcpu_id * 2) << 24);
763 vlapic_set_reg(vlapic, APIC_LVR, VLAPIC_VERSION);
765 for ( i = 0; i < 8; i++ )
766 {
767 vlapic_set_reg(vlapic, APIC_IRR + 0x10 * i, 0);
768 vlapic_set_reg(vlapic, APIC_ISR + 0x10 * i, 0);
769 vlapic_set_reg(vlapic, APIC_TMR + 0x10 * i, 0);
770 }
771 vlapic_set_reg(vlapic, APIC_ICR, 0);
772 vlapic_set_reg(vlapic, APIC_ICR2, 0);
773 vlapic_set_reg(vlapic, APIC_LDR, 0);
774 vlapic_set_reg(vlapic, APIC_TASKPRI, 0);
775 vlapic_set_reg(vlapic, APIC_TMICT, 0);
776 vlapic_set_reg(vlapic, APIC_TMCCT, 0);
777 vlapic_set_tdcr(vlapic, 0);
779 vlapic_set_reg(vlapic, APIC_DFR, 0xffffffffU);
781 for ( i = 0; i < VLAPIC_LVT_NUM; i++ )
782 vlapic_set_reg(vlapic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
784 vlapic_set_reg(vlapic, APIC_SPIV, 0xff);
785 vlapic->hw.disabled |= VLAPIC_SW_DISABLED;
786 }
788 #ifdef HVM_DEBUG_SUSPEND
789 static void lapic_info(struct vlapic *s)
790 {
791 printk("*****lapic state:*****\n");
792 printk("lapic 0x%"PRIx64".\n", s->hw.apic_base_msr);
793 printk("lapic 0x%x.\n", s->hw.disabled);
794 printk("lapic 0x%x.\n", s->hw.timer_divisor);
795 }
796 #else
797 static void lapic_info(struct vlapic *s)
798 {
799 }
800 #endif
802 /* rearm the actimer if needed, after a HVM restore */
803 static void lapic_rearm(struct vlapic *s)
804 {
805 unsigned long tmict;
807 tmict = vlapic_get_reg(s, APIC_TMICT);
808 if ( tmict > 0 )
809 {
810 uint64_t period = (uint64_t)APIC_BUS_CYCLE_NS *
811 (uint32_t)tmict * s->hw.timer_divisor;
812 uint32_t lvtt = vlapic_get_reg(s, APIC_LVTT);
814 s->pt.irq = lvtt & APIC_VECTOR_MASK;
815 create_periodic_time(vlapic_vcpu(s), &s->pt, period, s->pt.irq,
816 !vlapic_lvtt_period(s), vlapic_pt_cb,
817 &s->timer_last_update);
818 s->timer_last_update = s->pt.last_plt_gtime;
820 printk("lapic_load to rearm the actimer:"
821 "bus cycle is %uns, "
822 "saved tmict count %lu, period %"PRIu64"ns, irq=%"PRIu8"\n",
823 APIC_BUS_CYCLE_NS, tmict, period, s->pt.irq);
824 }
826 lapic_info(s);
827 }
829 static int lapic_save_hidden(struct domain *d, hvm_domain_context_t *h)
830 {
831 struct vcpu *v;
832 struct vlapic *s;
834 for_each_vcpu(d, v)
835 {
836 s = vcpu_vlapic(v);
837 lapic_info(s);
839 if ( hvm_save_entry(LAPIC, v->vcpu_id, h, &s->hw) != 0 )
840 return 1;
841 }
842 return 0;
843 }
845 static int lapic_save_regs(struct domain *d, hvm_domain_context_t *h)
846 {
847 struct vcpu *v;
848 struct vlapic *s;
850 for_each_vcpu(d, v)
851 {
852 s = vcpu_vlapic(v);
853 if ( hvm_save_entry(LAPIC_REGS, v->vcpu_id, h, s->regs) != 0 )
854 return 1;
855 }
856 return 0;
857 }
859 static int lapic_load_hidden(struct domain *d, hvm_domain_context_t *h)
860 {
861 uint16_t vcpuid;
862 struct vcpu *v;
863 struct vlapic *s;
865 /* Which vlapic to load? */
866 vcpuid = hvm_load_instance(h);
867 if ( vcpuid > MAX_VIRT_CPUS || (v = d->vcpu[vcpuid]) == NULL )
868 {
869 gdprintk(XENLOG_ERR, "HVM restore: domain has no vlapic %u\n", vcpuid);
870 return -EINVAL;
871 }
872 s = vcpu_vlapic(v);
874 if ( hvm_load_entry(LAPIC, h, &s->hw) != 0 )
875 return -EINVAL;
877 lapic_info(s);
879 vmx_vlapic_msr_changed(v);
881 return 0;
882 }
884 static int lapic_load_regs(struct domain *d, hvm_domain_context_t *h)
885 {
886 uint16_t vcpuid;
887 struct vcpu *v;
888 struct vlapic *s;
890 /* Which vlapic to load? */
891 vcpuid = hvm_load_instance(h);
892 if ( vcpuid > MAX_VIRT_CPUS || (v = d->vcpu[vcpuid]) == NULL )
893 {
894 gdprintk(XENLOG_ERR, "HVM restore: domain has no vlapic %u\n", vcpuid);
895 return -EINVAL;
896 }
897 s = vcpu_vlapic(v);
899 if ( hvm_load_entry(LAPIC_REGS, h, s->regs) != 0 )
900 return -EINVAL;
902 lapic_rearm(s);
903 return 0;
904 }
906 HVM_REGISTER_SAVE_RESTORE(LAPIC, lapic_save_hidden, lapic_load_hidden,
907 1, HVMSR_PER_VCPU);
908 HVM_REGISTER_SAVE_RESTORE(LAPIC_REGS, lapic_save_regs, lapic_load_regs,
909 1, HVMSR_PER_VCPU);
911 int vlapic_init(struct vcpu *v)
912 {
913 struct vlapic *vlapic = vcpu_vlapic(v);
914 unsigned int memflags = 0;
916 HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "%d", v->vcpu_id);
918 vlapic->pt.source = PTSRC_lapic;
920 #ifdef __i386__
921 /* 32-bit VMX may be limited to 32-bit physical addresses. */
922 if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
923 memflags = MEMF_bits(32);
924 #endif
926 vlapic->regs_page = alloc_domheap_pages(NULL, 0, memflags);
927 if ( vlapic->regs_page == NULL )
928 {
929 dprintk(XENLOG_ERR, "alloc vlapic regs error: %d/%d\n",
930 v->domain->domain_id, v->vcpu_id);
931 return -ENOMEM;
932 }
934 vlapic->regs = map_domain_page_global(page_to_mfn(vlapic->regs_page));
935 if ( vlapic->regs == NULL )
936 {
937 dprintk(XENLOG_ERR, "map vlapic regs error: %d/%d\n",
938 v->domain->domain_id, v->vcpu_id);
939 return -ENOMEM;
940 }
942 clear_page(vlapic->regs);
944 vlapic_reset(vlapic);
946 vlapic->hw.apic_base_msr = (MSR_IA32_APICBASE_ENABLE |
947 APIC_DEFAULT_PHYS_BASE);
948 if ( v->vcpu_id == 0 )
949 vlapic->hw.apic_base_msr |= MSR_IA32_APICBASE_BSP;
951 return 0;
952 }
954 void vlapic_destroy(struct vcpu *v)
955 {
956 struct vlapic *vlapic = vcpu_vlapic(v);
958 destroy_periodic_time(&vlapic->pt);
959 unmap_domain_page_global(vlapic->regs);
960 free_domheap_page(vlapic->regs_page);
961 }