ia64/xen-unstable

view xen/include/asm-x86/hvm/vmx/vmcs.h @ 16989:92734271810a

vmx realmode: Emulate protected-mode transition while CS and SS have
bad selector values (bottom two bits non-zero).

Allows opensuse 10.3 install CD to boot. Unfortunately SUSE Linux 10.1
install CD still fails to work...

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Feb 05 15:45:10 2008 +0000 (2008-02-05)
parents aecbf98aa709
children 9d0e86d8c1d1
line source
1 /*
2 * vmcs.h: VMCS related definitions
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 #ifndef __ASM_X86_HVM_VMX_VMCS_H__
20 #define __ASM_X86_HVM_VMX_VMCS_H__
22 #include <asm/config.h>
23 #include <asm/hvm/io.h>
24 #include <asm/hvm/vmx/cpu.h>
25 #include <asm/hvm/vmx/vpmu.h>
27 #ifdef VMXASSIST
28 #include <public/hvm/vmx_assist.h>
29 #endif
31 extern void start_vmx(void);
32 extern void vmcs_dump_vcpu(struct vcpu *v);
33 extern void setup_vmcs_dump(void);
34 extern int vmx_cpu_up(void);
35 extern void vmx_cpu_down(void);
37 struct vmcs_struct {
38 u32 vmcs_revision_id;
39 unsigned char data [0]; /* vmcs size is read from MSR */
40 };
42 struct vmx_msr_entry {
43 u32 index;
44 u32 mbz;
45 u64 data;
46 };
48 enum {
49 VMX_INDEX_MSR_LSTAR = 0,
50 VMX_INDEX_MSR_STAR,
51 VMX_INDEX_MSR_SYSCALL_MASK,
53 VMX_MSR_COUNT
54 };
56 struct vmx_msr_state {
57 unsigned long flags;
58 unsigned long msrs[VMX_MSR_COUNT];
59 };
61 struct arch_vmx_struct {
62 /* Virtual address of VMCS. */
63 struct vmcs_struct *vmcs;
65 /* Protects remote usage of VMCS (VMPTRLD/VMCLEAR). */
66 spinlock_t vmcs_lock;
68 /*
69 * Activation and launch status of this VMCS.
70 * - Activated on a CPU by VMPTRLD. Deactivated by VMCLEAR.
71 * - Launched on active CPU by VMLAUNCH when current VMCS.
72 */
73 struct list_head active_list;
74 int active_cpu;
75 int launched;
77 /* Cache of cpu execution control. */
78 u32 exec_control;
80 /* PMU */
81 struct vpmu_struct vpmu;
83 #ifdef __x86_64__
84 struct vmx_msr_state msr_state;
85 unsigned long shadow_gs;
86 unsigned long cstar;
87 #endif
89 char *msr_bitmap;
90 unsigned int msr_count;
91 struct vmx_msr_entry *msr_area;
92 unsigned int host_msr_count;
93 struct vmx_msr_entry *host_msr_area;
95 unsigned long host_cr0;
97 #ifdef VMXASSIST
99 unsigned long vmxassist_enabled:1;
100 unsigned long irqbase_mode:1;
101 unsigned char pm_irqbase[2];
103 #else
105 /* Are we emulating rather than VMENTERing? */
106 #define VMXEMUL_REALMODE 1 /* Yes, because CR0.PE == 0 */
107 #define VMXEMUL_BAD_CS 2 /* Yes, because CS.RPL != CPL */
108 #define VMXEMUL_BAD_SS 4 /* Yes, because SS.RPL != CPL */
109 uint8_t vmxemul;
111 /* I/O request in flight to device model. */
112 bool_t real_mode_io_in_progress;
113 bool_t real_mode_io_completed;
114 unsigned long real_mode_io_data;
115 #endif
116 };
118 int vmx_create_vmcs(struct vcpu *v);
119 void vmx_destroy_vmcs(struct vcpu *v);
120 void vmx_vmcs_enter(struct vcpu *v);
121 void vmx_vmcs_exit(struct vcpu *v);
123 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
124 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008
125 #define CPU_BASED_HLT_EXITING 0x00000080
126 #define CPU_BASED_INVLPG_EXITING 0x00000200
127 #define CPU_BASED_MWAIT_EXITING 0x00000400
128 #define CPU_BASED_RDPMC_EXITING 0x00000800
129 #define CPU_BASED_RDTSC_EXITING 0x00001000
130 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000
131 #define CPU_BASED_CR8_STORE_EXITING 0x00100000
132 #define CPU_BASED_TPR_SHADOW 0x00200000
133 #define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
134 #define CPU_BASED_MOV_DR_EXITING 0x00800000
135 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000
136 #define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000
137 #define CPU_BASED_ACTIVATE_MSR_BITMAP 0x10000000
138 #define CPU_BASED_MONITOR_EXITING 0x20000000
139 #define CPU_BASED_PAUSE_EXITING 0x40000000
140 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
141 extern u32 vmx_cpu_based_exec_control;
143 #define PIN_BASED_EXT_INTR_MASK 0x00000001
144 #define PIN_BASED_NMI_EXITING 0x00000008
145 #define PIN_BASED_VIRTUAL_NMIS 0x00000020
146 extern u32 vmx_pin_based_exec_control;
148 #define VM_EXIT_IA32E_MODE 0x00000200
149 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
150 extern u32 vmx_vmexit_control;
152 #define VM_ENTRY_IA32E_MODE 0x00000200
153 #define VM_ENTRY_SMM 0x00000400
154 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
155 extern u32 vmx_vmentry_control;
157 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
158 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
159 extern u32 vmx_secondary_exec_control;
161 extern bool_t cpu_has_vmx_ins_outs_instr_info;
163 #define cpu_has_wbinvd_exiting \
164 (vmx_secondary_exec_control & SECONDARY_EXEC_WBINVD_EXITING)
165 #define cpu_has_vmx_virtualize_apic_accesses \
166 (vmx_secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
167 #define cpu_has_vmx_tpr_shadow \
168 (vmx_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)
169 #define cpu_has_vmx_vnmi \
170 (vmx_pin_based_exec_control & PIN_BASED_VIRTUAL_NMIS)
171 #define cpu_has_vmx_msr_bitmap \
172 (vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_MSR_BITMAP)
174 /* GUEST_INTERRUPTIBILITY_INFO flags. */
175 #define VMX_INTR_SHADOW_STI 0x00000001
176 #define VMX_INTR_SHADOW_MOV_SS 0x00000002
177 #define VMX_INTR_SHADOW_SMI 0x00000004
178 #define VMX_INTR_SHADOW_NMI 0x00000008
180 /* VMCS field encodings. */
181 enum vmcs_field {
182 GUEST_ES_SELECTOR = 0x00000800,
183 GUEST_CS_SELECTOR = 0x00000802,
184 GUEST_SS_SELECTOR = 0x00000804,
185 GUEST_DS_SELECTOR = 0x00000806,
186 GUEST_FS_SELECTOR = 0x00000808,
187 GUEST_GS_SELECTOR = 0x0000080a,
188 GUEST_LDTR_SELECTOR = 0x0000080c,
189 GUEST_TR_SELECTOR = 0x0000080e,
190 HOST_ES_SELECTOR = 0x00000c00,
191 HOST_CS_SELECTOR = 0x00000c02,
192 HOST_SS_SELECTOR = 0x00000c04,
193 HOST_DS_SELECTOR = 0x00000c06,
194 HOST_FS_SELECTOR = 0x00000c08,
195 HOST_GS_SELECTOR = 0x00000c0a,
196 HOST_TR_SELECTOR = 0x00000c0c,
197 IO_BITMAP_A = 0x00002000,
198 IO_BITMAP_A_HIGH = 0x00002001,
199 IO_BITMAP_B = 0x00002002,
200 IO_BITMAP_B_HIGH = 0x00002003,
201 MSR_BITMAP = 0x00002004,
202 MSR_BITMAP_HIGH = 0x00002005,
203 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
204 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
205 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
206 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
207 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
208 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
209 TSC_OFFSET = 0x00002010,
210 TSC_OFFSET_HIGH = 0x00002011,
211 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
212 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
213 APIC_ACCESS_ADDR = 0x00002014,
214 APIC_ACCESS_ADDR_HIGH = 0x00002015,
215 VMCS_LINK_POINTER = 0x00002800,
216 VMCS_LINK_POINTER_HIGH = 0x00002801,
217 GUEST_IA32_DEBUGCTL = 0x00002802,
218 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
219 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
220 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
221 EXCEPTION_BITMAP = 0x00004004,
222 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
223 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
224 CR3_TARGET_COUNT = 0x0000400a,
225 VM_EXIT_CONTROLS = 0x0000400c,
226 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
227 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
228 VM_ENTRY_CONTROLS = 0x00004012,
229 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
230 VM_ENTRY_INTR_INFO = 0x00004016,
231 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
232 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
233 TPR_THRESHOLD = 0x0000401c,
234 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
235 VM_INSTRUCTION_ERROR = 0x00004400,
236 VM_EXIT_REASON = 0x00004402,
237 VM_EXIT_INTR_INFO = 0x00004404,
238 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
239 IDT_VECTORING_INFO = 0x00004408,
240 IDT_VECTORING_ERROR_CODE = 0x0000440a,
241 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
242 VMX_INSTRUCTION_INFO = 0x0000440e,
243 GUEST_ES_LIMIT = 0x00004800,
244 GUEST_CS_LIMIT = 0x00004802,
245 GUEST_SS_LIMIT = 0x00004804,
246 GUEST_DS_LIMIT = 0x00004806,
247 GUEST_FS_LIMIT = 0x00004808,
248 GUEST_GS_LIMIT = 0x0000480a,
249 GUEST_LDTR_LIMIT = 0x0000480c,
250 GUEST_TR_LIMIT = 0x0000480e,
251 GUEST_GDTR_LIMIT = 0x00004810,
252 GUEST_IDTR_LIMIT = 0x00004812,
253 GUEST_ES_AR_BYTES = 0x00004814,
254 GUEST_CS_AR_BYTES = 0x00004816,
255 GUEST_SS_AR_BYTES = 0x00004818,
256 GUEST_DS_AR_BYTES = 0x0000481a,
257 GUEST_FS_AR_BYTES = 0x0000481c,
258 GUEST_GS_AR_BYTES = 0x0000481e,
259 GUEST_LDTR_AR_BYTES = 0x00004820,
260 GUEST_TR_AR_BYTES = 0x00004822,
261 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
262 GUEST_ACTIVITY_STATE = 0x00004826,
263 GUEST_SYSENTER_CS = 0x0000482A,
264 HOST_SYSENTER_CS = 0x00004c00,
265 CR0_GUEST_HOST_MASK = 0x00006000,
266 CR4_GUEST_HOST_MASK = 0x00006002,
267 CR0_READ_SHADOW = 0x00006004,
268 CR4_READ_SHADOW = 0x00006006,
269 CR3_TARGET_VALUE0 = 0x00006008,
270 CR3_TARGET_VALUE1 = 0x0000600a,
271 CR3_TARGET_VALUE2 = 0x0000600c,
272 CR3_TARGET_VALUE3 = 0x0000600e,
273 EXIT_QUALIFICATION = 0x00006400,
274 GUEST_LINEAR_ADDRESS = 0x0000640a,
275 GUEST_CR0 = 0x00006800,
276 GUEST_CR3 = 0x00006802,
277 GUEST_CR4 = 0x00006804,
278 GUEST_ES_BASE = 0x00006806,
279 GUEST_CS_BASE = 0x00006808,
280 GUEST_SS_BASE = 0x0000680a,
281 GUEST_DS_BASE = 0x0000680c,
282 GUEST_FS_BASE = 0x0000680e,
283 GUEST_GS_BASE = 0x00006810,
284 GUEST_LDTR_BASE = 0x00006812,
285 GUEST_TR_BASE = 0x00006814,
286 GUEST_GDTR_BASE = 0x00006816,
287 GUEST_IDTR_BASE = 0x00006818,
288 GUEST_DR7 = 0x0000681a,
289 GUEST_RSP = 0x0000681c,
290 GUEST_RIP = 0x0000681e,
291 GUEST_RFLAGS = 0x00006820,
292 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
293 GUEST_SYSENTER_ESP = 0x00006824,
294 GUEST_SYSENTER_EIP = 0x00006826,
295 HOST_CR0 = 0x00006c00,
296 HOST_CR3 = 0x00006c02,
297 HOST_CR4 = 0x00006c04,
298 HOST_FS_BASE = 0x00006c06,
299 HOST_GS_BASE = 0x00006c08,
300 HOST_TR_BASE = 0x00006c0a,
301 HOST_GDTR_BASE = 0x00006c0c,
302 HOST_IDTR_BASE = 0x00006c0e,
303 HOST_SYSENTER_ESP = 0x00006c10,
304 HOST_SYSENTER_EIP = 0x00006c12,
305 HOST_RSP = 0x00006c14,
306 HOST_RIP = 0x00006c16,
307 };
309 void vmx_disable_intercept_for_msr(struct vcpu *v, u32 msr);
310 int vmx_read_guest_msr(struct vcpu *v, u32 msr, u64 *val);
311 int vmx_write_guest_msr(struct vcpu *v, u32 msr, u64 val);
312 int vmx_add_guest_msr(struct vcpu *v, u32 msr);
313 int vmx_add_host_load_msr(struct vcpu *v, u32 msr);
315 #endif /* ASM_X86_HVM_VMX_VMCS_H__ */
317 /*
318 * Local variables:
319 * mode: C
320 * c-set-style: "BSD"
321 * c-basic-offset: 4
322 * tab-width: 4
323 * indent-tabs-mode: nil
324 * End:
325 */