ia64/xen-unstable

view xen/arch/x86/hvm/vmx/vmx.c @ 10661:8e55c5c11475

[XEN] Add CPUID hypervisor-info leaves at index 0x40000000.
Currently only a signature leaf is defined ("Xen\0").
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Wed Jul 05 18:48:41 2006 +0100 (2006-07-05)
parents d6363854fb35
children 3fa8b914e2b5
line source
1 /*
2 * vmx.c: handling VMX architecture-related VM exits
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
20 #include <xen/config.h>
21 #include <xen/init.h>
22 #include <xen/lib.h>
23 #include <xen/trace.h>
24 #include <xen/sched.h>
25 #include <xen/irq.h>
26 #include <xen/softirq.h>
27 #include <xen/domain_page.h>
28 #include <asm/current.h>
29 #include <asm/io.h>
30 #include <asm/shadow.h>
31 #include <asm/regs.h>
32 #include <asm/cpufeature.h>
33 #include <asm/processor.h>
34 #include <asm/types.h>
35 #include <asm/msr.h>
36 #include <asm/spinlock.h>
37 #include <asm/hvm/hvm.h>
38 #include <asm/hvm/support.h>
39 #include <asm/hvm/vmx/vmx.h>
40 #include <asm/hvm/vmx/vmcs.h>
41 #include <asm/hvm/vmx/cpu.h>
42 #include <asm/shadow.h>
43 #if CONFIG_PAGING_LEVELS >= 3
44 #include <asm/shadow_64.h>
45 #endif
46 #include <public/sched.h>
47 #include <public/hvm/ioreq.h>
48 #include <asm/hvm/vpic.h>
49 #include <asm/hvm/vlapic.h>
51 static unsigned long trace_values[NR_CPUS][5];
52 #define TRACE_VMEXIT(index,value) trace_values[smp_processor_id()][index]=value
54 static void vmx_ctxt_switch_from(struct vcpu *v);
55 static void vmx_ctxt_switch_to(struct vcpu *v);
57 static int vmx_initialize_guest_resources(struct vcpu *v)
58 {
59 struct domain *d = v->domain;
60 struct vcpu *vc;
61 void *io_bitmap_a, *io_bitmap_b;
62 int rc;
64 v->arch.schedule_tail = arch_vmx_do_launch;
65 v->arch.ctxt_switch_from = vmx_ctxt_switch_from;
66 v->arch.ctxt_switch_to = vmx_ctxt_switch_to;
68 if ( v->vcpu_id != 0 )
69 return 1;
71 for_each_vcpu ( d, vc )
72 {
73 /* Initialize monitor page table */
74 vc->arch.monitor_table = pagetable_null();
76 memset(&vc->arch.hvm_vmx, 0, sizeof(struct arch_vmx_struct));
78 if ( (rc = vmx_create_vmcs(vc)) != 0 )
79 {
80 DPRINTK("Failed to create VMCS for vcpu %d: err=%d.\n",
81 vc->vcpu_id, rc);
82 return 0;
83 }
85 spin_lock_init(&vc->arch.hvm_vmx.vmcs_lock);
87 if ( (io_bitmap_a = alloc_xenheap_pages(IO_BITMAP_ORDER)) == NULL )
88 {
89 DPRINTK("Failed to allocate io bitmap b for vcpu %d.\n",
90 vc->vcpu_id);
91 return 0;
92 }
94 if ( (io_bitmap_b = alloc_xenheap_pages(IO_BITMAP_ORDER)) == NULL )
95 {
96 DPRINTK("Failed to allocate io bitmap b for vcpu %d.\n",
97 vc->vcpu_id);
98 return 0;
99 }
101 memset(io_bitmap_a, 0xff, 0x1000);
102 memset(io_bitmap_b, 0xff, 0x1000);
104 /* don't bother debug port access */
105 clear_bit(PC_DEBUG_PORT, io_bitmap_a);
107 vc->arch.hvm_vmx.io_bitmap_a = io_bitmap_a;
108 vc->arch.hvm_vmx.io_bitmap_b = io_bitmap_b;
109 }
111 /*
112 * Required to do this once per domain XXX todo: add a seperate function
113 * to do these.
114 */
115 memset(&d->shared_info->evtchn_mask[0], 0xff,
116 sizeof(d->shared_info->evtchn_mask));
118 /* Put the domain in shadow mode even though we're going to be using
119 * the shared 1:1 page table initially. It shouldn't hurt */
120 shadow_mode_enable(
121 d, SHM_enable|SHM_refcounts|SHM_translate|SHM_external|SHM_wr_pt_pte);
123 return 1;
124 }
126 static void vmx_relinquish_guest_resources(struct domain *d)
127 {
128 struct vcpu *v;
130 for_each_vcpu ( d, v )
131 {
132 vmx_destroy_vmcs(v);
133 if ( !test_bit(_VCPUF_initialised, &v->vcpu_flags) )
134 continue;
135 free_monitor_pagetable(v);
136 kill_timer(&v->arch.hvm_vmx.hlt_timer);
137 if ( hvm_apic_support(v->domain) && (VLAPIC(v) != NULL) )
138 {
139 kill_timer(&VLAPIC(v)->vlapic_timer);
140 xfree(VLAPIC(v));
141 }
142 }
144 kill_timer(&d->arch.hvm_domain.pl_time.periodic_tm.timer);
146 if ( d->arch.hvm_domain.shared_page_va )
147 unmap_domain_page_global(
148 (void *)d->arch.hvm_domain.shared_page_va);
150 shadow_direct_map_clean(d);
151 }
153 #ifdef __x86_64__
155 static struct vmx_msr_state percpu_msr[NR_CPUS];
157 static u32 msr_data_index[VMX_MSR_COUNT] =
158 {
159 MSR_LSTAR, MSR_STAR, MSR_CSTAR,
160 MSR_SYSCALL_MASK, MSR_EFER,
161 };
163 static void vmx_save_segments(struct vcpu *v)
164 {
165 rdmsrl(MSR_SHADOW_GS_BASE, v->arch.hvm_vmx.msr_content.shadow_gs);
166 }
168 /*
169 * To avoid MSR save/restore at every VM exit/entry time, we restore
170 * the x86_64 specific MSRs at domain switch time. Since those MSRs are
171 * are not modified once set for generic domains, we don't save them,
172 * but simply reset them to the values set at percpu_traps_init().
173 */
174 static void vmx_load_msrs(void)
175 {
176 struct vmx_msr_state *host_state = &percpu_msr[smp_processor_id()];
177 int i;
179 while ( host_state->flags )
180 {
181 i = find_first_set_bit(host_state->flags);
182 wrmsrl(msr_data_index[i], host_state->msr_items[i]);
183 clear_bit(i, &host_state->flags);
184 }
185 }
187 static void vmx_save_init_msrs(void)
188 {
189 struct vmx_msr_state *host_state = &percpu_msr[smp_processor_id()];
190 int i;
192 for ( i = 0; i < VMX_MSR_COUNT; i++ )
193 rdmsrl(msr_data_index[i], host_state->msr_items[i]);
194 }
196 #define CASE_READ_MSR(address) \
197 case MSR_ ## address: \
198 msr_content = msr->msr_items[VMX_INDEX_MSR_ ## address]; \
199 break
201 #define CASE_WRITE_MSR(address) \
202 case MSR_ ## address: \
203 { \
204 msr->msr_items[VMX_INDEX_MSR_ ## address] = msr_content; \
205 if (!test_bit(VMX_INDEX_MSR_ ## address, &msr->flags)) { \
206 set_bit(VMX_INDEX_MSR_ ## address, &msr->flags); \
207 } \
208 wrmsrl(MSR_ ## address, msr_content); \
209 set_bit(VMX_INDEX_MSR_ ## address, &host_state->flags); \
210 } \
211 break
213 #define IS_CANO_ADDRESS(add) 1
214 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
215 {
216 u64 msr_content = 0;
217 struct vcpu *v = current;
218 struct vmx_msr_state *msr = &v->arch.hvm_vmx.msr_content;
220 switch ( regs->ecx ) {
221 case MSR_EFER:
222 HVM_DBG_LOG(DBG_LEVEL_2, "EFER msr_content 0x%"PRIx64, msr_content);
223 msr_content = msr->msr_items[VMX_INDEX_MSR_EFER];
225 /* the following code may be not needed */
226 if ( test_bit(VMX_CPU_STATE_LME_ENABLED, &v->arch.hvm_vmx.cpu_state) )
227 msr_content |= EFER_LME;
228 else
229 msr_content &= ~EFER_LME;
231 if ( VMX_LONG_GUEST(v) )
232 msr_content |= EFER_LMA;
233 else
234 msr_content &= ~EFER_LMA;
235 break;
237 case MSR_FS_BASE:
238 if ( !(VMX_LONG_GUEST(v)) )
239 /* XXX should it be GP fault */
240 domain_crash_synchronous();
242 __vmread(GUEST_FS_BASE, &msr_content);
243 break;
245 case MSR_GS_BASE:
246 if ( !(VMX_LONG_GUEST(v)) )
247 domain_crash_synchronous();
249 __vmread(GUEST_GS_BASE, &msr_content);
250 break;
252 case MSR_SHADOW_GS_BASE:
253 msr_content = msr->shadow_gs;
254 break;
256 CASE_READ_MSR(STAR);
257 CASE_READ_MSR(LSTAR);
258 CASE_READ_MSR(CSTAR);
259 CASE_READ_MSR(SYSCALL_MASK);
261 default:
262 return 0;
263 }
265 HVM_DBG_LOG(DBG_LEVEL_2, "msr_content: 0x%"PRIx64, msr_content);
267 regs->eax = msr_content & 0xffffffff;
268 regs->edx = msr_content >> 32;
270 return 1;
271 }
273 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
274 {
275 u64 msr_content = regs->eax | ((u64)regs->edx << 32);
276 struct vcpu *v = current;
277 struct vmx_msr_state *msr = &v->arch.hvm_vmx.msr_content;
278 struct vmx_msr_state *host_state = &percpu_msr[smp_processor_id()];
280 HVM_DBG_LOG(DBG_LEVEL_1, "msr 0x%lx msr_content 0x%"PRIx64"\n",
281 (unsigned long)regs->ecx, msr_content);
283 switch ( regs->ecx ) {
284 case MSR_EFER:
285 /* offending reserved bit will cause #GP */
286 if ( msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE) )
287 {
288 printk("trying to set reserved bit in EFER\n");
289 vmx_inject_exception(v, TRAP_gp_fault, 0);
290 return 0;
291 }
293 /* LME: 0 -> 1 */
294 if ( msr_content & EFER_LME &&
295 !test_bit(VMX_CPU_STATE_LME_ENABLED, &v->arch.hvm_vmx.cpu_state) )
296 {
297 if ( vmx_paging_enabled(v) ||
298 !test_bit(VMX_CPU_STATE_PAE_ENABLED,
299 &v->arch.hvm_vmx.cpu_state) )
300 {
301 printk("trying to set LME bit when "
302 "in paging mode or PAE bit is not set\n");
303 vmx_inject_exception(v, TRAP_gp_fault, 0);
304 return 0;
305 }
307 set_bit(VMX_CPU_STATE_LME_ENABLED, &v->arch.hvm_vmx.cpu_state);
308 }
310 msr->msr_items[VMX_INDEX_MSR_EFER] = msr_content;
311 break;
313 case MSR_FS_BASE:
314 case MSR_GS_BASE:
315 if ( !(VMX_LONG_GUEST(v)) )
316 domain_crash_synchronous();
318 if ( !IS_CANO_ADDRESS(msr_content) )
319 {
320 HVM_DBG_LOG(DBG_LEVEL_1, "Not cano address of msr write\n");
321 vmx_inject_exception(v, TRAP_gp_fault, 0);
322 return 0;
323 }
325 if ( regs->ecx == MSR_FS_BASE )
326 __vmwrite(GUEST_FS_BASE, msr_content);
327 else
328 __vmwrite(GUEST_GS_BASE, msr_content);
330 break;
332 case MSR_SHADOW_GS_BASE:
333 if ( !(VMX_LONG_GUEST(v)) )
334 domain_crash_synchronous();
336 v->arch.hvm_vmx.msr_content.shadow_gs = msr_content;
337 wrmsrl(MSR_SHADOW_GS_BASE, msr_content);
338 break;
340 CASE_WRITE_MSR(STAR);
341 CASE_WRITE_MSR(LSTAR);
342 CASE_WRITE_MSR(CSTAR);
343 CASE_WRITE_MSR(SYSCALL_MASK);
345 default:
346 return 0;
347 }
349 return 1;
350 }
352 static void vmx_restore_msrs(struct vcpu *v)
353 {
354 int i = 0;
355 struct vmx_msr_state *guest_state;
356 struct vmx_msr_state *host_state;
357 unsigned long guest_flags ;
359 guest_state = &v->arch.hvm_vmx.msr_content;;
360 host_state = &percpu_msr[smp_processor_id()];
362 wrmsrl(MSR_SHADOW_GS_BASE, guest_state->shadow_gs);
363 guest_flags = guest_state->flags;
364 if (!guest_flags)
365 return;
367 while (guest_flags){
368 i = find_first_set_bit(guest_flags);
370 HVM_DBG_LOG(DBG_LEVEL_2,
371 "restore guest's index %d msr %lx with %lx\n",
372 i, (unsigned long)msr_data_index[i],
373 (unsigned long)guest_state->msr_items[i]);
374 set_bit(i, &host_state->flags);
375 wrmsrl(msr_data_index[i], guest_state->msr_items[i]);
376 clear_bit(i, &guest_flags);
377 }
378 }
380 #else /* __i386__ */
382 #define vmx_save_segments(v) ((void)0)
383 #define vmx_load_msrs() ((void)0)
384 #define vmx_restore_msrs(v) ((void)0)
385 #define vmx_save_init_msrs() ((void)0)
387 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
388 {
389 return 0;
390 }
392 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
393 {
394 return 0;
395 }
397 #endif /* __i386__ */
399 #define loaddebug(_v,_reg) \
400 __asm__ __volatile__ ("mov %0,%%db" #_reg : : "r" ((_v)->debugreg[_reg]))
401 #define savedebug(_v,_reg) \
402 __asm__ __volatile__ ("mov %%db" #_reg ",%0" : : "r" ((_v)->debugreg[_reg]))
404 static inline void vmx_save_dr(struct vcpu *v)
405 {
406 if ( v->arch.hvm_vcpu.flag_dr_dirty )
407 {
408 savedebug(&v->arch.guest_context, 0);
409 savedebug(&v->arch.guest_context, 1);
410 savedebug(&v->arch.guest_context, 2);
411 savedebug(&v->arch.guest_context, 3);
412 savedebug(&v->arch.guest_context, 6);
414 v->arch.hvm_vcpu.flag_dr_dirty = 0;
416 v->arch.hvm_vcpu.u.vmx.exec_control |= CPU_BASED_MOV_DR_EXITING;
417 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
418 v->arch.hvm_vcpu.u.vmx.exec_control);
419 }
420 }
422 static inline void __restore_debug_registers(struct vcpu *v)
423 {
424 loaddebug(&v->arch.guest_context, 0);
425 loaddebug(&v->arch.guest_context, 1);
426 loaddebug(&v->arch.guest_context, 2);
427 loaddebug(&v->arch.guest_context, 3);
428 /* No 4 and 5 */
429 loaddebug(&v->arch.guest_context, 6);
430 /* DR7 is loaded from the vmcs. */
431 }
433 /*
434 * DR7 is saved and restored on every vmexit. Other debug registers only
435 * need to be restored if their value is going to affect execution -- i.e.,
436 * if one of the breakpoints is enabled. So mask out all bits that don't
437 * enable some breakpoint functionality.
438 *
439 * This is in part necessary because bit 10 of DR7 is hardwired to 1, so a
440 * simple if( guest_dr7 ) will always return true. As long as we're masking,
441 * we might as well do it right.
442 */
443 #define DR7_ACTIVE_MASK 0xff
445 static inline void vmx_restore_dr(struct vcpu *v)
446 {
447 unsigned long guest_dr7;
449 __vmread(GUEST_DR7, &guest_dr7);
451 /* Assumes guest does not have DR access at time of context switch. */
452 if ( unlikely(guest_dr7 & DR7_ACTIVE_MASK) )
453 __restore_debug_registers(v);
454 }
456 static void vmx_freeze_time(struct vcpu *v)
457 {
458 struct periodic_time *pt=&v->domain->arch.hvm_domain.pl_time.periodic_tm;
460 if ( pt->enabled && pt->first_injected && !v->arch.hvm_vcpu.guest_time ) {
461 v->arch.hvm_vcpu.guest_time = hvm_get_guest_time(v);
462 stop_timer(&(pt->timer));
463 }
464 }
466 static void vmx_ctxt_switch_from(struct vcpu *v)
467 {
468 vmx_freeze_time(v);
469 vmx_save_segments(v);
470 vmx_load_msrs();
471 vmx_save_dr(v);
472 }
474 static void vmx_ctxt_switch_to(struct vcpu *v)
475 {
476 vmx_restore_msrs(v);
477 vmx_restore_dr(v);
478 }
480 void stop_vmx(void)
481 {
482 if (read_cr4() & X86_CR4_VMXE)
483 __vmxoff();
484 }
486 void vmx_migrate_timers(struct vcpu *v)
487 {
488 struct periodic_time *pt = &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
490 if ( pt->enabled ) {
491 migrate_timer(&pt->timer, v->processor);
492 migrate_timer(&v->arch.hvm_vmx.hlt_timer, v->processor);
493 }
494 if ( hvm_apic_support(v->domain) && VLAPIC(v))
495 migrate_timer(&(VLAPIC(v)->vlapic_timer), v->processor);
496 }
498 static void vmx_store_cpu_guest_regs(
499 struct vcpu *v, struct cpu_user_regs *regs, unsigned long *crs)
500 {
501 vmx_vmcs_enter(v);
503 if ( regs != NULL )
504 {
505 __vmread(GUEST_RFLAGS, &regs->eflags);
506 __vmread(GUEST_SS_SELECTOR, &regs->ss);
507 __vmread(GUEST_CS_SELECTOR, &regs->cs);
508 __vmread(GUEST_DS_SELECTOR, &regs->ds);
509 __vmread(GUEST_ES_SELECTOR, &regs->es);
510 __vmread(GUEST_GS_SELECTOR, &regs->gs);
511 __vmread(GUEST_FS_SELECTOR, &regs->fs);
512 __vmread(GUEST_RIP, &regs->eip);
513 __vmread(GUEST_RSP, &regs->esp);
514 }
516 if ( crs != NULL )
517 {
518 __vmread(CR0_READ_SHADOW, &crs[0]);
519 __vmread(GUEST_CR3, &crs[3]);
520 __vmread(CR4_READ_SHADOW, &crs[4]);
521 }
523 vmx_vmcs_exit(v);
524 }
526 /*
527 * The VMX spec (section 4.3.1.2, Checks on Guest Segment
528 * Registers) says that virtual-8086 mode guests' segment
529 * base-address fields in the VMCS must be equal to their
530 * corresponding segment selector field shifted right by
531 * four bits upon vmentry.
532 *
533 * This function (called only for VM86-mode guests) fixes
534 * the bases to be consistent with the selectors in regs
535 * if they're not already. Without this, we can fail the
536 * vmentry check mentioned above.
537 */
538 static void fixup_vm86_seg_bases(struct cpu_user_regs *regs)
539 {
540 int err = 0;
541 unsigned long base;
543 err |= __vmread(GUEST_ES_BASE, &base);
544 if (regs->es << 4 != base)
545 err |= __vmwrite(GUEST_ES_BASE, regs->es << 4);
546 err |= __vmread(GUEST_CS_BASE, &base);
547 if (regs->cs << 4 != base)
548 err |= __vmwrite(GUEST_CS_BASE, regs->cs << 4);
549 err |= __vmread(GUEST_SS_BASE, &base);
550 if (regs->ss << 4 != base)
551 err |= __vmwrite(GUEST_SS_BASE, regs->ss << 4);
552 err |= __vmread(GUEST_DS_BASE, &base);
553 if (regs->ds << 4 != base)
554 err |= __vmwrite(GUEST_DS_BASE, regs->ds << 4);
555 err |= __vmread(GUEST_FS_BASE, &base);
556 if (regs->fs << 4 != base)
557 err |= __vmwrite(GUEST_FS_BASE, regs->fs << 4);
558 err |= __vmread(GUEST_GS_BASE, &base);
559 if (regs->gs << 4 != base)
560 err |= __vmwrite(GUEST_GS_BASE, regs->gs << 4);
562 BUG_ON(err);
563 }
565 void vmx_load_cpu_guest_regs(struct vcpu *v, struct cpu_user_regs *regs)
566 {
567 vmx_vmcs_enter(v);
569 __vmwrite(GUEST_SS_SELECTOR, regs->ss);
570 __vmwrite(GUEST_DS_SELECTOR, regs->ds);
571 __vmwrite(GUEST_ES_SELECTOR, regs->es);
572 __vmwrite(GUEST_GS_SELECTOR, regs->gs);
573 __vmwrite(GUEST_FS_SELECTOR, regs->fs);
575 __vmwrite(GUEST_RSP, regs->esp);
577 __vmwrite(GUEST_RFLAGS, regs->eflags);
578 if (regs->eflags & EF_TF)
579 __vm_set_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
580 else
581 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
582 if (regs->eflags & EF_VM)
583 fixup_vm86_seg_bases(regs);
585 __vmwrite(GUEST_CS_SELECTOR, regs->cs);
586 __vmwrite(GUEST_RIP, regs->eip);
588 vmx_vmcs_exit(v);
589 }
591 int vmx_realmode(struct vcpu *v)
592 {
593 unsigned long rflags;
595 __vmread(GUEST_RFLAGS, &rflags);
596 return rflags & X86_EFLAGS_VM;
597 }
599 int vmx_instruction_length(struct vcpu *v)
600 {
601 unsigned long inst_len;
603 if (__vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len))
604 return 0;
605 return inst_len;
606 }
608 unsigned long vmx_get_ctrl_reg(struct vcpu *v, unsigned int num)
609 {
610 switch ( num )
611 {
612 case 0:
613 return v->arch.hvm_vmx.cpu_cr0;
614 case 2:
615 return v->arch.hvm_vmx.cpu_cr2;
616 case 3:
617 return v->arch.hvm_vmx.cpu_cr3;
618 default:
619 BUG();
620 }
621 return 0; /* dummy */
622 }
624 /* SMP VMX guest support */
625 void vmx_init_ap_context(struct vcpu_guest_context *ctxt,
626 int vcpuid, int trampoline_vector)
627 {
628 int i;
630 memset(ctxt, 0, sizeof(*ctxt));
632 /*
633 * Initial register values:
634 */
635 ctxt->user_regs.eip = VMXASSIST_BASE;
636 ctxt->user_regs.edx = vcpuid;
637 ctxt->user_regs.ebx = trampoline_vector;
639 ctxt->flags = VGCF_HVM_GUEST;
641 /* Virtual IDT is empty at start-of-day. */
642 for ( i = 0; i < 256; i++ )
643 {
644 ctxt->trap_ctxt[i].vector = i;
645 ctxt->trap_ctxt[i].cs = FLAT_KERNEL_CS;
646 }
648 /* No callback handlers. */
649 #if defined(__i386__)
650 ctxt->event_callback_cs = FLAT_KERNEL_CS;
651 ctxt->failsafe_callback_cs = FLAT_KERNEL_CS;
652 #endif
653 }
655 void do_nmi(struct cpu_user_regs *);
657 static int check_vmx_controls(u32 ctrls, u32 msr)
658 {
659 u32 vmx_msr_low, vmx_msr_high;
661 rdmsr(msr, vmx_msr_low, vmx_msr_high);
662 if ( (ctrls < vmx_msr_low) || (ctrls > vmx_msr_high) )
663 {
664 printk("Insufficient VMX capability 0x%x, "
665 "msr=0x%x,low=0x%8x,high=0x%x\n",
666 ctrls, msr, vmx_msr_low, vmx_msr_high);
667 return 0;
668 }
669 return 1;
670 }
672 int start_vmx(void)
673 {
674 u32 eax, edx;
675 struct vmcs_struct *vmcs;
677 /*
678 * Xen does not fill x86_capability words except 0.
679 */
680 boot_cpu_data.x86_capability[4] = cpuid_ecx(1);
682 if (!(test_bit(X86_FEATURE_VMXE, &boot_cpu_data.x86_capability)))
683 return 0;
685 rdmsr(IA32_FEATURE_CONTROL_MSR, eax, edx);
687 if ( eax & IA32_FEATURE_CONTROL_MSR_LOCK )
688 {
689 if ( (eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON) == 0x0 )
690 {
691 printk("VMX disabled by Feature Control MSR.\n");
692 return 0;
693 }
694 }
695 else
696 {
697 wrmsr(IA32_FEATURE_CONTROL_MSR,
698 IA32_FEATURE_CONTROL_MSR_LOCK |
699 IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON, 0);
700 }
702 if ( !check_vmx_controls(MONITOR_PIN_BASED_EXEC_CONTROLS,
703 MSR_IA32_VMX_PINBASED_CTLS_MSR) )
704 return 0;
705 if ( !check_vmx_controls(MONITOR_CPU_BASED_EXEC_CONTROLS,
706 MSR_IA32_VMX_PROCBASED_CTLS_MSR) )
707 return 0;
708 if ( !check_vmx_controls(MONITOR_VM_EXIT_CONTROLS,
709 MSR_IA32_VMX_EXIT_CTLS_MSR) )
710 return 0;
711 if ( !check_vmx_controls(MONITOR_VM_ENTRY_CONTROLS,
712 MSR_IA32_VMX_ENTRY_CTLS_MSR) )
713 return 0;
715 set_in_cr4(X86_CR4_VMXE);
717 vmx_init_vmcs_config();
719 if ( (vmcs = vmx_alloc_host_vmcs()) == NULL )
720 {
721 printk("Failed to allocate host VMCS\n");
722 return 0;
723 }
725 if ( __vmxon(virt_to_maddr(vmcs)) )
726 {
727 printk("VMXON failed\n");
728 vmx_free_host_vmcs(vmcs);
729 return 0;
730 }
732 printk("VMXON is done\n");
734 vmx_save_init_msrs();
736 /* Setup HVM interfaces */
737 hvm_funcs.disable = stop_vmx;
739 hvm_funcs.initialize_guest_resources = vmx_initialize_guest_resources;
740 hvm_funcs.relinquish_guest_resources = vmx_relinquish_guest_resources;
742 hvm_funcs.store_cpu_guest_regs = vmx_store_cpu_guest_regs;
743 hvm_funcs.load_cpu_guest_regs = vmx_load_cpu_guest_regs;
745 hvm_funcs.realmode = vmx_realmode;
746 hvm_funcs.paging_enabled = vmx_paging_enabled;
747 hvm_funcs.instruction_length = vmx_instruction_length;
748 hvm_funcs.get_guest_ctrl_reg = vmx_get_ctrl_reg;
750 hvm_funcs.init_ap_context = vmx_init_ap_context;
752 hvm_enabled = 1;
754 return 1;
755 }
757 /*
758 * Not all cases receive valid value in the VM-exit instruction length field.
759 */
760 #define __get_instruction_length(len) \
761 __vmread(VM_EXIT_INSTRUCTION_LEN, &(len)); \
762 if ((len) < 1 || (len) > 15) \
763 __hvm_bug(&regs);
765 static void inline __update_guest_eip(unsigned long inst_len)
766 {
767 unsigned long current_eip;
769 __vmread(GUEST_RIP, &current_eip);
770 __vmwrite(GUEST_RIP, current_eip + inst_len);
771 __vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0);
772 }
775 static int vmx_do_page_fault(unsigned long va, struct cpu_user_regs *regs)
776 {
777 unsigned long gpa; /* FIXME: PAE */
778 int result;
780 #if 0 /* keep for debugging */
781 {
782 unsigned long eip;
784 __vmread(GUEST_RIP, &eip);
785 HVM_DBG_LOG(DBG_LEVEL_VMMU,
786 "vmx_do_page_fault = 0x%lx, eip = %lx, error_code = %lx",
787 va, eip, (unsigned long)regs->error_code);
788 }
789 #endif
791 if ( !vmx_paging_enabled(current) )
792 {
793 /* construct 1-to-1 direct mapping */
794 if ( shadow_direct_map_fault(va, regs) )
795 return 1;
797 handle_mmio(va, va);
798 TRACE_VMEXIT (2,2);
799 return 1;
800 }
801 gpa = gva_to_gpa(va);
803 /* Use 1:1 page table to identify MMIO address space */
804 if ( mmio_space(gpa) ){
805 struct vcpu *v = current;
806 /* No support for APIC */
807 if (!hvm_apic_support(v->domain) && gpa >= 0xFEC00000) {
808 u32 inst_len;
809 __vmread(VM_EXIT_INSTRUCTION_LEN, &(inst_len));
810 __update_guest_eip(inst_len);
811 return 1;
812 }
813 TRACE_VMEXIT (2,2);
814 handle_mmio(va, gpa);
815 return 1;
816 }
818 result = shadow_fault(va, regs);
819 TRACE_VMEXIT (2,result);
820 #if 0
821 if ( !result )
822 {
823 __vmread(GUEST_RIP, &eip);
824 printk("vmx pgfault to guest va=%lx eip=%lx\n", va, eip);
825 }
826 #endif
828 return result;
829 }
831 static void vmx_do_no_device_fault(void)
832 {
833 unsigned long cr0;
834 struct vcpu *v = current;
836 setup_fpu(current);
837 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
839 /* Disable TS in guest CR0 unless the guest wants the exception too. */
840 __vmread_vcpu(v, CR0_READ_SHADOW, &cr0);
841 if ( !(cr0 & X86_CR0_TS) )
842 {
843 __vmread_vcpu(v, GUEST_CR0, &cr0);
844 cr0 &= ~X86_CR0_TS;
845 __vmwrite(GUEST_CR0, cr0);
846 }
847 }
849 #define bitmaskof(idx) (1U << ((idx)&31))
850 static void vmx_vmexit_do_cpuid(struct cpu_user_regs *regs)
851 {
852 unsigned int input = (unsigned int)regs->eax;
853 unsigned int count = (unsigned int)regs->ecx;
854 unsigned int eax, ebx, ecx, edx;
855 unsigned long eip;
856 struct vcpu *v = current;
858 __vmread(GUEST_RIP, &eip);
860 HVM_DBG_LOG(DBG_LEVEL_3, "(eax) 0x%08lx, (ebx) 0x%08lx, "
861 "(ecx) 0x%08lx, (edx) 0x%08lx, (esi) 0x%08lx, (edi) 0x%08lx",
862 (unsigned long)regs->eax, (unsigned long)regs->ebx,
863 (unsigned long)regs->ecx, (unsigned long)regs->edx,
864 (unsigned long)regs->esi, (unsigned long)regs->edi);
866 if ( input == CPUID_LEAF_0x4 )
867 {
868 cpuid_count(input, count, &eax, &ebx, &ecx, &edx);
869 eax &= NUM_CORES_RESET_MASK;
870 }
871 else if ( !cpuid_hypervisor_leaves(input, &eax, &ebx, &ecx, &edx) )
872 {
873 cpuid(input, &eax, &ebx, &ecx, &edx);
875 if ( input == CPUID_LEAF_0x1 )
876 {
877 /* mask off reserved bits */
878 ecx &= ~VMX_VCPU_CPUID_L1_ECX_RESERVED;
880 if ( !hvm_apic_support(v->domain) ||
881 !vlapic_global_enabled((VLAPIC(v))) )
882 {
883 /* Since the apic is disabled, avoid any
884 confusion about SMP cpus being available */
886 clear_bit(X86_FEATURE_APIC, &edx);
887 }
889 #if CONFIG_PAGING_LEVELS < 3
890 edx &= ~(bitmaskof(X86_FEATURE_PAE) |
891 bitmaskof(X86_FEATURE_PSE) |
892 bitmaskof(X86_FEATURE_PSE36));
893 #else
894 if ( v->domain->arch.ops->guest_paging_levels == PAGING_L2 )
895 {
896 if ( v->domain->arch.hvm_domain.pae_enabled )
897 clear_bit(X86_FEATURE_PSE36, &edx);
898 else
899 {
900 clear_bit(X86_FEATURE_PAE, &edx);
901 clear_bit(X86_FEATURE_PSE, &edx);
902 clear_bit(X86_FEATURE_PSE36, &edx);
903 }
904 }
905 #endif
907 ebx &= NUM_THREADS_RESET_MASK;
909 /* Unsupportable for virtualised CPUs. */
910 ecx &= ~(bitmaskof(X86_FEATURE_VMXE) |
911 bitmaskof(X86_FEATURE_EST) |
912 bitmaskof(X86_FEATURE_TM2) |
913 bitmaskof(X86_FEATURE_CID) |
914 bitmaskof(X86_FEATURE_MWAIT) );
916 edx &= ~( bitmaskof(X86_FEATURE_HT) |
917 bitmaskof(X86_FEATURE_MCA) |
918 bitmaskof(X86_FEATURE_MCE) |
919 bitmaskof(X86_FEATURE_ACPI) |
920 bitmaskof(X86_FEATURE_ACC) );
921 }
922 else if ( ( input == CPUID_LEAF_0x6 )
923 || ( input == CPUID_LEAF_0x9 )
924 || ( input == CPUID_LEAF_0xA ))
925 {
926 eax = ebx = ecx = edx = 0x0;
927 }
928 #ifdef __i386__
929 else if ( input == CPUID_LEAF_0x80000001 )
930 {
931 clear_bit(X86_FEATURE_LAHF_LM & 31, &ecx);
933 clear_bit(X86_FEATURE_LM & 31, &edx);
934 clear_bit(X86_FEATURE_SYSCALL & 31, &edx);
935 }
936 #endif
937 }
939 regs->eax = (unsigned long) eax;
940 regs->ebx = (unsigned long) ebx;
941 regs->ecx = (unsigned long) ecx;
942 regs->edx = (unsigned long) edx;
944 HVM_DBG_LOG(DBG_LEVEL_3, "eip@%lx, input: 0x%lx, "
945 "output: eax = 0x%08lx, ebx = 0x%08lx, "
946 "ecx = 0x%08lx, edx = 0x%08lx",
947 (unsigned long)eip, (unsigned long)input,
948 (unsigned long)eax, (unsigned long)ebx,
949 (unsigned long)ecx, (unsigned long)edx);
950 }
952 #define CASE_GET_REG_P(REG, reg) \
953 case REG_ ## REG: reg_p = (unsigned long *)&(regs->reg); break
955 #ifdef __i386__
956 #define CASE_EXTEND_GET_REG_P
957 #else
958 #define CASE_EXTEND_GET_REG_P \
959 CASE_GET_REG_P(R8, r8); \
960 CASE_GET_REG_P(R9, r9); \
961 CASE_GET_REG_P(R10, r10); \
962 CASE_GET_REG_P(R11, r11); \
963 CASE_GET_REG_P(R12, r12); \
964 CASE_GET_REG_P(R13, r13); \
965 CASE_GET_REG_P(R14, r14); \
966 CASE_GET_REG_P(R15, r15)
967 #endif
969 static void vmx_dr_access(unsigned long exit_qualification,
970 struct cpu_user_regs *regs)
971 {
972 struct vcpu *v = current;
974 v->arch.hvm_vcpu.flag_dr_dirty = 1;
976 /* We could probably be smarter about this */
977 __restore_debug_registers(v);
979 /* Allow guest direct access to DR registers */
980 v->arch.hvm_vcpu.u.vmx.exec_control &= ~CPU_BASED_MOV_DR_EXITING;
981 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
982 v->arch.hvm_vcpu.u.vmx.exec_control);
983 }
985 /*
986 * Invalidate the TLB for va. Invalidate the shadow page corresponding
987 * the address va.
988 */
989 static void vmx_vmexit_do_invlpg(unsigned long va)
990 {
991 unsigned long eip;
992 struct vcpu *v = current;
994 __vmread(GUEST_RIP, &eip);
996 HVM_DBG_LOG(DBG_LEVEL_VMMU, "vmx_vmexit_do_invlpg: eip=%lx, va=%lx",
997 eip, va);
999 /*
1000 * We do the safest things first, then try to update the shadow
1001 * copying from guest
1002 */
1003 shadow_invlpg(v, va);
1006 static int check_for_null_selector(unsigned long eip)
1008 unsigned char inst[MAX_INST_LEN];
1009 unsigned long sel;
1010 int i, inst_len;
1011 int inst_copy_from_guest(unsigned char *, unsigned long, int);
1013 __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
1014 memset(inst, 0, MAX_INST_LEN);
1015 if (inst_copy_from_guest(inst, eip, inst_len) != inst_len) {
1016 printf("check_for_null_selector: get guest instruction failed\n");
1017 domain_crash_synchronous();
1020 for (i = 0; i < inst_len; i++) {
1021 switch (inst[i]) {
1022 case 0xf3: /* REPZ */
1023 case 0xf2: /* REPNZ */
1024 case 0xf0: /* LOCK */
1025 case 0x66: /* data32 */
1026 case 0x67: /* addr32 */
1027 continue;
1028 case 0x2e: /* CS */
1029 __vmread(GUEST_CS_SELECTOR, &sel);
1030 break;
1031 case 0x36: /* SS */
1032 __vmread(GUEST_SS_SELECTOR, &sel);
1033 break;
1034 case 0x26: /* ES */
1035 __vmread(GUEST_ES_SELECTOR, &sel);
1036 break;
1037 case 0x64: /* FS */
1038 __vmread(GUEST_FS_SELECTOR, &sel);
1039 break;
1040 case 0x65: /* GS */
1041 __vmread(GUEST_GS_SELECTOR, &sel);
1042 break;
1043 case 0x3e: /* DS */
1044 /* FALLTHROUGH */
1045 default:
1046 /* DS is the default */
1047 __vmread(GUEST_DS_SELECTOR, &sel);
1049 return sel == 0 ? 1 : 0;
1052 return 0;
1055 extern void send_pio_req(struct cpu_user_regs *regs, unsigned long port,
1056 unsigned long count, int size, long value,
1057 int dir, int pvalid);
1059 static void vmx_io_instruction(struct cpu_user_regs *regs,
1060 unsigned long exit_qualification, unsigned long inst_len)
1062 struct mmio_op *mmio_opp;
1063 unsigned long eip, cs, eflags;
1064 unsigned long port, size, dir;
1065 int vm86;
1067 mmio_opp = &current->arch.hvm_vcpu.mmio_op;
1068 mmio_opp->instr = INSTR_PIO;
1069 mmio_opp->flags = 0;
1071 __vmread(GUEST_RIP, &eip);
1072 __vmread(GUEST_CS_SELECTOR, &cs);
1073 __vmread(GUEST_RFLAGS, &eflags);
1074 vm86 = eflags & X86_EFLAGS_VM ? 1 : 0;
1076 HVM_DBG_LOG(DBG_LEVEL_IO,
1077 "vmx_io_instruction: vm86 %d, eip=%lx:%lx, "
1078 "exit_qualification = %lx",
1079 vm86, cs, eip, exit_qualification);
1081 if (test_bit(6, &exit_qualification))
1082 port = (exit_qualification >> 16) & 0xFFFF;
1083 else
1084 port = regs->edx & 0xffff;
1085 TRACE_VMEXIT(1, port);
1086 size = (exit_qualification & 7) + 1;
1087 dir = test_bit(3, &exit_qualification); /* direction */
1089 if (test_bit(4, &exit_qualification)) { /* string instruction */
1090 unsigned long addr, count = 1;
1091 int sign = regs->eflags & EF_DF ? -1 : 1;
1093 __vmread(GUEST_LINEAR_ADDRESS, &addr);
1095 /*
1096 * In protected mode, guest linear address is invalid if the
1097 * selector is null.
1098 */
1099 if (!vm86 && check_for_null_selector(eip))
1100 addr = dir == IOREQ_WRITE ? regs->esi : regs->edi;
1102 if (test_bit(5, &exit_qualification)) { /* "rep" prefix */
1103 mmio_opp->flags |= REPZ;
1104 count = vm86 ? regs->ecx & 0xFFFF : regs->ecx;
1107 /*
1108 * Handle string pio instructions that cross pages or that
1109 * are unaligned. See the comments in hvm_domain.c/handle_mmio()
1110 */
1111 if ((addr & PAGE_MASK) != ((addr + size - 1) & PAGE_MASK)) {
1112 unsigned long value = 0;
1114 mmio_opp->flags |= OVERLAP;
1115 if (dir == IOREQ_WRITE)
1116 hvm_copy(&value, addr, size, HVM_COPY_IN);
1117 send_pio_req(regs, port, 1, size, value, dir, 0);
1118 } else {
1119 if ((addr & PAGE_MASK) != ((addr + count * size - 1) & PAGE_MASK)) {
1120 if (sign > 0)
1121 count = (PAGE_SIZE - (addr & ~PAGE_MASK)) / size;
1122 else
1123 count = (addr & ~PAGE_MASK) / size;
1124 } else
1125 __update_guest_eip(inst_len);
1127 send_pio_req(regs, port, count, size, addr, dir, 1);
1129 } else {
1130 if (port == 0xe9 && dir == IOREQ_WRITE && size == 1)
1131 hvm_print_line(current, regs->eax); /* guest debug output */
1133 __update_guest_eip(inst_len);
1134 send_pio_req(regs, port, 1, size, regs->eax, dir, 0);
1138 int
1139 vmx_world_save(struct vcpu *v, struct vmx_assist_context *c)
1141 unsigned long inst_len;
1142 int error = 0;
1144 error |= __vmread(VM_EXIT_INSTRUCTION_LEN, &inst_len);
1145 error |= __vmread(GUEST_RIP, &c->eip);
1146 c->eip += inst_len; /* skip transition instruction */
1147 error |= __vmread(GUEST_RSP, &c->esp);
1148 error |= __vmread(GUEST_RFLAGS, &c->eflags);
1150 error |= __vmread(CR0_READ_SHADOW, &c->cr0);
1151 c->cr3 = v->arch.hvm_vmx.cpu_cr3;
1152 error |= __vmread(CR4_READ_SHADOW, &c->cr4);
1154 error |= __vmread(GUEST_IDTR_LIMIT, &c->idtr_limit);
1155 error |= __vmread(GUEST_IDTR_BASE, &c->idtr_base);
1157 error |= __vmread(GUEST_GDTR_LIMIT, &c->gdtr_limit);
1158 error |= __vmread(GUEST_GDTR_BASE, &c->gdtr_base);
1160 error |= __vmread(GUEST_CS_SELECTOR, &c->cs_sel);
1161 error |= __vmread(GUEST_CS_LIMIT, &c->cs_limit);
1162 error |= __vmread(GUEST_CS_BASE, &c->cs_base);
1163 error |= __vmread(GUEST_CS_AR_BYTES, &c->cs_arbytes.bytes);
1165 error |= __vmread(GUEST_DS_SELECTOR, &c->ds_sel);
1166 error |= __vmread(GUEST_DS_LIMIT, &c->ds_limit);
1167 error |= __vmread(GUEST_DS_BASE, &c->ds_base);
1168 error |= __vmread(GUEST_DS_AR_BYTES, &c->ds_arbytes.bytes);
1170 error |= __vmread(GUEST_ES_SELECTOR, &c->es_sel);
1171 error |= __vmread(GUEST_ES_LIMIT, &c->es_limit);
1172 error |= __vmread(GUEST_ES_BASE, &c->es_base);
1173 error |= __vmread(GUEST_ES_AR_BYTES, &c->es_arbytes.bytes);
1175 error |= __vmread(GUEST_SS_SELECTOR, &c->ss_sel);
1176 error |= __vmread(GUEST_SS_LIMIT, &c->ss_limit);
1177 error |= __vmread(GUEST_SS_BASE, &c->ss_base);
1178 error |= __vmread(GUEST_SS_AR_BYTES, &c->ss_arbytes.bytes);
1180 error |= __vmread(GUEST_FS_SELECTOR, &c->fs_sel);
1181 error |= __vmread(GUEST_FS_LIMIT, &c->fs_limit);
1182 error |= __vmread(GUEST_FS_BASE, &c->fs_base);
1183 error |= __vmread(GUEST_FS_AR_BYTES, &c->fs_arbytes.bytes);
1185 error |= __vmread(GUEST_GS_SELECTOR, &c->gs_sel);
1186 error |= __vmread(GUEST_GS_LIMIT, &c->gs_limit);
1187 error |= __vmread(GUEST_GS_BASE, &c->gs_base);
1188 error |= __vmread(GUEST_GS_AR_BYTES, &c->gs_arbytes.bytes);
1190 error |= __vmread(GUEST_TR_SELECTOR, &c->tr_sel);
1191 error |= __vmread(GUEST_TR_LIMIT, &c->tr_limit);
1192 error |= __vmread(GUEST_TR_BASE, &c->tr_base);
1193 error |= __vmread(GUEST_TR_AR_BYTES, &c->tr_arbytes.bytes);
1195 error |= __vmread(GUEST_LDTR_SELECTOR, &c->ldtr_sel);
1196 error |= __vmread(GUEST_LDTR_LIMIT, &c->ldtr_limit);
1197 error |= __vmread(GUEST_LDTR_BASE, &c->ldtr_base);
1198 error |= __vmread(GUEST_LDTR_AR_BYTES, &c->ldtr_arbytes.bytes);
1200 return !error;
1203 int
1204 vmx_world_restore(struct vcpu *v, struct vmx_assist_context *c)
1206 unsigned long mfn, old_cr4, old_base_mfn;
1207 int error = 0;
1209 error |= __vmwrite(GUEST_RIP, c->eip);
1210 error |= __vmwrite(GUEST_RSP, c->esp);
1211 error |= __vmwrite(GUEST_RFLAGS, c->eflags);
1213 error |= __vmwrite(CR0_READ_SHADOW, c->cr0);
1215 if (!vmx_paging_enabled(v)) {
1216 HVM_DBG_LOG(DBG_LEVEL_VMMU, "switching to vmxassist. use phys table");
1217 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->domain->arch.phys_table));
1218 goto skip_cr3;
1221 if (c->cr3 == v->arch.hvm_vmx.cpu_cr3) {
1222 /*
1223 * This is simple TLB flush, implying the guest has
1224 * removed some translation or changed page attributes.
1225 * We simply invalidate the shadow.
1226 */
1227 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1228 if (mfn != pagetable_get_pfn(v->arch.guest_table)) {
1229 printk("Invalid CR3 value=%x", c->cr3);
1230 domain_crash_synchronous();
1231 return 0;
1233 shadow_sync_all(v->domain);
1234 } else {
1235 /*
1236 * If different, make a shadow. Check if the PDBR is valid
1237 * first.
1238 */
1239 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 c->cr3 = %x", c->cr3);
1240 if ((c->cr3 >> PAGE_SHIFT) > v->domain->max_pages) {
1241 printk("Invalid CR3 value=%x", c->cr3);
1242 domain_crash_synchronous();
1243 return 0;
1245 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1246 if(!get_page(mfn_to_page(mfn), v->domain))
1247 return 0;
1248 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1249 v->arch.guest_table = pagetable_from_pfn(mfn);
1250 if (old_base_mfn)
1251 put_page(mfn_to_page(old_base_mfn));
1252 /*
1253 * arch.shadow_table should now hold the next CR3 for shadow
1254 */
1255 v->arch.hvm_vmx.cpu_cr3 = c->cr3;
1256 update_pagetables(v);
1257 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %x", c->cr3);
1258 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1261 skip_cr3:
1263 error |= __vmread(CR4_READ_SHADOW, &old_cr4);
1264 error |= __vmwrite(GUEST_CR4, (c->cr4 | VMX_CR4_HOST_MASK));
1265 error |= __vmwrite(CR4_READ_SHADOW, c->cr4);
1267 error |= __vmwrite(GUEST_IDTR_LIMIT, c->idtr_limit);
1268 error |= __vmwrite(GUEST_IDTR_BASE, c->idtr_base);
1270 error |= __vmwrite(GUEST_GDTR_LIMIT, c->gdtr_limit);
1271 error |= __vmwrite(GUEST_GDTR_BASE, c->gdtr_base);
1273 error |= __vmwrite(GUEST_CS_SELECTOR, c->cs_sel);
1274 error |= __vmwrite(GUEST_CS_LIMIT, c->cs_limit);
1275 error |= __vmwrite(GUEST_CS_BASE, c->cs_base);
1276 error |= __vmwrite(GUEST_CS_AR_BYTES, c->cs_arbytes.bytes);
1278 error |= __vmwrite(GUEST_DS_SELECTOR, c->ds_sel);
1279 error |= __vmwrite(GUEST_DS_LIMIT, c->ds_limit);
1280 error |= __vmwrite(GUEST_DS_BASE, c->ds_base);
1281 error |= __vmwrite(GUEST_DS_AR_BYTES, c->ds_arbytes.bytes);
1283 error |= __vmwrite(GUEST_ES_SELECTOR, c->es_sel);
1284 error |= __vmwrite(GUEST_ES_LIMIT, c->es_limit);
1285 error |= __vmwrite(GUEST_ES_BASE, c->es_base);
1286 error |= __vmwrite(GUEST_ES_AR_BYTES, c->es_arbytes.bytes);
1288 error |= __vmwrite(GUEST_SS_SELECTOR, c->ss_sel);
1289 error |= __vmwrite(GUEST_SS_LIMIT, c->ss_limit);
1290 error |= __vmwrite(GUEST_SS_BASE, c->ss_base);
1291 error |= __vmwrite(GUEST_SS_AR_BYTES, c->ss_arbytes.bytes);
1293 error |= __vmwrite(GUEST_FS_SELECTOR, c->fs_sel);
1294 error |= __vmwrite(GUEST_FS_LIMIT, c->fs_limit);
1295 error |= __vmwrite(GUEST_FS_BASE, c->fs_base);
1296 error |= __vmwrite(GUEST_FS_AR_BYTES, c->fs_arbytes.bytes);
1298 error |= __vmwrite(GUEST_GS_SELECTOR, c->gs_sel);
1299 error |= __vmwrite(GUEST_GS_LIMIT, c->gs_limit);
1300 error |= __vmwrite(GUEST_GS_BASE, c->gs_base);
1301 error |= __vmwrite(GUEST_GS_AR_BYTES, c->gs_arbytes.bytes);
1303 error |= __vmwrite(GUEST_TR_SELECTOR, c->tr_sel);
1304 error |= __vmwrite(GUEST_TR_LIMIT, c->tr_limit);
1305 error |= __vmwrite(GUEST_TR_BASE, c->tr_base);
1306 error |= __vmwrite(GUEST_TR_AR_BYTES, c->tr_arbytes.bytes);
1308 error |= __vmwrite(GUEST_LDTR_SELECTOR, c->ldtr_sel);
1309 error |= __vmwrite(GUEST_LDTR_LIMIT, c->ldtr_limit);
1310 error |= __vmwrite(GUEST_LDTR_BASE, c->ldtr_base);
1311 error |= __vmwrite(GUEST_LDTR_AR_BYTES, c->ldtr_arbytes.bytes);
1313 return !error;
1316 enum { VMX_ASSIST_INVOKE = 0, VMX_ASSIST_RESTORE };
1318 int
1319 vmx_assist(struct vcpu *v, int mode)
1321 struct vmx_assist_context c;
1322 u32 magic;
1323 u32 cp;
1325 /* make sure vmxassist exists (this is not an error) */
1326 if (!hvm_copy(&magic, VMXASSIST_MAGIC_OFFSET, sizeof(magic), HVM_COPY_IN))
1327 return 0;
1328 if (magic != VMXASSIST_MAGIC)
1329 return 0;
1331 switch (mode) {
1332 /*
1333 * Transfer control to vmxassist.
1334 * Store the current context in VMXASSIST_OLD_CONTEXT and load
1335 * the new VMXASSIST_NEW_CONTEXT context. This context was created
1336 * by vmxassist and will transfer control to it.
1337 */
1338 case VMX_ASSIST_INVOKE:
1339 /* save the old context */
1340 if (!hvm_copy(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp), HVM_COPY_IN))
1341 goto error;
1342 if (cp != 0) {
1343 if (!vmx_world_save(v, &c))
1344 goto error;
1345 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_OUT))
1346 goto error;
1349 /* restore the new context, this should activate vmxassist */
1350 if (!hvm_copy(&cp, VMXASSIST_NEW_CONTEXT, sizeof(cp), HVM_COPY_IN))
1351 goto error;
1352 if (cp != 0) {
1353 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_IN))
1354 goto error;
1355 if (!vmx_world_restore(v, &c))
1356 goto error;
1357 return 1;
1359 break;
1361 /*
1362 * Restore the VMXASSIST_OLD_CONTEXT that was saved by VMX_ASSIST_INVOKE
1363 * above.
1364 */
1365 case VMX_ASSIST_RESTORE:
1366 /* save the old context */
1367 if (!hvm_copy(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp), HVM_COPY_IN))
1368 goto error;
1369 if (cp != 0) {
1370 if (!hvm_copy(&c, cp, sizeof(c), HVM_COPY_IN))
1371 goto error;
1372 if (!vmx_world_restore(v, &c))
1373 goto error;
1374 return 1;
1376 break;
1379 error:
1380 printf("Failed to transfer to vmxassist\n");
1381 domain_crash_synchronous();
1382 return 0;
1385 static int vmx_set_cr0(unsigned long value)
1387 struct vcpu *v = current;
1388 unsigned long mfn;
1389 unsigned long eip;
1390 int paging_enabled;
1391 unsigned long vm_entry_value;
1392 unsigned long old_cr0;
1394 /*
1395 * CR0: We don't want to lose PE and PG.
1396 */
1397 __vmread_vcpu(v, CR0_READ_SHADOW, &old_cr0);
1398 paging_enabled = (old_cr0 & X86_CR0_PE) && (old_cr0 & X86_CR0_PG);
1400 /* TS cleared? Then initialise FPU now. */
1401 if ( !(value & X86_CR0_TS) )
1403 setup_fpu(v);
1404 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1407 __vmwrite(GUEST_CR0, value | X86_CR0_PE | X86_CR0_PG | X86_CR0_NE);
1408 __vmwrite(CR0_READ_SHADOW, value);
1410 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR0 value = %lx\n", value);
1412 if ( (value & X86_CR0_PE) && (value & X86_CR0_PG) && !paging_enabled )
1414 /*
1415 * Trying to enable guest paging.
1416 * The guest CR3 must be pointing to the guest physical.
1417 */
1418 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1419 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1420 !get_page(mfn_to_page(mfn), v->domain) )
1422 printk("Invalid CR3 value = %lx", v->arch.hvm_vmx.cpu_cr3);
1423 domain_crash_synchronous(); /* need to take a clean path */
1426 #if defined(__x86_64__)
1427 if ( test_bit(VMX_CPU_STATE_LME_ENABLED,
1428 &v->arch.hvm_vmx.cpu_state) &&
1429 !test_bit(VMX_CPU_STATE_PAE_ENABLED,
1430 &v->arch.hvm_vmx.cpu_state) )
1432 HVM_DBG_LOG(DBG_LEVEL_1, "Enable paging before PAE enabled\n");
1433 vmx_inject_exception(v, TRAP_gp_fault, 0);
1436 if ( test_bit(VMX_CPU_STATE_LME_ENABLED,
1437 &v->arch.hvm_vmx.cpu_state) )
1439 /* Here the PAE is should be opened */
1440 HVM_DBG_LOG(DBG_LEVEL_1, "Enable long mode\n");
1441 set_bit(VMX_CPU_STATE_LMA_ENABLED,
1442 &v->arch.hvm_vmx.cpu_state);
1444 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1445 vm_entry_value |= VM_ENTRY_CONTROLS_IA32E_MODE;
1446 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1448 if ( !shadow_set_guest_paging_levels(v->domain, PAGING_L4) )
1450 printk("Unsupported guest paging levels\n");
1451 domain_crash_synchronous(); /* need to take a clean path */
1454 else
1455 #endif /* __x86_64__ */
1457 #if CONFIG_PAGING_LEVELS >= 3
1458 /* seems it's a 32-bit or 32-bit PAE guest */
1460 if ( test_bit(VMX_CPU_STATE_PAE_ENABLED,
1461 &v->arch.hvm_vmx.cpu_state) )
1463 /* The guest enables PAE first and then it enables PG, it is
1464 * really a PAE guest */
1465 if ( !shadow_set_guest_paging_levels(v->domain, PAGING_L3) )
1467 printk("Unsupported guest paging levels\n");
1468 domain_crash_synchronous();
1471 else
1473 if ( !shadow_set_guest_paging_levels(v->domain, PAGING_L2) )
1475 printk("Unsupported guest paging levels\n");
1476 domain_crash_synchronous(); /* need to take a clean path */
1479 #endif
1482 /*
1483 * Now arch.guest_table points to machine physical.
1484 */
1485 v->arch.guest_table = pagetable_from_pfn(mfn);
1486 update_pagetables(v);
1488 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1489 (unsigned long) (mfn << PAGE_SHIFT));
1491 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1492 /*
1493 * arch->shadow_table should hold the next CR3 for shadow
1494 */
1495 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1496 v->arch.hvm_vmx.cpu_cr3, mfn);
1499 if ( !((value & X86_CR0_PE) && (value & X86_CR0_PG)) && paging_enabled )
1500 if ( v->arch.hvm_vmx.cpu_cr3 ) {
1501 put_page(mfn_to_page(get_mfn_from_gpfn(
1502 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)));
1503 v->arch.guest_table = pagetable_null();
1506 /*
1507 * VMX does not implement real-mode virtualization. We emulate
1508 * real-mode by performing a world switch to VMXAssist whenever
1509 * a partition disables the CR0.PE bit.
1510 */
1511 if ( (value & X86_CR0_PE) == 0 )
1513 if ( value & X86_CR0_PG ) {
1514 /* inject GP here */
1515 vmx_inject_exception(v, TRAP_gp_fault, 0);
1516 return 0;
1517 } else {
1518 /*
1519 * Disable paging here.
1520 * Same to PE == 1 && PG == 0
1521 */
1522 if ( test_bit(VMX_CPU_STATE_LMA_ENABLED,
1523 &v->arch.hvm_vmx.cpu_state) )
1525 clear_bit(VMX_CPU_STATE_LMA_ENABLED,
1526 &v->arch.hvm_vmx.cpu_state);
1527 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1528 vm_entry_value &= ~VM_ENTRY_CONTROLS_IA32E_MODE;
1529 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1533 clear_all_shadow_status(v->domain);
1534 if ( vmx_assist(v, VMX_ASSIST_INVOKE) ) {
1535 set_bit(VMX_CPU_STATE_ASSIST_ENABLED, &v->arch.hvm_vmx.cpu_state);
1536 __vmread(GUEST_RIP, &eip);
1537 HVM_DBG_LOG(DBG_LEVEL_1,
1538 "Transfering control to vmxassist %%eip 0x%lx\n", eip);
1539 return 0; /* do not update eip! */
1541 } else if ( test_bit(VMX_CPU_STATE_ASSIST_ENABLED,
1542 &v->arch.hvm_vmx.cpu_state) )
1544 __vmread(GUEST_RIP, &eip);
1545 HVM_DBG_LOG(DBG_LEVEL_1,
1546 "Enabling CR0.PE at %%eip 0x%lx\n", eip);
1547 if ( vmx_assist(v, VMX_ASSIST_RESTORE) )
1549 clear_bit(VMX_CPU_STATE_ASSIST_ENABLED,
1550 &v->arch.hvm_vmx.cpu_state);
1551 __vmread(GUEST_RIP, &eip);
1552 HVM_DBG_LOG(DBG_LEVEL_1,
1553 "Restoring to %%eip 0x%lx\n", eip);
1554 return 0; /* do not update eip! */
1557 else if ( (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PE )
1559 /* we should take care of this kind of situation */
1560 clear_all_shadow_status(v->domain);
1561 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->domain->arch.phys_table));
1564 return 1;
1567 #define CASE_SET_REG(REG, reg) \
1568 case REG_ ## REG: regs->reg = value; break
1569 #define CASE_GET_REG(REG, reg) \
1570 case REG_ ## REG: value = regs->reg; break
1572 #define CASE_EXTEND_SET_REG \
1573 CASE_EXTEND_REG(S)
1574 #define CASE_EXTEND_GET_REG \
1575 CASE_EXTEND_REG(G)
1577 #ifdef __i386__
1578 #define CASE_EXTEND_REG(T)
1579 #else
1580 #define CASE_EXTEND_REG(T) \
1581 CASE_ ## T ## ET_REG(R8, r8); \
1582 CASE_ ## T ## ET_REG(R9, r9); \
1583 CASE_ ## T ## ET_REG(R10, r10); \
1584 CASE_ ## T ## ET_REG(R11, r11); \
1585 CASE_ ## T ## ET_REG(R12, r12); \
1586 CASE_ ## T ## ET_REG(R13, r13); \
1587 CASE_ ## T ## ET_REG(R14, r14); \
1588 CASE_ ## T ## ET_REG(R15, r15)
1589 #endif
1591 /*
1592 * Write to control registers
1593 */
1594 static int mov_to_cr(int gp, int cr, struct cpu_user_regs *regs)
1596 unsigned long value;
1597 unsigned long old_cr;
1598 struct vcpu *v = current;
1600 switch ( gp ) {
1601 CASE_GET_REG(EAX, eax);
1602 CASE_GET_REG(ECX, ecx);
1603 CASE_GET_REG(EDX, edx);
1604 CASE_GET_REG(EBX, ebx);
1605 CASE_GET_REG(EBP, ebp);
1606 CASE_GET_REG(ESI, esi);
1607 CASE_GET_REG(EDI, edi);
1608 CASE_EXTEND_GET_REG;
1609 case REG_ESP:
1610 __vmread(GUEST_RSP, &value);
1611 break;
1612 default:
1613 printk("invalid gp: %d\n", gp);
1614 __hvm_bug(regs);
1617 HVM_DBG_LOG(DBG_LEVEL_1, "CR%d, value = %lx", cr, value);
1619 switch ( cr ) {
1620 case 0:
1621 return vmx_set_cr0(value);
1622 case 3:
1624 unsigned long old_base_mfn, mfn;
1626 /*
1627 * If paging is not enabled yet, simply copy the value to CR3.
1628 */
1629 if (!vmx_paging_enabled(v)) {
1630 v->arch.hvm_vmx.cpu_cr3 = value;
1631 break;
1634 /*
1635 * We make a new one if the shadow does not exist.
1636 */
1637 if (value == v->arch.hvm_vmx.cpu_cr3) {
1638 /*
1639 * This is simple TLB flush, implying the guest has
1640 * removed some translation or changed page attributes.
1641 * We simply invalidate the shadow.
1642 */
1643 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1644 if (mfn != pagetable_get_pfn(v->arch.guest_table))
1645 __hvm_bug(regs);
1646 shadow_sync_all(v->domain);
1647 } else {
1648 /*
1649 * If different, make a shadow. Check if the PDBR is valid
1650 * first.
1651 */
1652 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 value = %lx", value);
1653 if ( ((value >> PAGE_SHIFT) > v->domain->max_pages ) ||
1654 !VALID_MFN(mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT)) ||
1655 !get_page(mfn_to_page(mfn), v->domain) )
1657 printk("Invalid CR3 value=%lx", value);
1658 domain_crash_synchronous(); /* need to take a clean path */
1660 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1661 v->arch.guest_table = pagetable_from_pfn(mfn);
1662 if (old_base_mfn)
1663 put_page(mfn_to_page(old_base_mfn));
1664 /*
1665 * arch.shadow_table should now hold the next CR3 for shadow
1666 */
1667 #if CONFIG_PAGING_LEVELS >= 3
1668 if ( v->domain->arch.ops->guest_paging_levels == PAGING_L3 )
1669 shadow_sync_all(v->domain);
1670 #endif
1672 v->arch.hvm_vmx.cpu_cr3 = value;
1673 update_pagetables(v);
1674 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx",
1675 value);
1676 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1678 break;
1680 case 4: /* CR4 */
1682 __vmread(CR4_READ_SHADOW, &old_cr);
1684 if ( value & X86_CR4_PAE && !(old_cr & X86_CR4_PAE) )
1686 set_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1688 if ( vmx_pgbit_test(v) )
1690 /* The guest is a 32-bit PAE guest. */
1691 #if CONFIG_PAGING_LEVELS >= 3
1692 unsigned long mfn, old_base_mfn;
1694 if( !shadow_set_guest_paging_levels(v->domain, PAGING_L3) )
1696 printk("Unsupported guest paging levels\n");
1697 domain_crash_synchronous(); /* need to take a clean path */
1700 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1701 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1702 !get_page(mfn_to_page(mfn), v->domain) )
1704 printk("Invalid CR3 value = %lx", v->arch.hvm_vmx.cpu_cr3);
1705 domain_crash_synchronous(); /* need to take a clean path */
1708 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1709 if ( old_base_mfn )
1710 put_page(mfn_to_page(old_base_mfn));
1712 /*
1713 * Now arch.guest_table points to machine physical.
1714 */
1716 v->arch.guest_table = pagetable_from_pfn(mfn);
1717 update_pagetables(v);
1719 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1720 (unsigned long) (mfn << PAGE_SHIFT));
1722 __vmwrite(GUEST_CR3, pagetable_get_paddr(v->arch.shadow_table));
1724 /*
1725 * arch->shadow_table should hold the next CR3 for shadow
1726 */
1728 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1729 v->arch.hvm_vmx.cpu_cr3, mfn);
1730 #endif
1732 else
1734 /* The guest is a 64 bit or 32-bit PAE guest. */
1735 #if CONFIG_PAGING_LEVELS >= 3
1736 if ( (v->domain->arch.ops != NULL) &&
1737 v->domain->arch.ops->guest_paging_levels == PAGING_L2)
1739 /* Seems the guest first enables PAE without enabling PG,
1740 * it must enable PG after that, and it is a 32-bit PAE
1741 * guest */
1743 if ( !shadow_set_guest_paging_levels(v->domain,
1744 PAGING_L3) )
1746 printk("Unsupported guest paging levels\n");
1747 /* need to take a clean path */
1748 domain_crash_synchronous();
1751 #endif
1754 else if ( value & X86_CR4_PAE )
1755 set_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1756 else
1758 if ( test_bit(VMX_CPU_STATE_LMA_ENABLED, &v->arch.hvm_vmx.cpu_state) )
1759 vmx_inject_exception(v, TRAP_gp_fault, 0);
1761 clear_bit(VMX_CPU_STATE_PAE_ENABLED, &v->arch.hvm_vmx.cpu_state);
1764 __vmwrite(GUEST_CR4, value| VMX_CR4_HOST_MASK);
1765 __vmwrite(CR4_READ_SHADOW, value);
1767 /*
1768 * Writing to CR4 to modify the PSE, PGE, or PAE flag invalidates
1769 * all TLB entries except global entries.
1770 */
1771 if ( (old_cr ^ value) & (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE) )
1772 shadow_sync_all(v->domain);
1774 break;
1776 default:
1777 printk("invalid cr: %d\n", gp);
1778 __hvm_bug(regs);
1781 return 1;
1784 /*
1785 * Read from control registers. CR0 and CR4 are read from the shadow.
1786 */
1787 static void mov_from_cr(int cr, int gp, struct cpu_user_regs *regs)
1789 unsigned long value;
1790 struct vcpu *v = current;
1792 if ( cr != 3 )
1793 __hvm_bug(regs);
1795 value = (unsigned long) v->arch.hvm_vmx.cpu_cr3;
1797 switch ( gp ) {
1798 CASE_SET_REG(EAX, eax);
1799 CASE_SET_REG(ECX, ecx);
1800 CASE_SET_REG(EDX, edx);
1801 CASE_SET_REG(EBX, ebx);
1802 CASE_SET_REG(EBP, ebp);
1803 CASE_SET_REG(ESI, esi);
1804 CASE_SET_REG(EDI, edi);
1805 CASE_EXTEND_SET_REG;
1806 case REG_ESP:
1807 __vmwrite(GUEST_RSP, value);
1808 regs->esp = value;
1809 break;
1810 default:
1811 printk("invalid gp: %d\n", gp);
1812 __hvm_bug(regs);
1815 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR%d, value = %lx", cr, value);
1818 static int vmx_cr_access(unsigned long exit_qualification, struct cpu_user_regs *regs)
1820 unsigned int gp, cr;
1821 unsigned long value;
1822 struct vcpu *v = current;
1824 switch (exit_qualification & CONTROL_REG_ACCESS_TYPE) {
1825 case TYPE_MOV_TO_CR:
1826 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1827 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1828 TRACE_VMEXIT(1,TYPE_MOV_TO_CR);
1829 TRACE_VMEXIT(2,cr);
1830 TRACE_VMEXIT(3,gp);
1831 return mov_to_cr(gp, cr, regs);
1832 case TYPE_MOV_FROM_CR:
1833 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1834 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1835 TRACE_VMEXIT(1,TYPE_MOV_FROM_CR);
1836 TRACE_VMEXIT(2,cr);
1837 TRACE_VMEXIT(3,gp);
1838 mov_from_cr(cr, gp, regs);
1839 break;
1840 case TYPE_CLTS:
1841 TRACE_VMEXIT(1,TYPE_CLTS);
1843 /* We initialise the FPU now, to avoid needing another vmexit. */
1844 setup_fpu(v);
1845 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1847 __vmread_vcpu(v, GUEST_CR0, &value);
1848 value &= ~X86_CR0_TS; /* clear TS */
1849 __vmwrite(GUEST_CR0, value);
1851 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1852 value &= ~X86_CR0_TS; /* clear TS */
1853 __vmwrite(CR0_READ_SHADOW, value);
1854 break;
1855 case TYPE_LMSW:
1856 TRACE_VMEXIT(1,TYPE_LMSW);
1857 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1858 value = (value & ~0xF) |
1859 (((exit_qualification & LMSW_SOURCE_DATA) >> 16) & 0xF);
1860 return vmx_set_cr0(value);
1861 break;
1862 default:
1863 __hvm_bug(regs);
1864 break;
1866 return 1;
1869 static inline void vmx_do_msr_read(struct cpu_user_regs *regs)
1871 u64 msr_content = 0;
1872 struct vcpu *v = current;
1874 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read: ecx=%lx, eax=%lx, edx=%lx",
1875 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1876 (unsigned long)regs->edx);
1877 switch (regs->ecx) {
1878 case MSR_IA32_TIME_STAMP_COUNTER:
1879 msr_content = hvm_get_guest_time(v);
1880 break;
1881 case MSR_IA32_SYSENTER_CS:
1882 __vmread(GUEST_SYSENTER_CS, (u32 *)&msr_content);
1883 break;
1884 case MSR_IA32_SYSENTER_ESP:
1885 __vmread(GUEST_SYSENTER_ESP, &msr_content);
1886 break;
1887 case MSR_IA32_SYSENTER_EIP:
1888 __vmread(GUEST_SYSENTER_EIP, &msr_content);
1889 break;
1890 case MSR_IA32_APICBASE:
1891 msr_content = VLAPIC(v) ? VLAPIC(v)->apic_base_msr : 0;
1892 break;
1893 default:
1894 if(long_mode_do_msr_read(regs))
1895 return;
1896 rdmsr_safe(regs->ecx, regs->eax, regs->edx);
1897 break;
1900 regs->eax = msr_content & 0xFFFFFFFF;
1901 regs->edx = msr_content >> 32;
1903 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read returns: "
1904 "ecx=%lx, eax=%lx, edx=%lx",
1905 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1906 (unsigned long)regs->edx);
1909 static inline void vmx_do_msr_write(struct cpu_user_regs *regs)
1911 u64 msr_content;
1912 struct vcpu *v = current;
1914 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write: ecx=%lx, eax=%lx, edx=%lx",
1915 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1916 (unsigned long)regs->edx);
1918 msr_content = (regs->eax & 0xFFFFFFFF) | ((u64)regs->edx << 32);
1920 switch (regs->ecx) {
1921 case MSR_IA32_TIME_STAMP_COUNTER:
1922 set_guest_time(v, msr_content);
1923 break;
1924 case MSR_IA32_SYSENTER_CS:
1925 __vmwrite(GUEST_SYSENTER_CS, msr_content);
1926 break;
1927 case MSR_IA32_SYSENTER_ESP:
1928 __vmwrite(GUEST_SYSENTER_ESP, msr_content);
1929 break;
1930 case MSR_IA32_SYSENTER_EIP:
1931 __vmwrite(GUEST_SYSENTER_EIP, msr_content);
1932 break;
1933 case MSR_IA32_APICBASE:
1934 vlapic_msr_set(VLAPIC(v), msr_content);
1935 break;
1936 default:
1937 long_mode_do_msr_write(regs);
1938 break;
1941 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write returns: "
1942 "ecx=%lx, eax=%lx, edx=%lx",
1943 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1944 (unsigned long)regs->edx);
1947 /*
1948 * Need to use this exit to reschedule
1949 */
1950 void vmx_vmexit_do_hlt(void)
1952 struct vcpu *v=current;
1953 struct periodic_time *pt = &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
1954 s_time_t next_pit=-1,next_wakeup;
1956 if ( !v->vcpu_id )
1957 next_pit = get_scheduled(v, pt->irq, pt);
1958 next_wakeup = get_apictime_scheduled(v);
1959 if ( (next_pit != -1 && next_pit < next_wakeup) || next_wakeup == -1 )
1960 next_wakeup = next_pit;
1961 if ( next_wakeup != - 1 )
1962 set_timer(&current->arch.hvm_vmx.hlt_timer, next_wakeup);
1963 hvm_safe_block();
1966 static inline void vmx_vmexit_do_extint(struct cpu_user_regs *regs)
1968 unsigned int vector;
1969 int error;
1971 asmlinkage void do_IRQ(struct cpu_user_regs *);
1972 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs *);
1973 fastcall void smp_event_check_interrupt(void);
1974 fastcall void smp_invalidate_interrupt(void);
1975 fastcall void smp_call_function_interrupt(void);
1976 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs);
1977 fastcall void smp_error_interrupt(struct cpu_user_regs *regs);
1978 #ifdef CONFIG_X86_MCE_P4THERMAL
1979 fastcall void smp_thermal_interrupt(struct cpu_user_regs *regs);
1980 #endif
1982 if ((error = __vmread(VM_EXIT_INTR_INFO, &vector))
1983 && !(vector & INTR_INFO_VALID_MASK))
1984 __hvm_bug(regs);
1986 vector &= INTR_INFO_VECTOR_MASK;
1987 TRACE_VMEXIT(1,vector);
1989 switch(vector) {
1990 case LOCAL_TIMER_VECTOR:
1991 smp_apic_timer_interrupt(regs);
1992 break;
1993 case EVENT_CHECK_VECTOR:
1994 smp_event_check_interrupt();
1995 break;
1996 case INVALIDATE_TLB_VECTOR:
1997 smp_invalidate_interrupt();
1998 break;
1999 case CALL_FUNCTION_VECTOR:
2000 smp_call_function_interrupt();
2001 break;
2002 case SPURIOUS_APIC_VECTOR:
2003 smp_spurious_interrupt(regs);
2004 break;
2005 case ERROR_APIC_VECTOR:
2006 smp_error_interrupt(regs);
2007 break;
2008 #ifdef CONFIG_X86_MCE_P4THERMAL
2009 case THERMAL_APIC_VECTOR:
2010 smp_thermal_interrupt(regs);
2011 break;
2012 #endif
2013 default:
2014 regs->entry_vector = vector;
2015 do_IRQ(regs);
2016 break;
2020 #if defined (__x86_64__)
2021 void store_cpu_user_regs(struct cpu_user_regs *regs)
2023 __vmread(GUEST_SS_SELECTOR, &regs->ss);
2024 __vmread(GUEST_RSP, &regs->rsp);
2025 __vmread(GUEST_RFLAGS, &regs->rflags);
2026 __vmread(GUEST_CS_SELECTOR, &regs->cs);
2027 __vmread(GUEST_DS_SELECTOR, &regs->ds);
2028 __vmread(GUEST_ES_SELECTOR, &regs->es);
2029 __vmread(GUEST_RIP, &regs->rip);
2031 #elif defined (__i386__)
2032 void store_cpu_user_regs(struct cpu_user_regs *regs)
2034 __vmread(GUEST_SS_SELECTOR, &regs->ss);
2035 __vmread(GUEST_RSP, &regs->esp);
2036 __vmread(GUEST_RFLAGS, &regs->eflags);
2037 __vmread(GUEST_CS_SELECTOR, &regs->cs);
2038 __vmread(GUEST_DS_SELECTOR, &regs->ds);
2039 __vmread(GUEST_ES_SELECTOR, &regs->es);
2040 __vmread(GUEST_RIP, &regs->eip);
2042 #endif
2044 #ifdef XEN_DEBUGGER
2045 void save_cpu_user_regs(struct cpu_user_regs *regs)
2047 __vmread(GUEST_SS_SELECTOR, &regs->xss);
2048 __vmread(GUEST_RSP, &regs->esp);
2049 __vmread(GUEST_RFLAGS, &regs->eflags);
2050 __vmread(GUEST_CS_SELECTOR, &regs->xcs);
2051 __vmread(GUEST_RIP, &regs->eip);
2053 __vmread(GUEST_GS_SELECTOR, &regs->xgs);
2054 __vmread(GUEST_FS_SELECTOR, &regs->xfs);
2055 __vmread(GUEST_ES_SELECTOR, &regs->xes);
2056 __vmread(GUEST_DS_SELECTOR, &regs->xds);
2059 void restore_cpu_user_regs(struct cpu_user_regs *regs)
2061 __vmwrite(GUEST_SS_SELECTOR, regs->xss);
2062 __vmwrite(GUEST_RSP, regs->esp);
2063 __vmwrite(GUEST_RFLAGS, regs->eflags);
2064 __vmwrite(GUEST_CS_SELECTOR, regs->xcs);
2065 __vmwrite(GUEST_RIP, regs->eip);
2067 __vmwrite(GUEST_GS_SELECTOR, regs->xgs);
2068 __vmwrite(GUEST_FS_SELECTOR, regs->xfs);
2069 __vmwrite(GUEST_ES_SELECTOR, regs->xes);
2070 __vmwrite(GUEST_DS_SELECTOR, regs->xds);
2072 #endif
2074 asmlinkage void vmx_vmexit_handler(struct cpu_user_regs regs)
2076 unsigned int exit_reason;
2077 unsigned long exit_qualification, eip, inst_len = 0;
2078 struct vcpu *v = current;
2079 int error;
2081 error = __vmread(VM_EXIT_REASON, &exit_reason);
2082 BUG_ON(error);
2084 perfc_incra(vmexits, exit_reason);
2086 if ( (exit_reason != EXIT_REASON_EXTERNAL_INTERRUPT) &&
2087 (exit_reason != EXIT_REASON_VMCALL) &&
2088 (exit_reason != EXIT_REASON_IO_INSTRUCTION) )
2089 HVM_DBG_LOG(DBG_LEVEL_0, "exit reason = %x", exit_reason);
2091 if ( exit_reason != EXIT_REASON_EXTERNAL_INTERRUPT )
2092 local_irq_enable();
2094 if ( unlikely(exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) )
2096 unsigned int failed_vmentry_reason = exit_reason & 0xFFFF;
2098 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2099 printk("Failed vm entry (exit reason 0x%x) ", exit_reason);
2100 switch ( failed_vmentry_reason ) {
2101 case EXIT_REASON_INVALID_GUEST_STATE:
2102 printk("caused by invalid guest state (%ld).\n", exit_qualification);
2103 break;
2104 case EXIT_REASON_MSR_LOADING:
2105 printk("caused by MSR entry %ld loading.\n", exit_qualification);
2106 break;
2107 case EXIT_REASON_MACHINE_CHECK:
2108 printk("caused by machine check.\n");
2109 break;
2110 default:
2111 printk("reason not known yet!");
2112 break;
2115 printk("************* VMCS Area **************\n");
2116 vmcs_dump_vcpu();
2117 printk("**************************************\n");
2118 domain_crash_synchronous();
2121 __vmread(GUEST_RIP, &eip);
2122 TRACE_VMEXIT(0,exit_reason);
2124 switch ( exit_reason )
2126 case EXIT_REASON_EXCEPTION_NMI:
2128 /*
2129 * We don't set the software-interrupt exiting (INT n).
2130 * (1) We can get an exception (e.g. #PG) in the guest, or
2131 * (2) NMI
2132 */
2133 int error;
2134 unsigned int vector;
2135 unsigned long va;
2137 if ((error = __vmread(VM_EXIT_INTR_INFO, &vector))
2138 || !(vector & INTR_INFO_VALID_MASK))
2139 __hvm_bug(&regs);
2140 vector &= INTR_INFO_VECTOR_MASK;
2142 TRACE_VMEXIT(1,vector);
2143 perfc_incra(cause_vector, vector);
2145 switch (vector) {
2146 #ifdef XEN_DEBUGGER
2147 case TRAP_debug:
2149 save_cpu_user_regs(&regs);
2150 pdb_handle_exception(1, &regs, 1);
2151 restore_cpu_user_regs(&regs);
2152 break;
2154 case TRAP_int3:
2156 save_cpu_user_regs(&regs);
2157 pdb_handle_exception(3, &regs, 1);
2158 restore_cpu_user_regs(&regs);
2159 break;
2161 #else
2162 case TRAP_debug:
2164 void store_cpu_user_regs(struct cpu_user_regs *regs);
2166 if ( test_bit(_DOMF_debugging, &v->domain->domain_flags) )
2168 store_cpu_user_regs(&regs);
2169 domain_pause_for_debugger();
2170 __vm_clear_bit(GUEST_PENDING_DBG_EXCEPTIONS,
2171 PENDING_DEBUG_EXC_BS);
2173 else
2175 vmx_reflect_exception(v);
2176 __vm_clear_bit(GUEST_PENDING_DBG_EXCEPTIONS,
2177 PENDING_DEBUG_EXC_BS);
2180 break;
2182 case TRAP_int3:
2184 if ( test_bit(_DOMF_debugging, &v->domain->domain_flags) )
2185 domain_pause_for_debugger();
2186 else
2187 vmx_inject_exception(v, TRAP_int3, VMX_DELIVER_NO_ERROR_CODE);
2188 break;
2190 #endif
2191 case TRAP_no_device:
2193 vmx_do_no_device_fault();
2194 break;
2196 case TRAP_page_fault:
2198 __vmread(EXIT_QUALIFICATION, &va);
2199 __vmread(VM_EXIT_INTR_ERROR_CODE, &regs.error_code);
2201 TRACE_VMEXIT(3,regs.error_code);
2202 TRACE_VMEXIT(4,va);
2204 HVM_DBG_LOG(DBG_LEVEL_VMMU,
2205 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
2206 (unsigned long)regs.eax, (unsigned long)regs.ebx,
2207 (unsigned long)regs.ecx, (unsigned long)regs.edx,
2208 (unsigned long)regs.esi, (unsigned long)regs.edi);
2209 v->arch.hvm_vcpu.mmio_op.inst_decoder_regs = &regs;
2211 if (!(error = vmx_do_page_fault(va, &regs))) {
2212 /*
2213 * Inject #PG using Interruption-Information Fields
2214 */
2215 vmx_inject_exception(v, TRAP_page_fault, regs.error_code);
2216 v->arch.hvm_vmx.cpu_cr2 = va;
2217 TRACE_3D(TRC_VMX_INT, v->domain->domain_id, TRAP_page_fault, va);
2219 break;
2221 case TRAP_nmi:
2222 do_nmi(&regs);
2223 break;
2224 default:
2225 vmx_reflect_exception(v);
2226 break;
2228 break;
2230 case EXIT_REASON_EXTERNAL_INTERRUPT:
2231 vmx_vmexit_do_extint(&regs);
2232 break;
2233 case EXIT_REASON_PENDING_INTERRUPT:
2234 /*
2235 * Not sure exactly what the purpose of this is. The only bits set
2236 * and cleared at this point are CPU_BASED_VIRTUAL_INTR_PENDING.
2237 * (in io.c:{enable,disable}_irq_window(). So presumably we want to
2238 * set it to the original value...
2239 */
2240 v->arch.hvm_vcpu.u.vmx.exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2241 v->arch.hvm_vcpu.u.vmx.exec_control |=
2242 (MONITOR_CPU_BASED_EXEC_CONTROLS & CPU_BASED_VIRTUAL_INTR_PENDING);
2243 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
2244 v->arch.hvm_vcpu.u.vmx.exec_control);
2245 break;
2246 case EXIT_REASON_TASK_SWITCH:
2247 __hvm_bug(&regs);
2248 break;
2249 case EXIT_REASON_CPUID:
2250 vmx_vmexit_do_cpuid(&regs);
2251 __get_instruction_length(inst_len);
2252 __update_guest_eip(inst_len);
2253 break;
2254 case EXIT_REASON_HLT:
2255 __get_instruction_length(inst_len);
2256 __update_guest_eip(inst_len);
2257 vmx_vmexit_do_hlt();
2258 break;
2259 case EXIT_REASON_INVLPG:
2261 unsigned long va;
2263 __vmread(EXIT_QUALIFICATION, &va);
2264 vmx_vmexit_do_invlpg(va);
2265 __get_instruction_length(inst_len);
2266 __update_guest_eip(inst_len);
2267 break;
2269 #if 0 /* keep this for debugging */
2270 case EXIT_REASON_VMCALL:
2271 __get_instruction_length(inst_len);
2272 __vmread(GUEST_RIP, &eip);
2273 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2275 hvm_print_line(v, regs.eax); /* provides the current domain */
2276 __update_guest_eip(inst_len);
2277 break;
2278 #endif
2279 case EXIT_REASON_CR_ACCESS:
2281 __vmread(GUEST_RIP, &eip);
2282 __get_instruction_length(inst_len);
2283 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2285 HVM_DBG_LOG(DBG_LEVEL_1, "eip = %lx, inst_len =%lx, exit_qualification = %lx",
2286 eip, inst_len, exit_qualification);
2287 if (vmx_cr_access(exit_qualification, &regs))
2288 __update_guest_eip(inst_len);
2289 TRACE_VMEXIT(3,regs.error_code);
2290 TRACE_VMEXIT(4,exit_qualification);
2291 break;
2293 case EXIT_REASON_DR_ACCESS:
2294 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2295 vmx_dr_access(exit_qualification, &regs);
2296 __get_instruction_length(inst_len);
2297 __update_guest_eip(inst_len);
2298 break;
2299 case EXIT_REASON_IO_INSTRUCTION:
2300 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2301 __get_instruction_length(inst_len);
2302 vmx_io_instruction(&regs, exit_qualification, inst_len);
2303 TRACE_VMEXIT(4,exit_qualification);
2304 break;
2305 case EXIT_REASON_MSR_READ:
2306 __get_instruction_length(inst_len);
2307 vmx_do_msr_read(&regs);
2308 __update_guest_eip(inst_len);
2309 break;
2310 case EXIT_REASON_MSR_WRITE:
2311 __vmread(GUEST_RIP, &eip);
2312 vmx_do_msr_write(&regs);
2313 __get_instruction_length(inst_len);
2314 __update_guest_eip(inst_len);
2315 break;
2316 case EXIT_REASON_MWAIT_INSTRUCTION:
2317 __hvm_bug(&regs);
2318 break;
2319 case EXIT_REASON_VMCALL:
2320 case EXIT_REASON_VMCLEAR:
2321 case EXIT_REASON_VMLAUNCH:
2322 case EXIT_REASON_VMPTRLD:
2323 case EXIT_REASON_VMPTRST:
2324 case EXIT_REASON_VMREAD:
2325 case EXIT_REASON_VMRESUME:
2326 case EXIT_REASON_VMWRITE:
2327 case EXIT_REASON_VMOFF:
2328 case EXIT_REASON_VMON:
2329 /* Report invalid opcode exception when a VMX guest tries to execute
2330 any of the VMX instructions */
2331 vmx_inject_exception(v, TRAP_invalid_op, VMX_DELIVER_NO_ERROR_CODE);
2332 break;
2334 default:
2335 __hvm_bug(&regs); /* should not happen */
2339 asmlinkage void vmx_load_cr2(void)
2341 struct vcpu *v = current;
2343 local_irq_disable();
2344 asm volatile("mov %0,%%cr2": :"r" (v->arch.hvm_vmx.cpu_cr2));
2347 asmlinkage void vmx_trace_vmentry (void)
2349 TRACE_5D(TRC_VMX_VMENTRY,
2350 trace_values[smp_processor_id()][0],
2351 trace_values[smp_processor_id()][1],
2352 trace_values[smp_processor_id()][2],
2353 trace_values[smp_processor_id()][3],
2354 trace_values[smp_processor_id()][4]);
2355 TRACE_VMEXIT(0,9);
2356 TRACE_VMEXIT(1,9);
2357 TRACE_VMEXIT(2,9);
2358 TRACE_VMEXIT(3,9);
2359 TRACE_VMEXIT(4,9);
2360 return;
2363 asmlinkage void vmx_trace_vmexit (void)
2365 TRACE_3D(TRC_VMX_VMEXIT,0,0,0);
2366 return;
2369 /*
2370 * Local variables:
2371 * mode: C
2372 * c-set-style: "BSD"
2373 * c-basic-offset: 4
2374 * tab-width: 4
2375 * indent-tabs-mode: nil
2376 * End:
2377 */