ia64/xen-unstable

view linux-2.6-xen-sparse/arch/ia64/kernel/gate.S @ 10703:8d501f39286c

[IA64] vDSO paravirtualization: paravirtualize vDSO

paravirtualize vdso areabased on Kevin's pointout and Dan's Idea.
introduce hyperprivop HYPERPRIVOP_RSM_BE and HYPERPRIVOP_GET_PSR.
and paravirtualize vdso area using them.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author awilliam@xenbuild.aw
date Mon Jul 24 13:43:35 2006 -0600 (2006-07-24)
parents f8ab23b4f704
children 147144f9ec51
line source
1 /*
2 * This file contains the code that gets mapped at the upper end of each task's text
3 * region. For now, it contains the signal trampoline code only.
4 *
5 * Copyright (C) 1999-2003 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 */
9 #include <linux/config.h>
11 #include <asm/asmmacro.h>
12 #include <asm/errno.h>
13 #include <asm/asm-offsets.h>
14 #include <asm/sigcontext.h>
15 #include <asm/system.h>
16 #include <asm/unistd.h>
17 #ifdef CONFIG_XEN_IA64_VDSO_PARAVIRT
18 # include <asm/privop.h>
19 #endif
21 /*
22 * We can't easily refer to symbols inside the kernel. To avoid full runtime relocation,
23 * complications with the linker (which likes to create PLT stubs for branches
24 * to targets outside the shared object) and to avoid multi-phase kernel builds, we
25 * simply create minimalistic "patch lists" in special ELF sections.
26 */
27 .section ".data.patch.fsyscall_table", "a"
28 .previous
29 #define LOAD_FSYSCALL_TABLE(reg) \
30 [1:] movl reg=0; \
31 .xdata4 ".data.patch.fsyscall_table", 1b-.
33 .section ".data.patch.brl_fsys_bubble_down", "a"
34 .previous
35 #define BRL_COND_FSYS_BUBBLE_DOWN(pr) \
36 [1:](pr)brl.cond.sptk 0; \
37 .xdata4 ".data.patch.brl_fsys_bubble_down", 1b-.
39 #ifdef CONFIG_XEN_IA64_VDSO_PARAVIRT
40 // The page in which hyperprivop lives must be pinned by ITR.
41 // However vDSO area isn't pinned. So issuing hyperprivop
42 // from vDSO page causes trouble that Kevin pointed out.
43 // After clearing vpsr.ic, the vcpu is pre-empted and the itlb
44 // is flushed. Then vcpu get cpu again, tlb miss fault occures.
45 // However it results in nested dtlb fault because vpsr.ic is off.
46 // To avoid such a situation, we jump into the kernel text area
47 // which is pinned, and then issue hyperprivop and return back
48 // to vDSO page.
49 // This is Dan Magenheimer's idea.
51 // Currently is_running_on_xen() is defined as running_on_xen.
52 // If is_running_on_xen() is a real function, we must update
53 // according to it.
54 .section ".data.patch.running_on_xen", "a"
55 .previous
56 #define LOAD_RUNNING_ON_XEN(reg) \
57 [1:] movl reg=0; \
58 .xdata4 ".data.patch.running_on_xen", 1b-.
60 .section ".data.patch.brl_xen_rsm_be_i", "a"
61 .previous
62 #define BRL_COND_XEN_RSM_BE_I(pr) \
63 [1:](pr)brl.cond.sptk 0; \
64 .xdata4 ".data.patch.brl_xen_rsm_be_i", 1b-.
66 .section ".data.patch.brl_xen_get_psr", "a"
67 .previous
68 #define BRL_COND_XEN_GET_PSR(pr) \
69 [1:](pr)brl.cond.sptk 0; \
70 .xdata4 ".data.patch.brl_xen_get_psr", 1b-.
72 .section ".data.patch.brl_xen_ssm_i_0", "a"
73 .previous
74 #define BRL_COND_XEN_SSM_I_0(pr) \
75 [1:](pr)brl.cond.sptk 0; \
76 .xdata4 ".data.patch.brl_xen_ssm_i_0", 1b-.
78 .section ".data.patch.brl_xen_ssm_i_1", "a"
79 .previous
80 #define BRL_COND_XEN_SSM_I_1(pr) \
81 [1:](pr)brl.cond.sptk 0; \
82 .xdata4 ".data.patch.brl_xen_ssm_i_1", 1b-.
83 #endif
85 GLOBAL_ENTRY(__kernel_syscall_via_break)
86 .prologue
87 .altrp b6
88 .body
89 /*
90 * Note: for (fast) syscall restart to work, the break instruction must be
91 * the first one in the bundle addressed by syscall_via_break.
92 */
93 { .mib
94 break 0x100000
95 nop.i 0
96 br.ret.sptk.many b6
97 }
98 END(__kernel_syscall_via_break)
100 /*
101 * On entry:
102 * r11 = saved ar.pfs
103 * r15 = system call #
104 * b0 = saved return address
105 * b6 = return address
106 * On exit:
107 * r11 = saved ar.pfs
108 * r15 = system call #
109 * b0 = saved return address
110 * all other "scratch" registers: undefined
111 * all "preserved" registers: same as on entry
112 */
114 GLOBAL_ENTRY(__kernel_syscall_via_epc)
115 .prologue
116 .altrp b6
117 .body
118 {
119 /*
120 * Note: the kernel cannot assume that the first two instructions in this
121 * bundle get executed. The remaining code must be safe even if
122 * they do not get executed.
123 */
124 adds r17=-1024,r15 // A
125 mov r10=0 // A default to successful syscall execution
126 epc // B causes split-issue
127 }
128 ;;
129 #ifdef CONFIG_XEN_IA64_VDSO_PARAVIRT
130 // r20 = 1
131 // r22 = &vcpu->evtchn_mask
132 // r23 = &vpsr.ic
133 // r24 = vcpu->pending_interruption
134 // r25 = tmp
135 // r28 = &running_on_xen
136 // r30 = running_on_xen
137 // r31 = tmp
138 // p11 = tmp
139 // p12 = running_on_xen
140 // p13 = !running_on_xen
141 // p14 = tmp
142 // p15 = tmp
143 #define isXen p12
144 #define isRaw p13
145 LOAD_RUNNING_ON_XEN(r28)
146 movl r22=XSI_PSR_I_ADDR
147 movl r23=XSI_PSR_IC
148 movl r24=XSI_PSR_I_ADDR+(XSI_PEND_OFS-XSI_PSR_I_ADDR_OFS)
149 mov r20=1
150 ;;
151 ld4 r30=[r28]
152 ;;
153 cmp.ne isXen,isRaw=r0,r30
154 ;;
155 (isRaw) rsm psr.be | psr.i
156 BRL_COND_XEN_RSM_BE_I(isXen)
157 .global .vdso_rsm_be_i_ret
158 .vdso_rsm_be_i_ret:
159 #else
160 rsm psr.be | psr.i // M2 (5 cyc to srlz.d)
161 #endif
162 LOAD_FSYSCALL_TABLE(r14) // X
163 ;;
164 mov r16=IA64_KR(CURRENT) // M2 (12 cyc)
165 shladd r18=r17,3,r14 // A
166 mov r19=NR_syscalls-1 // A
167 ;;
168 lfetch [r18] // M0|1
169 #ifdef CONFIG_XEN_IA64_VDSO_PARAVIRT
170 (isRaw) mov r29=psr
171 BRL_COND_XEN_GET_PSR(isXen)
172 .global .vdso_get_psr_ret
173 .vdso_get_psr_ret:
174 #else
175 mov r29=psr // M2 (12 cyc)
176 #endif
177 // If r17 is a NaT, p6 will be zero
178 cmp.geu p6,p7=r19,r17 // A (sysnr > 0 && sysnr < 1024+NR_syscalls)?
179 ;;
180 mov r21=ar.fpsr // M2 (12 cyc)
181 tnat.nz p10,p9=r15 // I0
182 mov.i r26=ar.pfs // I0 (would stall anyhow due to srlz.d...)
183 ;;
184 srlz.d // M0 (forces split-issue) ensure PSR.BE==0
185 (p6) ld8 r18=[r18] // M0|1
186 nop.i 0
187 ;;
188 nop.m 0
189 (p6) tbit.z.unc p8,p0=r18,0 // I0 (dual-issues with "mov b7=r18"!)
190 #ifdef CONFIG_XEN_IA64_VDSO_PARAVIRT
191 ;;
192 // p14 = running_on_xen && p8
193 // p15 = !running_on_xen && p8
194 (p8) cmp.ne.unc p14,p15=r0,r30
195 ;;
196 (p15) ssm psr.i
197 BRL_COND_XEN_SSM_I_0(p14)
198 .global .vdso_ssm_i_0_ret
199 .vdso_ssm_i_0_ret:
200 #else
201 nop.i 0
202 ;;
203 (p8) ssm psr.i
204 #endif
205 (p6) mov b7=r18 // I0
206 (p8) br.dptk.many b7 // B
208 mov r27=ar.rsc // M2 (12 cyc)
209 /*
210 * brl.cond doesn't work as intended because the linker would convert this branch
211 * into a branch to a PLT. Perhaps there will be a way to avoid this with some
212 * future version of the linker. In the meantime, we just use an indirect branch
213 * instead.
214 */
215 #ifdef CONFIG_ITANIUM
216 (p6) add r14=-8,r14 // r14 <- addr of fsys_bubble_down entry
217 ;;
218 (p6) ld8 r14=[r14] // r14 <- fsys_bubble_down
219 ;;
220 (p6) mov b7=r14
221 (p6) br.sptk.many b7
222 #else
223 BRL_COND_FSYS_BUBBLE_DOWN(p6)
224 #endif
225 #ifdef CONFIG_XEN_IA64_VDSO_PARAVIRT
226 (isRaw) ssm psr.i
227 BRL_COND_XEN_SSM_I_1(isXen)
228 .global .vdso_ssm_i_1_ret
229 .vdso_ssm_i_1_ret:
230 #else
231 ssm psr.i
232 #endif
233 mov r10=-1
234 (p10) mov r8=EINVAL
235 #ifdef CONFIG_XEN_IA64_VDSO_PARAVIRT
236 dv_serialize_data // shut up gas warning.
237 // we know xen_hyper_ssm_i_0 or xen_hyper_ssm_i_1
238 // doesn't change p9 and p10
239 #endif
240 (p9) mov r8=ENOSYS
241 FSYS_RETURN
242 END(__kernel_syscall_via_epc)
244 # define ARG0_OFF (16 + IA64_SIGFRAME_ARG0_OFFSET)
245 # define ARG1_OFF (16 + IA64_SIGFRAME_ARG1_OFFSET)
246 # define ARG2_OFF (16 + IA64_SIGFRAME_ARG2_OFFSET)
247 # define SIGHANDLER_OFF (16 + IA64_SIGFRAME_HANDLER_OFFSET)
248 # define SIGCONTEXT_OFF (16 + IA64_SIGFRAME_SIGCONTEXT_OFFSET)
250 # define FLAGS_OFF IA64_SIGCONTEXT_FLAGS_OFFSET
251 # define CFM_OFF IA64_SIGCONTEXT_CFM_OFFSET
252 # define FR6_OFF IA64_SIGCONTEXT_FR6_OFFSET
253 # define BSP_OFF IA64_SIGCONTEXT_AR_BSP_OFFSET
254 # define RNAT_OFF IA64_SIGCONTEXT_AR_RNAT_OFFSET
255 # define UNAT_OFF IA64_SIGCONTEXT_AR_UNAT_OFFSET
256 # define FPSR_OFF IA64_SIGCONTEXT_AR_FPSR_OFFSET
257 # define PR_OFF IA64_SIGCONTEXT_PR_OFFSET
258 # define RP_OFF IA64_SIGCONTEXT_IP_OFFSET
259 # define SP_OFF IA64_SIGCONTEXT_R12_OFFSET
260 # define RBS_BASE_OFF IA64_SIGCONTEXT_RBS_BASE_OFFSET
261 # define LOADRS_OFF IA64_SIGCONTEXT_LOADRS_OFFSET
262 # define base0 r2
263 # define base1 r3
264 /*
265 * When we get here, the memory stack looks like this:
266 *
267 * +===============================+
268 * | |
269 * // struct sigframe //
270 * | |
271 * +-------------------------------+ <-- sp+16
272 * | 16 byte of scratch |
273 * | space |
274 * +-------------------------------+ <-- sp
275 *
276 * The register stack looks _exactly_ the way it looked at the time the signal
277 * occurred. In other words, we're treading on a potential mine-field: each
278 * incoming general register may be a NaT value (including sp, in which case the
279 * process ends up dying with a SIGSEGV).
280 *
281 * The first thing need to do is a cover to get the registers onto the backing
282 * store. Once that is done, we invoke the signal handler which may modify some
283 * of the machine state. After returning from the signal handler, we return
284 * control to the previous context by executing a sigreturn system call. A signal
285 * handler may call the rt_sigreturn() function to directly return to a given
286 * sigcontext. However, the user-level sigreturn() needs to do much more than
287 * calling the rt_sigreturn() system call as it needs to unwind the stack to
288 * restore preserved registers that may have been saved on the signal handler's
289 * call stack.
290 */
292 #define SIGTRAMP_SAVES \
293 .unwabi 3, 's'; /* mark this as a sigtramp handler (saves scratch regs) */ \
294 .unwabi @svr4, 's'; /* backwards compatibility with old unwinders (remove in v2.7) */ \
295 .savesp ar.unat, UNAT_OFF+SIGCONTEXT_OFF; \
296 .savesp ar.fpsr, FPSR_OFF+SIGCONTEXT_OFF; \
297 .savesp pr, PR_OFF+SIGCONTEXT_OFF; \
298 .savesp rp, RP_OFF+SIGCONTEXT_OFF; \
299 .savesp ar.pfs, CFM_OFF+SIGCONTEXT_OFF; \
300 .vframesp SP_OFF+SIGCONTEXT_OFF
302 GLOBAL_ENTRY(__kernel_sigtramp)
303 // describe the state that is active when we get here:
304 .prologue
305 SIGTRAMP_SAVES
306 .body
308 .label_state 1
310 adds base0=SIGHANDLER_OFF,sp
311 adds base1=RBS_BASE_OFF+SIGCONTEXT_OFF,sp
312 br.call.sptk.many rp=1f
313 1:
314 ld8 r17=[base0],(ARG0_OFF-SIGHANDLER_OFF) // get pointer to signal handler's plabel
315 ld8 r15=[base1] // get address of new RBS base (or NULL)
316 cover // push args in interrupted frame onto backing store
317 ;;
318 cmp.ne p1,p0=r15,r0 // do we need to switch rbs? (note: pr is saved by kernel)
319 mov.m r9=ar.bsp // fetch ar.bsp
320 .spillsp.p p1, ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
321 (p1) br.cond.spnt setup_rbs // yup -> (clobbers p8, r14-r16, and r18-r20)
322 back_from_setup_rbs:
323 alloc r8=ar.pfs,0,0,3,0
324 ld8 out0=[base0],16 // load arg0 (signum)
325 adds base1=(ARG1_OFF-(RBS_BASE_OFF+SIGCONTEXT_OFF)),base1
326 ;;
327 ld8 out1=[base1] // load arg1 (siginfop)
328 ld8 r10=[r17],8 // get signal handler entry point
329 ;;
330 ld8 out2=[base0] // load arg2 (sigcontextp)
331 ld8 gp=[r17] // get signal handler's global pointer
332 adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp
333 ;;
334 .spillsp ar.bsp, BSP_OFF+SIGCONTEXT_OFF
335 st8 [base0]=r9 // save sc_ar_bsp
336 adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp
337 adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp
338 ;;
339 stf.spill [base0]=f6,32
340 stf.spill [base1]=f7,32
341 ;;
342 stf.spill [base0]=f8,32
343 stf.spill [base1]=f9,32
344 mov b6=r10
345 ;;
346 stf.spill [base0]=f10,32
347 stf.spill [base1]=f11,32
348 ;;
349 stf.spill [base0]=f12,32
350 stf.spill [base1]=f13,32
351 ;;
352 stf.spill [base0]=f14,32
353 stf.spill [base1]=f15,32
354 br.call.sptk.many rp=b6 // call the signal handler
355 .ret0: adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp
356 ;;
357 ld8 r15=[base0] // fetch sc_ar_bsp
358 mov r14=ar.bsp
359 ;;
360 cmp.ne p1,p0=r14,r15 // do we need to restore the rbs?
361 (p1) br.cond.spnt restore_rbs // yup -> (clobbers r14-r18, f6 & f7)
362 ;;
363 back_from_restore_rbs:
364 adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp
365 adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp
366 ;;
367 ldf.fill f6=[base0],32
368 ldf.fill f7=[base1],32
369 ;;
370 ldf.fill f8=[base0],32
371 ldf.fill f9=[base1],32
372 ;;
373 ldf.fill f10=[base0],32
374 ldf.fill f11=[base1],32
375 ;;
376 ldf.fill f12=[base0],32
377 ldf.fill f13=[base1],32
378 ;;
379 ldf.fill f14=[base0],32
380 ldf.fill f15=[base1],32
381 mov r15=__NR_rt_sigreturn
382 .restore sp // pop .prologue
383 break __BREAK_SYSCALL
385 .prologue
386 SIGTRAMP_SAVES
387 setup_rbs:
388 mov ar.rsc=0 // put RSE into enforced lazy mode
389 ;;
390 .save ar.rnat, r19
391 mov r19=ar.rnat // save RNaT before switching backing store area
392 adds r14=(RNAT_OFF+SIGCONTEXT_OFF),sp
394 mov r18=ar.bspstore
395 mov ar.bspstore=r15 // switch over to new register backing store area
396 ;;
398 .spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
399 st8 [r14]=r19 // save sc_ar_rnat
400 .body
401 mov.m r16=ar.bsp // sc_loadrs <- (new bsp - new bspstore) << 16
402 adds r14=(LOADRS_OFF+SIGCONTEXT_OFF),sp
403 ;;
404 invala
405 sub r15=r16,r15
406 extr.u r20=r18,3,6
407 ;;
408 mov ar.rsc=0xf // set RSE into eager mode, pl 3
409 cmp.eq p8,p0=63,r20
410 shl r15=r15,16
411 ;;
412 st8 [r14]=r15 // save sc_loadrs
413 (p8) st8 [r18]=r19 // if bspstore points at RNaT slot, store RNaT there now
414 .restore sp // pop .prologue
415 br.cond.sptk back_from_setup_rbs
417 .prologue
418 SIGTRAMP_SAVES
419 .spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
420 .body
421 restore_rbs:
422 // On input:
423 // r14 = bsp1 (bsp at the time of return from signal handler)
424 // r15 = bsp0 (bsp at the time the signal occurred)
425 //
426 // Here, we need to calculate bspstore0, the value that ar.bspstore needs
427 // to be set to, based on bsp0 and the size of the dirty partition on
428 // the alternate stack (sc_loadrs >> 16). This can be done with the
429 // following algorithm:
430 //
431 // bspstore0 = rse_skip_regs(bsp0, -rse_num_regs(bsp1 - (loadrs >> 19), bsp1));
432 //
433 // This is what the code below does.
434 //
435 alloc r2=ar.pfs,0,0,0,0 // alloc null frame
436 adds r16=(LOADRS_OFF+SIGCONTEXT_OFF),sp
437 adds r18=(RNAT_OFF+SIGCONTEXT_OFF),sp
438 ;;
439 ld8 r17=[r16]
440 ld8 r16=[r18] // get new rnat
441 extr.u r18=r15,3,6 // r18 <- rse_slot_num(bsp0)
442 ;;
443 mov ar.rsc=r17 // put RSE into enforced lazy mode
444 shr.u r17=r17,16
445 ;;
446 sub r14=r14,r17 // r14 (bspstore1) <- bsp1 - (sc_loadrs >> 16)
447 shr.u r17=r17,3 // r17 <- (sc_loadrs >> 19)
448 ;;
449 loadrs // restore dirty partition
450 extr.u r14=r14,3,6 // r14 <- rse_slot_num(bspstore1)
451 ;;
452 add r14=r14,r17 // r14 <- rse_slot_num(bspstore1) + (sc_loadrs >> 19)
453 ;;
454 shr.u r14=r14,6 // r14 <- (rse_slot_num(bspstore1) + (sc_loadrs >> 19))/0x40
455 ;;
456 sub r14=r14,r17 // r14 <- -rse_num_regs(bspstore1, bsp1)
457 movl r17=0x8208208208208209
458 ;;
459 add r18=r18,r14 // r18 (delta) <- rse_slot_num(bsp0) - rse_num_regs(bspstore1,bsp1)
460 setf.sig f7=r17
461 cmp.lt p7,p0=r14,r0 // p7 <- (r14 < 0)?
462 ;;
463 (p7) adds r18=-62,r18 // delta -= 62
464 ;;
465 setf.sig f6=r18
466 ;;
467 xmpy.h f6=f6,f7
468 ;;
469 getf.sig r17=f6
470 ;;
471 add r17=r17,r18
472 shr r18=r18,63
473 ;;
474 shr r17=r17,5
475 ;;
476 sub r17=r17,r18 // r17 = delta/63
477 ;;
478 add r17=r14,r17 // r17 <- delta/63 - rse_num_regs(bspstore1, bsp1)
479 ;;
480 shladd r15=r17,3,r15 // r15 <- bsp0 + 8*(delta/63 - rse_num_regs(bspstore1, bsp1))
481 ;;
482 mov ar.bspstore=r15 // switch back to old register backing store area
483 ;;
484 mov ar.rnat=r16 // restore RNaT
485 mov ar.rsc=0xf // (will be restored later on from sc_ar_rsc)
486 // invala not necessary as that will happen when returning to user-mode
487 br.cond.sptk back_from_restore_rbs
488 END(__kernel_sigtramp)