ia64/xen-unstable

view extras/mini-os/hypervisor.c @ 16536:89e7031e153c

hvm: Initialize vlapic->timer_last_update.

Without the fix, before the first vlapic timer interrupt is injected,
the "vlapic->timer_last_update" in vlapic_get_tmcct() is always 0,
causing a wrong value of counter_passed.

Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Dec 05 14:01:39 2007 +0000 (2007-12-05)
parents ee519207734f
children e35a379e7fe9
line source
1 /******************************************************************************
2 * hypervisor.c
3 *
4 * Communication to/from hypervisor.
5 *
6 * Copyright (c) 2002-2003, K A Fraser
7 * Copyright (c) 2005, Grzegorz Milos, gm281@cam.ac.uk,Intel Research Cambridge
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to
11 * deal in the Software without restriction, including without limitation the
12 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
13 * sell copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
22 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 */
28 #include <os.h>
29 #include <hypervisor.h>
30 #include <events.h>
32 #define active_evtchns(cpu,sh,idx) \
33 ((sh)->evtchn_pending[idx] & \
34 ~(sh)->evtchn_mask[idx])
36 int in_callback;
38 void do_hypervisor_callback(struct pt_regs *regs)
39 {
40 unsigned long l1, l2, l1i, l2i;
41 unsigned int port;
42 int cpu = 0;
43 shared_info_t *s = HYPERVISOR_shared_info;
44 vcpu_info_t *vcpu_info = &s->vcpu_info[cpu];
46 in_callback = 1;
48 vcpu_info->evtchn_upcall_pending = 0;
49 /* NB. No need for a barrier here -- XCHG is a barrier on x86. */
50 l1 = xchg(&vcpu_info->evtchn_pending_sel, 0);
51 while ( l1 != 0 )
52 {
53 l1i = __ffs(l1);
54 l1 &= ~(1 << l1i);
56 while ( (l2 = active_evtchns(cpu, s, l1i)) != 0 )
57 {
58 l2i = __ffs(l2);
59 l2 &= ~(1 << l2i);
61 port = (l1i << 5) + l2i;
62 do_event(port, regs);
63 }
64 }
66 in_callback = 0;
67 }
70 inline void mask_evtchn(u32 port)
71 {
72 shared_info_t *s = HYPERVISOR_shared_info;
73 synch_set_bit(port, &s->evtchn_mask[0]);
74 }
76 inline void unmask_evtchn(u32 port)
77 {
78 shared_info_t *s = HYPERVISOR_shared_info;
79 vcpu_info_t *vcpu_info = &s->vcpu_info[smp_processor_id()];
81 synch_clear_bit(port, &s->evtchn_mask[0]);
83 /*
84 * The following is basically the equivalent of 'hw_resend_irq'. Just like
85 * a real IO-APIC we 'lose the interrupt edge' if the channel is masked.
86 */
87 if ( synch_test_bit (port, &s->evtchn_pending[0]) &&
88 !synch_test_and_set_bit(port>>5, &vcpu_info->evtchn_pending_sel) )
89 {
90 vcpu_info->evtchn_upcall_pending = 1;
91 if ( !vcpu_info->evtchn_upcall_mask )
92 force_evtchn_callback();
93 }
94 }
96 inline void clear_evtchn(u32 port)
97 {
98 shared_info_t *s = HYPERVISOR_shared_info;
99 synch_clear_bit(port, &s->evtchn_pending[0]);
100 }