ia64/xen-unstable

view xen/arch/ia64/xen/vcpu.c @ 13065:893b786cc66a

[IA64] Mask out reserved bits to avoid Reserved Register/Field faults.

Signed-off-by: Dietmar Hahn <dietmar.hahn@fujitsu-siemens.com>
author awilliam@xenbuild2.aw
date Mon Dec 18 10:04:49 2006 -0700 (2006-12-18)
parents 05d227d81935
children a50fd1fed61e
line source
1 /*
2 * Virtualized CPU functions
3 *
4 * Copyright (C) 2004-2005 Hewlett-Packard Co.
5 * Dan Magenheimer (dan.magenheimer@hp.com)
6 *
7 */
9 #include <linux/sched.h>
10 #include <public/xen.h>
11 #include <xen/mm.h>
12 #include <asm/ia64_int.h>
13 #include <asm/vcpu.h>
14 #include <asm/regionreg.h>
15 #include <asm/tlb.h>
16 #include <asm/processor.h>
17 #include <asm/delay.h>
18 #include <asm/vmx_vcpu.h>
19 #include <asm/vhpt.h>
20 #include <asm/tlbflush.h>
21 #include <asm/privop.h>
22 #include <xen/event.h>
23 #include <asm/vmx_phy_mode.h>
24 #include <asm/bundle.h>
25 #include <asm/privop_stat.h>
26 #include <asm/uaccess.h>
27 #include <asm/p2m_entry.h>
28 #include <asm/tlb_track.h>
30 /* FIXME: where these declarations should be there ? */
31 extern void getreg(unsigned long regnum, unsigned long *val, int *nat,
32 struct pt_regs *regs);
33 extern void setreg(unsigned long regnum, unsigned long val, int nat,
34 struct pt_regs *regs);
35 extern void getfpreg(unsigned long regnum, struct ia64_fpreg *fpval,
36 struct pt_regs *regs);
38 extern void setfpreg(unsigned long regnum, struct ia64_fpreg *fpval,
39 struct pt_regs *regs);
41 typedef union {
42 struct ia64_psr ia64_psr;
43 unsigned long i64;
44 } PSR;
46 // this def for vcpu_regs won't work if kernel stack is present
47 //#define vcpu_regs(vcpu) ((struct pt_regs *) vcpu->arch.regs
49 #define IA64_PTA_SZ_BIT 2
50 #define IA64_PTA_VF_BIT 8
51 #define IA64_PTA_BASE_BIT 15
52 #define IA64_PTA_LFMT (1UL << IA64_PTA_VF_BIT)
53 #define IA64_PTA_SZ(x) (x##UL << IA64_PTA_SZ_BIT)
55 unsigned long vcpu_verbose = 0;
57 /**************************************************************************
58 VCPU general register access routines
59 **************************************************************************/
60 #ifdef XEN
61 u64 vcpu_get_gr(VCPU * vcpu, unsigned long reg)
62 {
63 REGS *regs = vcpu_regs(vcpu);
64 u64 val;
66 if (!reg)
67 return 0;
68 getreg(reg, &val, 0, regs); // FIXME: handle NATs later
69 return val;
70 }
72 IA64FAULT vcpu_get_gr_nat(VCPU * vcpu, unsigned long reg, u64 * val)
73 {
74 REGS *regs = vcpu_regs(vcpu);
75 int nat;
77 getreg(reg, val, &nat, regs); // FIXME: handle NATs later
78 if (nat)
79 return IA64_NAT_CONSUMPTION_VECTOR;
80 return 0;
81 }
83 // returns:
84 // IA64_ILLOP_FAULT if the register would cause an Illegal Operation fault
85 // IA64_NO_FAULT otherwise
86 IA64FAULT vcpu_set_gr(VCPU * vcpu, unsigned long reg, u64 value, int nat)
87 {
88 REGS *regs = vcpu_regs(vcpu);
89 long sof = (regs->cr_ifs) & 0x7f;
91 if (!reg)
92 return IA64_ILLOP_FAULT;
93 if (reg >= sof + 32)
94 return IA64_ILLOP_FAULT;
95 setreg(reg, value, nat, regs); // FIXME: handle NATs later
96 return IA64_NO_FAULT;
97 }
99 IA64FAULT
100 vcpu_get_fpreg(VCPU * vcpu, unsigned long reg, struct ia64_fpreg * val)
101 {
102 REGS *regs = vcpu_regs(vcpu);
103 getfpreg(reg, val, regs); // FIXME: handle NATs later
104 return IA64_NO_FAULT;
105 }
107 IA64FAULT
108 vcpu_set_fpreg(VCPU * vcpu, unsigned long reg, struct ia64_fpreg * val)
109 {
110 REGS *regs = vcpu_regs(vcpu);
111 if (reg > 1)
112 setfpreg(reg, val, regs); // FIXME: handle NATs later
113 return IA64_NO_FAULT;
114 }
116 #else
117 // returns:
118 // IA64_ILLOP_FAULT if the register would cause an Illegal Operation fault
119 // IA64_NO_FAULT otherwise
120 IA64FAULT vcpu_set_gr(VCPU * vcpu, unsigned long reg, u64 value)
121 {
122 REGS *regs = vcpu_regs(vcpu);
123 long sof = (regs->cr_ifs) & 0x7f;
125 if (!reg)
126 return IA64_ILLOP_FAULT;
127 if (reg >= sof + 32)
128 return IA64_ILLOP_FAULT;
129 setreg(reg, value, 0, regs); // FIXME: handle NATs later
130 return IA64_NO_FAULT;
131 }
133 #endif
135 void vcpu_init_regs(struct vcpu *v)
136 {
137 struct pt_regs *regs;
139 regs = vcpu_regs(v);
140 if (VMX_DOMAIN(v)) {
141 /* dt/rt/it:1;i/ic:1, si:1, vm/bn:1, ac:1 */
142 /* Need to be expanded as macro */
143 regs->cr_ipsr = 0x501008826008;
144 } else {
145 regs->cr_ipsr = ia64_getreg(_IA64_REG_PSR)
146 | IA64_PSR_BITS_TO_SET | IA64_PSR_BN;
147 regs->cr_ipsr &= ~(IA64_PSR_BITS_TO_CLEAR
148 | IA64_PSR_RI | IA64_PSR_IS);
149 // domain runs at PL2
150 regs->cr_ipsr |= 2UL << IA64_PSR_CPL0_BIT;
151 }
152 regs->cr_ifs = 1UL << 63; /* or clear? */
153 regs->ar_fpsr = FPSR_DEFAULT;
155 if (VMX_DOMAIN(v)) {
156 vmx_init_all_rr(v);
157 /* Virtual processor context setup */
158 VCPU(v, vpsr) = IA64_PSR_BN;
159 VCPU(v, dcr) = 0;
160 } else {
161 init_all_rr(v);
162 regs->ar_rsc |= (2 << 2); /* force PL2/3 */
163 VCPU(v, banknum) = 1;
164 VCPU(v, metaphysical_mode) = 1;
165 VCPU(v, interrupt_mask_addr) =
166 (unsigned char *)v->domain->arch.shared_info_va +
167 INT_ENABLE_OFFSET(v);
168 VCPU(v, itv) = (1 << 16); /* timer vector masked */
169 }
171 v->arch.domain_itm_last = -1L;
172 }
174 /**************************************************************************
175 VCPU privileged application register access routines
176 **************************************************************************/
178 void vcpu_load_kernel_regs(VCPU * vcpu)
179 {
180 ia64_set_kr(0, VCPU(vcpu, krs[0]));
181 ia64_set_kr(1, VCPU(vcpu, krs[1]));
182 ia64_set_kr(2, VCPU(vcpu, krs[2]));
183 ia64_set_kr(3, VCPU(vcpu, krs[3]));
184 ia64_set_kr(4, VCPU(vcpu, krs[4]));
185 ia64_set_kr(5, VCPU(vcpu, krs[5]));
186 ia64_set_kr(6, VCPU(vcpu, krs[6]));
187 ia64_set_kr(7, VCPU(vcpu, krs[7]));
188 }
190 /* GCC 4.0.2 seems not to be able to suppress this call!. */
191 #define ia64_setreg_unknown_kr() return IA64_ILLOP_FAULT
193 IA64FAULT vcpu_set_ar(VCPU * vcpu, u64 reg, u64 val)
194 {
195 if (reg == 44)
196 return vcpu_set_itc(vcpu, val);
197 else if (reg == 27)
198 return IA64_ILLOP_FAULT;
199 else if (reg == 24)
200 printk("warning: setting ar.eflg is a no-op; no IA-32 "
201 "support\n");
202 else if (reg > 7)
203 return IA64_ILLOP_FAULT;
204 else {
205 PSCB(vcpu, krs[reg]) = val;
206 ia64_set_kr(reg, val);
207 }
208 return IA64_NO_FAULT;
209 }
211 IA64FAULT vcpu_get_ar(VCPU * vcpu, u64 reg, u64 * val)
212 {
213 if (reg == 24)
214 printk("warning: getting ar.eflg is a no-op; no IA-32 "
215 "support\n");
216 else if (reg > 7)
217 return IA64_ILLOP_FAULT;
218 else
219 *val = PSCB(vcpu, krs[reg]);
220 return IA64_NO_FAULT;
221 }
223 /**************************************************************************
224 VCPU processor status register access routines
225 **************************************************************************/
227 void vcpu_set_metaphysical_mode(VCPU * vcpu, BOOLEAN newmode)
228 {
229 /* only do something if mode changes */
230 if (!!newmode ^ !!PSCB(vcpu, metaphysical_mode)) {
231 PSCB(vcpu, metaphysical_mode) = newmode;
232 if (newmode)
233 set_metaphysical_rr0();
234 else if (PSCB(vcpu, rrs[0]) != -1)
235 set_one_rr(0, PSCB(vcpu, rrs[0]));
236 }
237 }
239 IA64FAULT vcpu_reset_psr_dt(VCPU * vcpu)
240 {
241 vcpu_set_metaphysical_mode(vcpu, TRUE);
242 return IA64_NO_FAULT;
243 }
245 IA64FAULT vcpu_reset_psr_sm(VCPU * vcpu, u64 imm24)
246 {
247 struct ia64_psr psr, imm, *ipsr;
248 REGS *regs = vcpu_regs(vcpu);
250 //PRIVOP_COUNT_ADDR(regs,_RSM);
251 // TODO: All of these bits need to be virtualized
252 // TODO: Only allowed for current vcpu
253 __asm__ __volatile("mov %0=psr;;":"=r"(psr)::"memory");
254 ipsr = (struct ia64_psr *)&regs->cr_ipsr;
255 imm = *(struct ia64_psr *)&imm24;
256 // interrupt flag
257 if (imm.i)
258 vcpu->vcpu_info->evtchn_upcall_mask = 1;
259 if (imm.ic)
260 PSCB(vcpu, interrupt_collection_enabled) = 0;
261 // interrupt collection flag
262 //if (imm.ic) PSCB(vcpu,interrupt_delivery_enabled) = 0;
263 // just handle psr.up and psr.pp for now
264 if (imm24 & ~(IA64_PSR_BE | IA64_PSR_PP | IA64_PSR_UP | IA64_PSR_SP |
265 IA64_PSR_I | IA64_PSR_IC | IA64_PSR_DT |
266 IA64_PSR_DFL | IA64_PSR_DFH))
267 return IA64_ILLOP_FAULT;
268 if (imm.dfh)
269 ipsr->dfh = 0;
270 if (imm.dfl)
271 ipsr->dfl = 0;
272 if (imm.pp) {
273 ipsr->pp = 1;
274 psr.pp = 1; // priv perf ctrs always enabled
275 PSCB(vcpu, vpsr_pp) = 0; // but fool the domain if it gets psr
276 }
277 if (imm.up) {
278 ipsr->up = 0;
279 psr.up = 0;
280 }
281 if (imm.sp) {
282 ipsr->sp = 0;
283 psr.sp = 0;
284 }
285 if (imm.be)
286 ipsr->be = 0;
287 if (imm.dt)
288 vcpu_set_metaphysical_mode(vcpu, TRUE);
289 __asm__ __volatile(";; mov psr.l=%0;; srlz.d"::"r"(psr):"memory");
290 return IA64_NO_FAULT;
291 }
293 IA64FAULT vcpu_set_psr_dt(VCPU * vcpu)
294 {
295 vcpu_set_metaphysical_mode(vcpu, FALSE);
296 return IA64_NO_FAULT;
297 }
299 IA64FAULT vcpu_set_psr_i(VCPU * vcpu)
300 {
301 vcpu->vcpu_info->evtchn_upcall_mask = 0;
302 PSCB(vcpu, interrupt_collection_enabled) = 1;
303 return IA64_NO_FAULT;
304 }
306 IA64FAULT vcpu_set_psr_sm(VCPU * vcpu, u64 imm24)
307 {
308 struct ia64_psr psr, imm, *ipsr;
309 REGS *regs = vcpu_regs(vcpu);
310 u64 mask, enabling_interrupts = 0;
312 //PRIVOP_COUNT_ADDR(regs,_SSM);
313 // TODO: All of these bits need to be virtualized
314 __asm__ __volatile("mov %0=psr;;":"=r"(psr)::"memory");
315 imm = *(struct ia64_psr *)&imm24;
316 ipsr = (struct ia64_psr *)&regs->cr_ipsr;
317 // just handle psr.sp,pp and psr.i,ic (and user mask) for now
318 mask =
319 IA64_PSR_PP | IA64_PSR_SP | IA64_PSR_I | IA64_PSR_IC | IA64_PSR_UM |
320 IA64_PSR_DT | IA64_PSR_DFL | IA64_PSR_DFH;
321 if (imm24 & ~mask)
322 return IA64_ILLOP_FAULT;
323 if (imm.dfh)
324 ipsr->dfh = 1;
325 if (imm.dfl)
326 ipsr->dfl = 1;
327 if (imm.pp) {
328 ipsr->pp = 1;
329 psr.pp = 1;
330 PSCB(vcpu, vpsr_pp) = 1;
331 }
332 if (imm.sp) {
333 ipsr->sp = 1;
334 psr.sp = 1;
335 }
336 if (imm.i) {
337 if (vcpu->vcpu_info->evtchn_upcall_mask) {
338 //printk("vcpu_set_psr_sm: psr.ic 0->1\n");
339 enabling_interrupts = 1;
340 }
341 vcpu->vcpu_info->evtchn_upcall_mask = 0;
342 }
343 if (imm.ic)
344 PSCB(vcpu, interrupt_collection_enabled) = 1;
345 // TODO: do this faster
346 if (imm.mfl) {
347 ipsr->mfl = 1;
348 psr.mfl = 1;
349 }
350 if (imm.mfh) {
351 ipsr->mfh = 1;
352 psr.mfh = 1;
353 }
354 if (imm.ac) {
355 ipsr->ac = 1;
356 psr.ac = 1;
357 }
358 if (imm.up) {
359 ipsr->up = 1;
360 psr.up = 1;
361 }
362 if (imm.be) {
363 printk("*** DOMAIN TRYING TO TURN ON BIG-ENDIAN!!!\n");
364 return IA64_ILLOP_FAULT;
365 }
366 if (imm.dt)
367 vcpu_set_metaphysical_mode(vcpu, FALSE);
368 __asm__ __volatile(";; mov psr.l=%0;; srlz.d"::"r"(psr):"memory");
369 if (enabling_interrupts &&
370 vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
371 PSCB(vcpu, pending_interruption) = 1;
372 return IA64_NO_FAULT;
373 }
375 IA64FAULT vcpu_set_psr_l(VCPU * vcpu, u64 val)
376 {
377 struct ia64_psr psr, newpsr, *ipsr;
378 REGS *regs = vcpu_regs(vcpu);
379 u64 enabling_interrupts = 0;
381 // TODO: All of these bits need to be virtualized
382 __asm__ __volatile("mov %0=psr;;":"=r"(psr)::"memory");
383 newpsr = *(struct ia64_psr *)&val;
384 ipsr = (struct ia64_psr *)&regs->cr_ipsr;
385 // just handle psr.up and psr.pp for now
386 //if (val & ~(IA64_PSR_PP | IA64_PSR_UP | IA64_PSR_SP))
387 // return IA64_ILLOP_FAULT;
388 // however trying to set other bits can't be an error as it is in ssm
389 if (newpsr.dfh)
390 ipsr->dfh = 1;
391 if (newpsr.dfl)
392 ipsr->dfl = 1;
393 if (newpsr.pp) {
394 ipsr->pp = 1;
395 psr.pp = 1;
396 PSCB(vcpu, vpsr_pp) = 1;
397 } else {
398 ipsr->pp = 1;
399 psr.pp = 1;
400 PSCB(vcpu, vpsr_pp) = 0;
401 }
402 if (newpsr.up) {
403 ipsr->up = 1;
404 psr.up = 1;
405 }
406 if (newpsr.sp) {
407 ipsr->sp = 1;
408 psr.sp = 1;
409 }
410 if (newpsr.i) {
411 if (vcpu->vcpu_info->evtchn_upcall_mask)
412 enabling_interrupts = 1;
413 vcpu->vcpu_info->evtchn_upcall_mask = 0;
414 }
415 if (newpsr.ic)
416 PSCB(vcpu, interrupt_collection_enabled) = 1;
417 if (newpsr.mfl) {
418 ipsr->mfl = 1;
419 psr.mfl = 1;
420 }
421 if (newpsr.mfh) {
422 ipsr->mfh = 1;
423 psr.mfh = 1;
424 }
425 if (newpsr.ac) {
426 ipsr->ac = 1;
427 psr.ac = 1;
428 }
429 if (newpsr.up) {
430 ipsr->up = 1;
431 psr.up = 1;
432 }
433 if (newpsr.dt && newpsr.rt)
434 vcpu_set_metaphysical_mode(vcpu, FALSE);
435 else
436 vcpu_set_metaphysical_mode(vcpu, TRUE);
437 if (newpsr.be) {
438 printk("*** DOMAIN TRYING TO TURN ON BIG-ENDIAN!!!\n");
439 return IA64_ILLOP_FAULT;
440 }
441 if (enabling_interrupts &&
442 vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
443 PSCB(vcpu, pending_interruption) = 1;
444 return IA64_NO_FAULT;
445 }
447 IA64FAULT vcpu_get_psr(VCPU * vcpu, u64 * pval)
448 {
449 REGS *regs = vcpu_regs(vcpu);
450 struct ia64_psr newpsr;
452 newpsr = *(struct ia64_psr *)&regs->cr_ipsr;
453 if (newpsr.cpl == 2)
454 newpsr.cpl = 0;
455 if (!vcpu->vcpu_info->evtchn_upcall_mask)
456 newpsr.i = 1;
457 else
458 newpsr.i = 0;
459 if (PSCB(vcpu, interrupt_collection_enabled))
460 newpsr.ic = 1;
461 else
462 newpsr.ic = 0;
463 if (PSCB(vcpu, metaphysical_mode))
464 newpsr.dt = 0;
465 else
466 newpsr.dt = 1;
467 if (PSCB(vcpu, vpsr_pp))
468 newpsr.pp = 1;
469 else
470 newpsr.pp = 0;
471 *pval = *(unsigned long *)&newpsr;
472 return IA64_NO_FAULT;
473 }
475 BOOLEAN vcpu_get_psr_ic(VCPU * vcpu)
476 {
477 return !!PSCB(vcpu, interrupt_collection_enabled);
478 }
480 BOOLEAN vcpu_get_psr_i(VCPU * vcpu)
481 {
482 return !vcpu->vcpu_info->evtchn_upcall_mask;
483 }
485 u64 vcpu_get_ipsr_int_state(VCPU * vcpu, u64 prevpsr)
486 {
487 u64 dcr = PSCBX(vcpu, dcr);
488 PSR psr;
490 //printk("*** vcpu_get_ipsr_int_state (0x%016lx)...\n",prevpsr);
491 psr.i64 = prevpsr;
492 psr.ia64_psr.be = 0;
493 if (dcr & IA64_DCR_BE)
494 psr.ia64_psr.be = 1;
495 psr.ia64_psr.pp = 0;
496 if (dcr & IA64_DCR_PP)
497 psr.ia64_psr.pp = 1;
498 psr.ia64_psr.ic = PSCB(vcpu, interrupt_collection_enabled);
499 psr.ia64_psr.i = !vcpu->vcpu_info->evtchn_upcall_mask;
500 psr.ia64_psr.bn = PSCB(vcpu, banknum);
501 psr.ia64_psr.dt = 1;
502 psr.ia64_psr.it = 1;
503 psr.ia64_psr.rt = 1;
504 if (psr.ia64_psr.cpl == 2)
505 psr.ia64_psr.cpl = 0; // !!!! fool domain
506 // psr.pk = 1;
507 //printk("returns 0x%016lx...\n",psr.i64);
508 return psr.i64;
509 }
511 /**************************************************************************
512 VCPU control register access routines
513 **************************************************************************/
515 IA64FAULT vcpu_get_dcr(VCPU * vcpu, u64 * pval)
516 {
517 //verbose("vcpu_get_dcr: called @%p\n",PSCB(vcpu,iip));
518 // Reads of cr.dcr on Xen always have the sign bit set, so
519 // a domain can differentiate whether it is running on SP or not
520 *pval = PSCBX(vcpu, dcr) | 0x8000000000000000L;
521 return IA64_NO_FAULT;
522 }
524 IA64FAULT vcpu_get_iva(VCPU * vcpu, u64 * pval)
525 {
526 if (VMX_DOMAIN(vcpu))
527 *pval = PSCB(vcpu, iva) & ~0x7fffL;
528 else
529 *pval = PSCBX(vcpu, iva) & ~0x7fffL;
531 return IA64_NO_FAULT;
532 }
534 IA64FAULT vcpu_get_pta(VCPU * vcpu, u64 * pval)
535 {
536 *pval = PSCB(vcpu, pta);
537 return IA64_NO_FAULT;
538 }
540 IA64FAULT vcpu_get_ipsr(VCPU * vcpu, u64 * pval)
541 {
542 //REGS *regs = vcpu_regs(vcpu);
543 //*pval = regs->cr_ipsr;
544 *pval = PSCB(vcpu, ipsr);
545 return IA64_NO_FAULT;
546 }
548 IA64FAULT vcpu_get_isr(VCPU * vcpu, u64 * pval)
549 {
550 *pval = PSCB(vcpu, isr);
551 return IA64_NO_FAULT;
552 }
554 IA64FAULT vcpu_get_iip(VCPU * vcpu, u64 * pval)
555 {
556 //REGS *regs = vcpu_regs(vcpu);
557 //*pval = regs->cr_iip;
558 *pval = PSCB(vcpu, iip);
559 return IA64_NO_FAULT;
560 }
562 IA64FAULT vcpu_get_ifa(VCPU * vcpu, u64 * pval)
563 {
564 PRIVOP_COUNT_ADDR(vcpu_regs(vcpu), privop_inst_get_ifa);
565 *pval = PSCB(vcpu, ifa);
566 return IA64_NO_FAULT;
567 }
569 unsigned long vcpu_get_rr_ps(VCPU * vcpu, u64 vadr)
570 {
571 ia64_rr rr;
573 rr.rrval = PSCB(vcpu, rrs)[vadr >> 61];
574 return rr.ps;
575 }
577 unsigned long vcpu_get_rr_rid(VCPU * vcpu, u64 vadr)
578 {
579 ia64_rr rr;
581 rr.rrval = PSCB(vcpu, rrs)[vadr >> 61];
582 return rr.rid;
583 }
585 unsigned long vcpu_get_itir_on_fault(VCPU * vcpu, u64 ifa)
586 {
587 ia64_rr rr;
589 rr.rrval = 0;
590 rr.ps = vcpu_get_rr_ps(vcpu, ifa);
591 rr.rid = vcpu_get_rr_rid(vcpu, ifa);
592 return rr.rrval;
593 }
595 IA64FAULT vcpu_get_itir(VCPU * vcpu, u64 * pval)
596 {
597 u64 val = PSCB(vcpu, itir);
598 *pval = val;
599 return IA64_NO_FAULT;
600 }
602 IA64FAULT vcpu_get_iipa(VCPU * vcpu, u64 * pval)
603 {
604 u64 val = PSCB(vcpu, iipa);
605 // SP entry code does not save iipa yet nor does it get
606 // properly delivered in the pscb
607 // printk("*** vcpu_get_iipa: cr.iipa not fully implemented yet!!\n");
608 *pval = val;
609 return IA64_NO_FAULT;
610 }
612 IA64FAULT vcpu_get_ifs(VCPU * vcpu, u64 * pval)
613 {
614 //PSCB(vcpu,ifs) = PSCB(vcpu)->regs.cr_ifs;
615 //*pval = PSCB(vcpu,regs).cr_ifs;
616 *pval = PSCB(vcpu, ifs);
617 PSCB(vcpu, incomplete_regframe) = 0;
618 return IA64_NO_FAULT;
619 }
621 IA64FAULT vcpu_get_iim(VCPU * vcpu, u64 * pval)
622 {
623 u64 val = PSCB(vcpu, iim);
624 *pval = val;
625 return IA64_NO_FAULT;
626 }
628 IA64FAULT vcpu_get_iha(VCPU * vcpu, u64 * pval)
629 {
630 PRIVOP_COUNT_ADDR(vcpu_regs(vcpu), privop_inst_thash);
631 *pval = PSCB(vcpu, iha);
632 return IA64_NO_FAULT;
633 }
635 IA64FAULT vcpu_set_dcr(VCPU * vcpu, u64 val)
636 {
637 // Reads of cr.dcr on SP always have the sign bit set, so
638 // a domain can differentiate whether it is running on SP or not
639 // Thus, writes of DCR should ignore the sign bit
640 //verbose("vcpu_set_dcr: called\n");
641 PSCBX(vcpu, dcr) = val & ~0x8000000000000000L;
642 return IA64_NO_FAULT;
643 }
645 IA64FAULT vcpu_set_iva(VCPU * vcpu, u64 val)
646 {
647 if (VMX_DOMAIN(vcpu))
648 PSCB(vcpu, iva) = val & ~0x7fffL;
649 else
650 PSCBX(vcpu, iva) = val & ~0x7fffL;
652 return IA64_NO_FAULT;
653 }
655 IA64FAULT vcpu_set_pta(VCPU * vcpu, u64 val)
656 {
657 if (val & IA64_PTA_LFMT) {
658 printk("*** No support for VHPT long format yet!!\n");
659 return IA64_ILLOP_FAULT;
660 }
661 if (val & (0x3f << 9)) /* reserved fields */
662 return IA64_RSVDREG_FAULT;
663 if (val & 2) /* reserved fields */
664 return IA64_RSVDREG_FAULT;
665 PSCB(vcpu, pta) = val;
666 return IA64_NO_FAULT;
667 }
669 IA64FAULT vcpu_set_ipsr(VCPU * vcpu, u64 val)
670 {
671 PSCB(vcpu, ipsr) = val;
672 return IA64_NO_FAULT;
673 }
675 IA64FAULT vcpu_set_isr(VCPU * vcpu, u64 val)
676 {
677 PSCB(vcpu, isr) = val;
678 return IA64_NO_FAULT;
679 }
681 IA64FAULT vcpu_set_iip(VCPU * vcpu, u64 val)
682 {
683 PSCB(vcpu, iip) = val;
684 return IA64_NO_FAULT;
685 }
687 IA64FAULT vcpu_increment_iip(VCPU * vcpu)
688 {
689 REGS *regs = vcpu_regs(vcpu);
690 struct ia64_psr *ipsr = (struct ia64_psr *)&regs->cr_ipsr;
691 if (ipsr->ri == 2) {
692 ipsr->ri = 0;
693 regs->cr_iip += 16;
694 } else
695 ipsr->ri++;
696 return IA64_NO_FAULT;
697 }
699 IA64FAULT vcpu_set_ifa(VCPU * vcpu, u64 val)
700 {
701 PSCB(vcpu, ifa) = val;
702 return IA64_NO_FAULT;
703 }
705 IA64FAULT vcpu_set_itir(VCPU * vcpu, u64 val)
706 {
707 PSCB(vcpu, itir) = val;
708 return IA64_NO_FAULT;
709 }
711 IA64FAULT vcpu_set_iipa(VCPU * vcpu, u64 val)
712 {
713 // SP entry code does not save iipa yet nor does it get
714 // properly delivered in the pscb
715 // printk("*** vcpu_set_iipa: cr.iipa not fully implemented yet!!\n");
716 PSCB(vcpu, iipa) = val;
717 return IA64_NO_FAULT;
718 }
720 IA64FAULT vcpu_set_ifs(VCPU * vcpu, u64 val)
721 {
722 //REGS *regs = vcpu_regs(vcpu);
723 PSCB(vcpu, ifs) = val;
724 return IA64_NO_FAULT;
725 }
727 IA64FAULT vcpu_set_iim(VCPU * vcpu, u64 val)
728 {
729 PSCB(vcpu, iim) = val;
730 return IA64_NO_FAULT;
731 }
733 IA64FAULT vcpu_set_iha(VCPU * vcpu, u64 val)
734 {
735 PSCB(vcpu, iha) = val;
736 return IA64_NO_FAULT;
737 }
739 /**************************************************************************
740 VCPU interrupt control register access routines
741 **************************************************************************/
743 void vcpu_pend_unspecified_interrupt(VCPU * vcpu)
744 {
745 PSCB(vcpu, pending_interruption) = 1;
746 }
748 void vcpu_pend_interrupt(VCPU * vcpu, u64 vector)
749 {
750 if (vector & ~0xff) {
751 printk("vcpu_pend_interrupt: bad vector\n");
752 return;
753 }
755 if (vcpu->arch.event_callback_ip) {
756 printk("Deprecated interface. Move to new event based "
757 "solution\n");
758 return;
759 }
761 if (VMX_DOMAIN(vcpu)) {
762 set_bit(vector, VCPU(vcpu, irr));
763 } else {
764 set_bit(vector, PSCBX(vcpu, irr));
765 PSCB(vcpu, pending_interruption) = 1;
766 }
767 }
769 #define IA64_TPR_MMI 0x10000
770 #define IA64_TPR_MIC 0x000f0
772 /* checks to see if a VCPU has any unmasked pending interrupts
773 * if so, returns the highest, else returns SPURIOUS_VECTOR */
774 /* NOTE: Since this gets called from vcpu_get_ivr() and the
775 * semantics of "mov rx=cr.ivr" ignore the setting of the psr.i bit,
776 * this routine also ignores pscb.interrupt_delivery_enabled
777 * and this must be checked independently; see vcpu_deliverable interrupts() */
778 u64 vcpu_check_pending_interrupts(VCPU * vcpu)
779 {
780 u64 *p, *r, bits, bitnum, mask, i, vector;
782 if (vcpu->arch.event_callback_ip)
783 return SPURIOUS_VECTOR;
785 /* Always check pending event, since guest may just ack the
786 * event injection without handle. Later guest may throw out
787 * the event itself.
788 */
789 check_start:
790 if (event_pending(vcpu) &&
791 !test_bit(vcpu->domain->shared_info->arch.evtchn_vector,
792 &PSCBX(vcpu, insvc[0])))
793 vcpu_pend_interrupt(vcpu,
794 vcpu->domain->shared_info->arch.
795 evtchn_vector);
797 p = &PSCBX(vcpu, irr[3]);
798 r = &PSCBX(vcpu, insvc[3]);
799 for (i = 3 ;; p--, r--, i--) {
800 bits = *p;
801 if (bits)
802 break; // got a potential interrupt
803 if (*r) {
804 // nothing in this word which is pending+inservice
805 // but there is one inservice which masks lower
806 return SPURIOUS_VECTOR;
807 }
808 if (i == 0) {
809 // checked all bits... nothing pending+inservice
810 return SPURIOUS_VECTOR;
811 }
812 }
813 // have a pending,deliverable interrupt... see if it is masked
814 bitnum = ia64_fls(bits);
815 //printk("XXXXXXX vcpu_check_pending_interrupts: got bitnum=%p...\n",bitnum);
816 vector = bitnum + (i * 64);
817 mask = 1L << bitnum;
818 /* sanity check for guest timer interrupt */
819 if (vector == (PSCB(vcpu, itv) & 0xff)) {
820 uint64_t now = ia64_get_itc();
821 if (now < PSCBX(vcpu, domain_itm)) {
822 // printk("Ooops, pending guest timer before its due\n");
823 PSCBX(vcpu, irr[i]) &= ~mask;
824 goto check_start;
825 }
826 }
827 //printk("XXXXXXX vcpu_check_pending_interrupts: got vector=%p...\n",vector);
828 if (*r >= mask) {
829 // masked by equal inservice
830 //printk("but masked by equal inservice\n");
831 return SPURIOUS_VECTOR;
832 }
833 if (PSCB(vcpu, tpr) & IA64_TPR_MMI) {
834 // tpr.mmi is set
835 //printk("but masked by tpr.mmi\n");
836 return SPURIOUS_VECTOR;
837 }
838 if (((PSCB(vcpu, tpr) & IA64_TPR_MIC) + 15) >= vector) {
839 //tpr.mic masks class
840 //printk("but masked by tpr.mic\n");
841 return SPURIOUS_VECTOR;
842 }
843 //printk("returned to caller\n");
844 return vector;
845 }
847 u64 vcpu_deliverable_interrupts(VCPU * vcpu)
848 {
849 return (vcpu_get_psr_i(vcpu) &&
850 vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR);
851 }
853 u64 vcpu_deliverable_timer(VCPU * vcpu)
854 {
855 return (vcpu_get_psr_i(vcpu) &&
856 vcpu_check_pending_interrupts(vcpu) == PSCB(vcpu, itv));
857 }
859 IA64FAULT vcpu_get_lid(VCPU * vcpu, u64 * pval)
860 {
861 /* Use EID=0, ID=vcpu_id. */
862 *pval = vcpu->vcpu_id << 24;
863 return IA64_NO_FAULT;
864 }
866 IA64FAULT vcpu_get_ivr(VCPU * vcpu, u64 * pval)
867 {
868 int i;
869 u64 vector, mask;
871 #define HEARTBEAT_FREQ 16 // period in seconds
872 #ifdef HEARTBEAT_FREQ
873 #define N_DOMS 16 // period in seconds
874 #if 0
875 static long count[N_DOMS] = { 0 };
876 #endif
877 static long nonclockcount[N_DOMS] = { 0 };
878 unsigned domid = vcpu->domain->domain_id;
879 #endif
880 #ifdef IRQ_DEBUG
881 static char firstivr = 1;
882 static char firsttime[256];
883 if (firstivr) {
884 int i;
885 for (i = 0; i < 256; i++)
886 firsttime[i] = 1;
887 firstivr = 0;
888 }
889 #endif
891 vector = vcpu_check_pending_interrupts(vcpu);
892 if (vector == SPURIOUS_VECTOR) {
893 PSCB(vcpu, pending_interruption) = 0;
894 *pval = vector;
895 return IA64_NO_FAULT;
896 }
897 #ifdef HEARTBEAT_FREQ
898 if (domid >= N_DOMS)
899 domid = N_DOMS - 1;
900 #if 0
901 if (vector == (PSCB(vcpu, itv) & 0xff)) {
902 if (!(++count[domid] & ((HEARTBEAT_FREQ * 1024) - 1))) {
903 printk("Dom%d heartbeat... ticks=%lx,nonticks=%lx\n",
904 domid, count[domid], nonclockcount[domid]);
905 //count[domid] = 0;
906 //dump_runq();
907 }
908 }
909 #endif
910 else
911 nonclockcount[domid]++;
912 #endif
913 // now have an unmasked, pending, deliverable vector!
914 // getting ivr has "side effects"
915 #ifdef IRQ_DEBUG
916 if (firsttime[vector]) {
917 printk("*** First get_ivr on vector=%lu,itc=%lx\n",
918 vector, ia64_get_itc());
919 firsttime[vector] = 0;
920 }
921 #endif
922 /* if delivering a timer interrupt, remember domain_itm, which
923 * needs to be done before clearing irr
924 */
925 if (vector == (PSCB(vcpu, itv) & 0xff)) {
926 PSCBX(vcpu, domain_itm_last) = PSCBX(vcpu, domain_itm);
927 }
929 i = vector >> 6;
930 mask = 1L << (vector & 0x3f);
931 //printk("ZZZZZZ vcpu_get_ivr: setting insvc mask for vector %lu\n",vector);
932 PSCBX(vcpu, insvc[i]) |= mask;
933 PSCBX(vcpu, irr[i]) &= ~mask;
934 //PSCB(vcpu,pending_interruption)--;
935 *pval = vector;
936 return IA64_NO_FAULT;
937 }
939 IA64FAULT vcpu_get_tpr(VCPU * vcpu, u64 * pval)
940 {
941 *pval = PSCB(vcpu, tpr);
942 return IA64_NO_FAULT;
943 }
945 IA64FAULT vcpu_get_eoi(VCPU * vcpu, u64 * pval)
946 {
947 *pval = 0L; // reads of eoi always return 0
948 return IA64_NO_FAULT;
949 }
951 IA64FAULT vcpu_get_irr0(VCPU * vcpu, u64 * pval)
952 {
953 *pval = PSCBX(vcpu, irr[0]);
954 return IA64_NO_FAULT;
955 }
957 IA64FAULT vcpu_get_irr1(VCPU * vcpu, u64 * pval)
958 {
959 *pval = PSCBX(vcpu, irr[1]);
960 return IA64_NO_FAULT;
961 }
963 IA64FAULT vcpu_get_irr2(VCPU * vcpu, u64 * pval)
964 {
965 *pval = PSCBX(vcpu, irr[2]);
966 return IA64_NO_FAULT;
967 }
969 IA64FAULT vcpu_get_irr3(VCPU * vcpu, u64 * pval)
970 {
971 *pval = PSCBX(vcpu, irr[3]);
972 return IA64_NO_FAULT;
973 }
975 IA64FAULT vcpu_get_itv(VCPU * vcpu, u64 * pval)
976 {
977 *pval = PSCB(vcpu, itv);
978 return IA64_NO_FAULT;
979 }
981 IA64FAULT vcpu_get_pmv(VCPU * vcpu, u64 * pval)
982 {
983 *pval = PSCB(vcpu, pmv);
984 return IA64_NO_FAULT;
985 }
987 IA64FAULT vcpu_get_cmcv(VCPU * vcpu, u64 * pval)
988 {
989 *pval = PSCB(vcpu, cmcv);
990 return IA64_NO_FAULT;
991 }
993 IA64FAULT vcpu_get_lrr0(VCPU * vcpu, u64 * pval)
994 {
995 // fix this when setting values other than m-bit is supported
996 printk("vcpu_get_lrr0: Unmasked interrupts unsupported\n");
997 *pval = (1L << 16);
998 return IA64_NO_FAULT;
999 }
1001 IA64FAULT vcpu_get_lrr1(VCPU * vcpu, u64 * pval)
1003 // fix this when setting values other than m-bit is supported
1004 printk("vcpu_get_lrr1: Unmasked interrupts unsupported\n");
1005 *pval = (1L << 16);
1006 return IA64_NO_FAULT;
1009 IA64FAULT vcpu_set_lid(VCPU * vcpu, u64 val)
1011 printk("vcpu_set_lid: Setting cr.lid is unsupported\n");
1012 return IA64_ILLOP_FAULT;
1015 IA64FAULT vcpu_set_tpr(VCPU * vcpu, u64 val)
1017 if (val & 0xff00)
1018 return IA64_RSVDREG_FAULT;
1019 PSCB(vcpu, tpr) = val;
1020 /* This can unmask interrupts. */
1021 if (vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
1022 PSCB(vcpu, pending_interruption) = 1;
1023 return IA64_NO_FAULT;
1026 IA64FAULT vcpu_set_eoi(VCPU * vcpu, u64 val)
1028 u64 *p, bits, vec, bitnum;
1029 int i;
1031 p = &PSCBX(vcpu, insvc[3]);
1032 for (i = 3; (i >= 0) && !(bits = *p); i--, p--)
1034 if (i < 0) {
1035 printk("Trying to EOI interrupt when none are in-service.\n");
1036 return IA64_NO_FAULT;
1038 bitnum = ia64_fls(bits);
1039 vec = bitnum + (i * 64);
1040 /* clear the correct bit */
1041 bits &= ~(1L << bitnum);
1042 *p = bits;
1043 /* clearing an eoi bit may unmask another pending interrupt... */
1044 if (!vcpu->vcpu_info->evtchn_upcall_mask) { // but only if enabled...
1045 // worry about this later... Linux only calls eoi
1046 // with interrupts disabled
1047 printk("Trying to EOI interrupt with interrupts enabled\n");
1049 if (vcpu_check_pending_interrupts(vcpu) != SPURIOUS_VECTOR)
1050 PSCB(vcpu, pending_interruption) = 1;
1051 //printk("YYYYY vcpu_set_eoi: Successful\n");
1052 return IA64_NO_FAULT;
1055 IA64FAULT vcpu_set_lrr0(VCPU * vcpu, u64 val)
1057 if (!(val & (1L << 16))) {
1058 printk("vcpu_set_lrr0: Unmasked interrupts unsupported\n");
1059 return IA64_ILLOP_FAULT;
1061 // no place to save this state but nothing to do anyway
1062 return IA64_NO_FAULT;
1065 IA64FAULT vcpu_set_lrr1(VCPU * vcpu, u64 val)
1067 if (!(val & (1L << 16))) {
1068 printk("vcpu_set_lrr0: Unmasked interrupts unsupported\n");
1069 return IA64_ILLOP_FAULT;
1071 // no place to save this state but nothing to do anyway
1072 return IA64_NO_FAULT;
1075 IA64FAULT vcpu_set_itv(VCPU * vcpu, u64 val)
1077 /* Check reserved fields. */
1078 if (val & 0xef00)
1079 return IA64_ILLOP_FAULT;
1080 PSCB(vcpu, itv) = val;
1081 if (val & 0x10000) {
1082 /* Disable itm. */
1083 PSCBX(vcpu, domain_itm) = 0;
1084 } else
1085 vcpu_set_next_timer(vcpu);
1086 return IA64_NO_FAULT;
1089 IA64FAULT vcpu_set_pmv(VCPU * vcpu, u64 val)
1091 if (val & 0xef00) /* reserved fields */
1092 return IA64_RSVDREG_FAULT;
1093 PSCB(vcpu, pmv) = val;
1094 return IA64_NO_FAULT;
1097 IA64FAULT vcpu_set_cmcv(VCPU * vcpu, u64 val)
1099 if (val & 0xef00) /* reserved fields */
1100 return IA64_RSVDREG_FAULT;
1101 PSCB(vcpu, cmcv) = val;
1102 return IA64_NO_FAULT;
1105 /**************************************************************************
1106 VCPU temporary register access routines
1107 **************************************************************************/
1108 u64 vcpu_get_tmp(VCPU * vcpu, u64 index)
1110 if (index > 7)
1111 return 0;
1112 return PSCB(vcpu, tmp[index]);
1115 void vcpu_set_tmp(VCPU * vcpu, u64 index, u64 val)
1117 if (index <= 7)
1118 PSCB(vcpu, tmp[index]) = val;
1121 /**************************************************************************
1122 Interval timer routines
1123 **************************************************************************/
1125 BOOLEAN vcpu_timer_disabled(VCPU * vcpu)
1127 u64 itv = PSCB(vcpu, itv);
1128 return (!itv || !!(itv & 0x10000));
1131 BOOLEAN vcpu_timer_inservice(VCPU * vcpu)
1133 u64 itv = PSCB(vcpu, itv);
1134 return test_bit(itv, PSCBX(vcpu, insvc));
1137 BOOLEAN vcpu_timer_expired(VCPU * vcpu)
1139 unsigned long domain_itm = PSCBX(vcpu, domain_itm);
1140 unsigned long now = ia64_get_itc();
1142 if (!domain_itm)
1143 return FALSE;
1144 if (now < domain_itm)
1145 return FALSE;
1146 if (vcpu_timer_disabled(vcpu))
1147 return FALSE;
1148 return TRUE;
1151 void vcpu_safe_set_itm(unsigned long val)
1153 unsigned long epsilon = 100;
1154 unsigned long flags;
1155 u64 now = ia64_get_itc();
1157 local_irq_save(flags);
1158 while (1) {
1159 //printk("*** vcpu_safe_set_itm: Setting itm to %lx, itc=%lx\n",val,now);
1160 ia64_set_itm(val);
1161 if (val > (now = ia64_get_itc()))
1162 break;
1163 val = now + epsilon;
1164 epsilon <<= 1;
1166 local_irq_restore(flags);
1169 void vcpu_set_next_timer(VCPU * vcpu)
1171 u64 d = PSCBX(vcpu, domain_itm);
1172 //u64 s = PSCBX(vcpu,xen_itm);
1173 u64 s = local_cpu_data->itm_next;
1174 u64 now = ia64_get_itc();
1176 /* gloss over the wraparound problem for now... we know it exists
1177 * but it doesn't matter right now */
1179 if (is_idle_domain(vcpu->domain)) {
1180 // printk("****** vcpu_set_next_timer called during idle!!\n");
1181 vcpu_safe_set_itm(s);
1182 return;
1184 //s = PSCBX(vcpu,xen_itm);
1185 if (d && (d > now) && (d < s)) {
1186 vcpu_safe_set_itm(d);
1187 //using_domain_as_itm++;
1188 } else {
1189 vcpu_safe_set_itm(s);
1190 //using_xen_as_itm++;
1194 IA64FAULT vcpu_set_itm(VCPU * vcpu, u64 val)
1196 //UINT now = ia64_get_itc();
1198 //if (val < now) val = now + 1000;
1199 //printk("*** vcpu_set_itm: called with %lx\n",val);
1200 PSCBX(vcpu, domain_itm) = val;
1201 vcpu_set_next_timer(vcpu);
1202 return IA64_NO_FAULT;
1205 IA64FAULT vcpu_set_itc(VCPU * vcpu, u64 val)
1207 #define DISALLOW_SETTING_ITC_FOR_NOW
1208 #ifdef DISALLOW_SETTING_ITC_FOR_NOW
1209 static int did_print;
1210 if (!did_print) {
1211 printk("vcpu_set_itc: Setting ar.itc is currently disabled\n");
1212 printk("(this message is only displayed one)\n");
1213 did_print = 1;
1215 #else
1216 u64 oldnow = ia64_get_itc();
1217 u64 olditm = PSCBX(vcpu, domain_itm);
1218 unsigned long d = olditm - oldnow;
1219 unsigned long x = local_cpu_data->itm_next - oldnow;
1221 u64 newnow = val, min_delta;
1223 local_irq_disable();
1224 if (olditm) {
1225 printk("**** vcpu_set_itc(%lx): vitm changed to %lx\n", val,
1226 newnow + d);
1227 PSCBX(vcpu, domain_itm) = newnow + d;
1229 local_cpu_data->itm_next = newnow + x;
1230 d = PSCBX(vcpu, domain_itm);
1231 x = local_cpu_data->itm_next;
1233 ia64_set_itc(newnow);
1234 if (d && (d > newnow) && (d < x)) {
1235 vcpu_safe_set_itm(d);
1236 //using_domain_as_itm++;
1237 } else {
1238 vcpu_safe_set_itm(x);
1239 //using_xen_as_itm++;
1241 local_irq_enable();
1242 #endif
1243 return IA64_NO_FAULT;
1246 IA64FAULT vcpu_get_itm(VCPU * vcpu, u64 * pval)
1248 //FIXME: Implement this
1249 printk("vcpu_get_itm: Getting cr.itm is unsupported... continuing\n");
1250 return IA64_NO_FAULT;
1251 //return IA64_ILLOP_FAULT;
1254 IA64FAULT vcpu_get_itc(VCPU * vcpu, u64 * pval)
1256 //TODO: Implement this
1257 printk("vcpu_get_itc: Getting ar.itc is unsupported\n");
1258 return IA64_ILLOP_FAULT;
1261 void vcpu_pend_timer(VCPU * vcpu)
1263 u64 itv = PSCB(vcpu, itv) & 0xff;
1265 if (vcpu_timer_disabled(vcpu))
1266 return;
1267 //if (vcpu_timer_inservice(vcpu)) return;
1268 if (PSCBX(vcpu, domain_itm_last) == PSCBX(vcpu, domain_itm)) {
1269 // already delivered an interrupt for this so
1270 // don't deliver another
1271 return;
1273 if (vcpu->arch.event_callback_ip) {
1274 /* A small window may occur when injecting vIRQ while related
1275 * handler has not been registered. Don't fire in such case.
1276 */
1277 if (vcpu->virq_to_evtchn[VIRQ_ITC]) {
1278 send_guest_vcpu_virq(vcpu, VIRQ_ITC);
1279 PSCBX(vcpu, domain_itm_last) = PSCBX(vcpu, domain_itm);
1281 } else
1282 vcpu_pend_interrupt(vcpu, itv);
1285 // returns true if ready to deliver a timer interrupt too early
1286 u64 vcpu_timer_pending_early(VCPU * vcpu)
1288 u64 now = ia64_get_itc();
1289 u64 itm = PSCBX(vcpu, domain_itm);
1291 if (vcpu_timer_disabled(vcpu))
1292 return 0;
1293 if (!itm)
1294 return 0;
1295 return (vcpu_deliverable_timer(vcpu) && (now < itm));
1298 /**************************************************************************
1299 Privileged operation emulation routines
1300 **************************************************************************/
1302 static void vcpu_force_tlb_miss(VCPU * vcpu, u64 ifa)
1304 PSCB(vcpu, ifa) = ifa;
1305 PSCB(vcpu, itir) = vcpu_get_itir_on_fault(vcpu, ifa);
1306 vcpu_thash(current, ifa, &PSCB(current, iha));
1309 IA64FAULT vcpu_force_inst_miss(VCPU * vcpu, u64 ifa)
1311 vcpu_force_tlb_miss(vcpu, ifa);
1312 return vcpu_get_rr_ve(vcpu, ifa) ? IA64_INST_TLB_VECTOR :
1313 IA64_ALT_INST_TLB_VECTOR;
1316 IA64FAULT vcpu_force_data_miss(VCPU * vcpu, u64 ifa)
1318 vcpu_force_tlb_miss(vcpu, ifa);
1319 return vcpu_get_rr_ve(vcpu, ifa) ? IA64_DATA_TLB_VECTOR :
1320 IA64_ALT_DATA_TLB_VECTOR;
1323 IA64FAULT vcpu_rfi(VCPU * vcpu)
1325 // TODO: Only allowed for current vcpu
1326 PSR psr;
1327 u64 int_enable, regspsr = 0;
1328 u64 ifs;
1329 REGS *regs = vcpu_regs(vcpu);
1330 extern void dorfirfi(void);
1332 psr.i64 = PSCB(vcpu, ipsr);
1333 if (psr.ia64_psr.cpl < 3)
1334 psr.ia64_psr.cpl = 2;
1335 int_enable = psr.ia64_psr.i;
1336 if (psr.ia64_psr.ic)
1337 PSCB(vcpu, interrupt_collection_enabled) = 1;
1338 if (psr.ia64_psr.dt && psr.ia64_psr.rt && psr.ia64_psr.it)
1339 vcpu_set_metaphysical_mode(vcpu, FALSE);
1340 else
1341 vcpu_set_metaphysical_mode(vcpu, TRUE);
1342 psr.ia64_psr.ic = 1;
1343 psr.ia64_psr.i = 1;
1344 psr.ia64_psr.dt = 1;
1345 psr.ia64_psr.rt = 1;
1346 psr.ia64_psr.it = 1;
1347 psr.ia64_psr.bn = 1;
1348 //psr.pk = 1; // checking pkeys shouldn't be a problem but seems broken
1349 if (psr.ia64_psr.be) {
1350 printk("*** DOMAIN TRYING TO TURN ON BIG-ENDIAN!!!\n");
1351 return IA64_ILLOP_FAULT;
1353 PSCB(vcpu, incomplete_regframe) = 0; // is this necessary?
1354 ifs = PSCB(vcpu, ifs);
1355 //if ((ifs & regs->cr_ifs & 0x8000000000000000L) && ifs != regs->cr_ifs) {
1356 //if ((ifs & 0x8000000000000000L) && ifs != regs->cr_ifs) {
1357 if (ifs & regs->cr_ifs & 0x8000000000000000L) {
1358 // TODO: validate PSCB(vcpu,iip)
1359 // TODO: PSCB(vcpu,ipsr) = psr;
1360 PSCB(vcpu, ipsr) = psr.i64;
1361 // now set up the trampoline
1362 regs->cr_iip = *(unsigned long *)dorfirfi; // function pointer!!
1363 __asm__ __volatile("mov %0=psr;;":"=r"(regspsr)::"memory");
1364 regs->cr_ipsr =
1365 regspsr & ~(IA64_PSR_I | IA64_PSR_IC | IA64_PSR_BN);
1366 } else {
1367 regs->cr_ipsr = psr.i64;
1368 regs->cr_iip = PSCB(vcpu, iip);
1370 PSCB(vcpu, interrupt_collection_enabled) = 1;
1371 vcpu_bsw1(vcpu);
1372 vcpu->vcpu_info->evtchn_upcall_mask = !int_enable;
1373 return IA64_NO_FAULT;
1376 IA64FAULT vcpu_cover(VCPU * vcpu)
1378 // TODO: Only allowed for current vcpu
1379 REGS *regs = vcpu_regs(vcpu);
1381 if (!PSCB(vcpu, interrupt_collection_enabled)) {
1382 if (!PSCB(vcpu, incomplete_regframe))
1383 PSCB(vcpu, ifs) = regs->cr_ifs;
1384 else
1385 PSCB(vcpu, incomplete_regframe) = 0;
1387 regs->cr_ifs = 0;
1388 return IA64_NO_FAULT;
1391 IA64FAULT vcpu_thash(VCPU * vcpu, u64 vadr, u64 * pval)
1393 u64 pta = PSCB(vcpu, pta);
1394 u64 pta_sz = (pta & IA64_PTA_SZ(0x3f)) >> IA64_PTA_SZ_BIT;
1395 u64 pta_base = pta & ~((1UL << IA64_PTA_BASE_BIT) - 1);
1396 u64 Mask = (1L << pta_sz) - 1;
1397 u64 Mask_60_15 = (Mask >> 15) & 0x3fffffffffff;
1398 u64 compMask_60_15 = ~Mask_60_15;
1399 u64 rr_ps = vcpu_get_rr_ps(vcpu, vadr);
1400 u64 VHPT_offset = (vadr >> rr_ps) << 3;
1401 u64 VHPT_addr1 = vadr & 0xe000000000000000L;
1402 u64 VHPT_addr2a =
1403 ((pta_base >> 15) & 0x3fffffffffff) & compMask_60_15;
1404 u64 VHPT_addr2b =
1405 ((VHPT_offset >> 15) & 0x3fffffffffff) & Mask_60_15;
1406 u64 VHPT_addr3 = VHPT_offset & 0x7fff;
1407 u64 VHPT_addr = VHPT_addr1 | ((VHPT_addr2a | VHPT_addr2b) << 15) |
1408 VHPT_addr3;
1410 //verbose("vcpu_thash: vadr=%p, VHPT_addr=%p\n",vadr,VHPT_addr);
1411 *pval = VHPT_addr;
1412 return IA64_NO_FAULT;
1415 IA64FAULT vcpu_ttag(VCPU * vcpu, u64 vadr, u64 * padr)
1417 printk("vcpu_ttag: ttag instruction unsupported\n");
1418 return IA64_ILLOP_FAULT;
1421 int warn_region0_address = 0; // FIXME later: tie to a boot parameter?
1423 /* Return TRUE iff [b1,e1] and [b2,e2] partially or fully overlaps. */
1424 static inline int range_overlap(u64 b1, u64 e1, u64 b2, u64 e2)
1426 return (b1 <= e2) && (e1 >= b2);
1429 /* Crash domain if [base, base + page_size] and Xen virtual space overlaps.
1430 Note: LSBs of base inside page_size are ignored. */
1431 static inline void
1432 check_xen_space_overlap(const char *func, u64 base, u64 page_size)
1434 /* Overlaps can occur only in region 7.
1435 (This is an optimization to bypass all the checks). */
1436 if (REGION_NUMBER(base) != 7)
1437 return;
1439 /* Mask LSBs of base. */
1440 base &= ~(page_size - 1);
1442 /* FIXME: ideally an MCA should be generated... */
1443 if (range_overlap(HYPERVISOR_VIRT_START, HYPERVISOR_VIRT_END,
1444 base, base + page_size)
1445 || range_overlap(current->domain->arch.shared_info_va,
1446 current->domain->arch.shared_info_va
1447 + XSI_SIZE + XMAPPEDREGS_SIZE,
1448 base, base + page_size))
1449 panic_domain(NULL, "%s on Xen virtual space (%lx)\n",
1450 func, base);
1453 // FIXME: also need to check && (!trp->key || vcpu_pkr_match(trp->key))
1454 static inline int vcpu_match_tr_entry_no_p(TR_ENTRY * trp, u64 ifa,
1455 u64 rid)
1457 return trp->rid == rid
1458 && ifa >= trp->vadr && ifa <= (trp->vadr + (1L << trp->ps) - 1);
1461 static inline int vcpu_match_tr_entry(TR_ENTRY * trp, u64 ifa, u64 rid)
1463 return trp->pte.p && vcpu_match_tr_entry_no_p(trp, ifa, rid);
1466 static inline int
1467 vcpu_match_tr_entry_range(TR_ENTRY * trp, u64 rid, u64 b, u64 e)
1469 return trp->rid == rid
1470 && trp->pte.p
1471 && range_overlap(b, e, trp->vadr, trp->vadr + (1L << trp->ps) - 1);
1475 static TR_ENTRY *vcpu_tr_lookup(VCPU * vcpu, unsigned long va, u64 rid,
1476 BOOLEAN is_data)
1478 unsigned char *regions;
1479 TR_ENTRY *trp;
1480 int tr_max;
1481 int i;
1483 if (is_data) {
1484 // data
1485 regions = &vcpu->arch.dtr_regions;
1486 trp = vcpu->arch.dtrs;
1487 tr_max = sizeof(vcpu->arch.dtrs) / sizeof(vcpu->arch.dtrs[0]);
1488 } else {
1489 // instruction
1490 regions = &vcpu->arch.itr_regions;
1491 trp = vcpu->arch.itrs;
1492 tr_max = sizeof(vcpu->arch.itrs) / sizeof(vcpu->arch.itrs[0]);
1495 if (!vcpu_quick_region_check(*regions, va)) {
1496 return NULL;
1498 for (i = 0; i < tr_max; i++, trp++) {
1499 if (vcpu_match_tr_entry(trp, va, rid)) {
1500 return trp;
1503 return NULL;
1506 // return value
1507 // 0: failure
1508 // 1: success
1509 int
1510 vcpu_get_domain_bundle(VCPU * vcpu, REGS * regs, u64 gip,
1511 IA64_BUNDLE * bundle)
1513 u64 gpip; // guest pseudo phyiscal ip
1514 unsigned long vaddr;
1515 struct page_info *page;
1517 again:
1518 #if 0
1519 // Currently xen doesn't track psr.it bits.
1520 // it assumes always psr.it = 1.
1521 if (!(VCPU(vcpu, vpsr) & IA64_PSR_IT)) {
1522 gpip = gip;
1523 } else
1524 #endif
1526 unsigned long region = REGION_NUMBER(gip);
1527 unsigned long rr = PSCB(vcpu, rrs)[region];
1528 unsigned long rid = rr & RR_RID_MASK;
1529 BOOLEAN swap_rr0;
1530 TR_ENTRY *trp;
1532 // vcpu->arch.{i, d}tlb are volatile,
1533 // copy its value to the variable, tr, before use.
1534 TR_ENTRY tr;
1536 trp = vcpu_tr_lookup(vcpu, gip, rid, 0);
1537 if (trp != NULL) {
1538 tr = *trp;
1539 goto found;
1541 // When it failed to get a bundle, itlb miss is reflected.
1542 // Last itc.i value is cached to PSCBX(vcpu, itlb).
1543 tr = PSCBX(vcpu, itlb);
1544 if (vcpu_match_tr_entry(&tr, gip, rid)) {
1545 //dprintk(XENLOG_WARNING,
1546 // "%s gip 0x%lx gpip 0x%lx\n", __func__,
1547 // gip, gpip);
1548 goto found;
1550 trp = vcpu_tr_lookup(vcpu, gip, rid, 1);
1551 if (trp != NULL) {
1552 tr = *trp;
1553 goto found;
1555 #if 0
1556 tr = PSCBX(vcpu, dtlb);
1557 if (vcpu_match_tr_entry(&tr, gip, rid)) {
1558 goto found;
1560 #endif
1562 // try to access gip with guest virtual address
1563 // This may cause tlb miss. see vcpu_translate(). Be careful!
1564 swap_rr0 = (!region && PSCB(vcpu, metaphysical_mode));
1565 if (swap_rr0) {
1566 set_one_rr(0x0, PSCB(vcpu, rrs[0]));
1568 *bundle = __get_domain_bundle(gip);
1569 if (swap_rr0) {
1570 set_metaphysical_rr0();
1572 if (bundle->i64[0] == 0 && bundle->i64[1] == 0) {
1573 dprintk(XENLOG_INFO, "%s gip 0x%lx\n", __func__, gip);
1574 return 0;
1576 return 1;
1578 found:
1579 gpip = ((tr.pte.ppn >> (tr.ps - 12)) << tr.ps) |
1580 (gip & ((1 << tr.ps) - 1));
1583 vaddr = (unsigned long)domain_mpa_to_imva(vcpu->domain, gpip);
1584 page = virt_to_page(vaddr);
1585 if (get_page(page, vcpu->domain) == 0) {
1586 if (page_get_owner(page) != vcpu->domain) {
1587 // This page might be a page granted by another
1588 // domain.
1589 panic_domain(regs, "domain tries to execute foreign "
1590 "domain page which might be mapped by "
1591 "grant table.\n");
1593 goto again;
1595 *bundle = *((IA64_BUNDLE *) vaddr);
1596 put_page(page);
1597 return 1;
1600 IA64FAULT vcpu_translate(VCPU * vcpu, u64 address, BOOLEAN is_data,
1601 u64 * pteval, u64 * itir, u64 * iha)
1603 unsigned long region = address >> 61;
1604 unsigned long pta, rid, rr;
1605 union pte_flags pte;
1606 TR_ENTRY *trp;
1608 if (PSCB(vcpu, metaphysical_mode) && !(!is_data && region)) {
1609 // dom0 may generate an uncacheable physical address (msb=1)
1610 if (region && ((region != 4) || (vcpu->domain != dom0))) {
1611 // FIXME: This seems to happen even though it shouldn't. Need to track
1612 // this down, but since it has been apparently harmless, just flag it for now
1613 // panic_domain(vcpu_regs(vcpu),
1615 /*
1616 * Guest may execute itc.d and rfi with psr.dt=0
1617 * When VMM try to fetch opcode, tlb miss may happen,
1618 * At this time PSCB(vcpu,metaphysical_mode)=1,
1619 * region=5,VMM need to handle this tlb miss as if
1620 * PSCB(vcpu,metaphysical_mode)=0
1621 */
1622 printk("vcpu_translate: bad physical address: 0x%lx "
1623 "at %lx\n", address, vcpu_regs(vcpu)->cr_iip);
1625 } else {
1626 *pteval = (address & _PAGE_PPN_MASK) |
1627 __DIRTY_BITS | _PAGE_PL_2 | _PAGE_AR_RWX;
1628 *itir = PAGE_SHIFT << 2;
1629 perfc_incrc(phys_translate);
1630 return IA64_NO_FAULT;
1632 } else if (!region && warn_region0_address) {
1633 REGS *regs = vcpu_regs(vcpu);
1634 unsigned long viip = PSCB(vcpu, iip);
1635 unsigned long vipsr = PSCB(vcpu, ipsr);
1636 unsigned long iip = regs->cr_iip;
1637 unsigned long ipsr = regs->cr_ipsr;
1638 printk("vcpu_translate: bad address 0x%lx, viip=0x%lx, "
1639 "vipsr=0x%lx, iip=0x%lx, ipsr=0x%lx continuing\n",
1640 address, viip, vipsr, iip, ipsr);
1643 rr = PSCB(vcpu, rrs)[region];
1644 rid = rr & RR_RID_MASK;
1645 if (is_data) {
1646 trp = vcpu_tr_lookup(vcpu, address, rid, 1);
1647 if (trp != NULL) {
1648 *pteval = trp->pte.val;
1649 *itir = trp->itir;
1650 perfc_incrc(tr_translate);
1651 return IA64_NO_FAULT;
1654 // FIXME?: check itr's for data accesses too, else bad things happen?
1655 /* else */ {
1656 trp = vcpu_tr_lookup(vcpu, address, rid, 0);
1657 if (trp != NULL) {
1658 *pteval = trp->pte.val;
1659 *itir = trp->itir;
1660 perfc_incrc(tr_translate);
1661 return IA64_NO_FAULT;
1665 /* check 1-entry TLB */
1666 // FIXME?: check dtlb for inst accesses too, else bad things happen?
1667 trp = &vcpu->arch.dtlb;
1668 pte = trp->pte;
1669 if ( /* is_data && */ pte.p
1670 && vcpu_match_tr_entry_no_p(trp, address, rid)) {
1671 *pteval = pte.val;
1672 *itir = trp->itir;
1673 perfc_incrc(dtlb_translate);
1674 return IA64_USE_TLB;
1677 /* check guest VHPT */
1678 pta = PSCB(vcpu, pta);
1679 if (pta & IA64_PTA_VF) { /* long format VHPT - not implemented */
1680 panic_domain(vcpu_regs(vcpu), "can't do long format VHPT\n");
1681 //return is_data ? IA64_DATA_TLB_VECTOR:IA64_INST_TLB_VECTOR;
1684 *itir = rr & (RR_RID_MASK | RR_PS_MASK);
1685 // note: architecturally, iha is optionally set for alt faults but
1686 // xenlinux depends on it so should document it as part of PV interface
1687 vcpu_thash(vcpu, address, iha);
1688 if (!(rr & RR_VE_MASK) || !(pta & IA64_PTA_VE))
1689 return is_data ? IA64_ALT_DATA_TLB_VECTOR :
1690 IA64_ALT_INST_TLB_VECTOR;
1692 /* avoid recursively walking (short format) VHPT */
1693 if (((address ^ pta) & ((itir_mask(pta) << 3) >> 3)) == 0)
1694 return is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
1696 if (!__access_ok(*iha)
1697 || __copy_from_user(&pte, (void *)(*iha), sizeof(pte)) != 0)
1698 // virtual VHPT walker "missed" in TLB
1699 return IA64_VHPT_FAULT;
1701 /*
1702 * Optimisation: this VHPT walker aborts on not-present pages
1703 * instead of inserting a not-present translation, this allows
1704 * vectoring directly to the miss handler.
1705 */
1706 if (!pte.p)
1707 return is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
1709 /* found mapping in guest VHPT! */
1710 *itir = rr & RR_PS_MASK;
1711 *pteval = pte.val;
1712 perfc_incrc(vhpt_translate);
1713 return IA64_NO_FAULT;
1716 IA64FAULT vcpu_tpa(VCPU * vcpu, u64 vadr, u64 * padr)
1718 u64 pteval, itir, mask, iha;
1719 IA64FAULT fault;
1721 fault = vcpu_translate(vcpu, vadr, TRUE, &pteval, &itir, &iha);
1722 if (fault == IA64_NO_FAULT || fault == IA64_USE_TLB) {
1723 mask = itir_mask(itir);
1724 *padr = (pteval & _PAGE_PPN_MASK & mask) | (vadr & ~mask);
1725 return IA64_NO_FAULT;
1727 return vcpu_force_data_miss(vcpu, vadr);
1730 IA64FAULT vcpu_tak(VCPU * vcpu, u64 vadr, u64 * key)
1732 printk("vcpu_tak: tak instruction unsupported\n");
1733 return IA64_ILLOP_FAULT;
1734 // HACK ALERT: tak does a thash for now
1735 //return vcpu_thash(vcpu,vadr,key);
1738 /**************************************************************************
1739 VCPU debug breakpoint register access routines
1740 **************************************************************************/
1742 IA64FAULT vcpu_set_dbr(VCPU * vcpu, u64 reg, u64 val)
1744 // TODO: unimplemented DBRs return a reserved register fault
1745 // TODO: Should set Logical CPU state, not just physical
1746 ia64_set_dbr(reg, val);
1747 return IA64_NO_FAULT;
1750 IA64FAULT vcpu_set_ibr(VCPU * vcpu, u64 reg, u64 val)
1752 // TODO: unimplemented IBRs return a reserved register fault
1753 // TODO: Should set Logical CPU state, not just physical
1754 ia64_set_ibr(reg, val);
1755 return IA64_NO_FAULT;
1758 IA64FAULT vcpu_get_dbr(VCPU * vcpu, u64 reg, u64 * pval)
1760 // TODO: unimplemented DBRs return a reserved register fault
1761 u64 val = ia64_get_dbr(reg);
1762 *pval = val;
1763 return IA64_NO_FAULT;
1766 IA64FAULT vcpu_get_ibr(VCPU * vcpu, u64 reg, u64 * pval)
1768 // TODO: unimplemented IBRs return a reserved register fault
1769 u64 val = ia64_get_ibr(reg);
1770 *pval = val;
1771 return IA64_NO_FAULT;
1774 /**************************************************************************
1775 VCPU performance monitor register access routines
1776 **************************************************************************/
1778 IA64FAULT vcpu_set_pmc(VCPU * vcpu, u64 reg, u64 val)
1780 // TODO: Should set Logical CPU state, not just physical
1781 // NOTE: Writes to unimplemented PMC registers are discarded
1782 #ifdef DEBUG_PFMON
1783 printk("vcpu_set_pmc(%x,%lx)\n", reg, val);
1784 #endif
1785 ia64_set_pmc(reg, val);
1786 return IA64_NO_FAULT;
1789 IA64FAULT vcpu_set_pmd(VCPU * vcpu, u64 reg, u64 val)
1791 // TODO: Should set Logical CPU state, not just physical
1792 // NOTE: Writes to unimplemented PMD registers are discarded
1793 #ifdef DEBUG_PFMON
1794 printk("vcpu_set_pmd(%x,%lx)\n", reg, val);
1795 #endif
1796 ia64_set_pmd(reg, val);
1797 return IA64_NO_FAULT;
1800 IA64FAULT vcpu_get_pmc(VCPU * vcpu, u64 reg, u64 * pval)
1802 // NOTE: Reads from unimplemented PMC registers return zero
1803 u64 val = (u64) ia64_get_pmc(reg);
1804 #ifdef DEBUG_PFMON
1805 printk("%lx=vcpu_get_pmc(%x)\n", val, reg);
1806 #endif
1807 *pval = val;
1808 return IA64_NO_FAULT;
1811 IA64FAULT vcpu_get_pmd(VCPU * vcpu, u64 reg, u64 * pval)
1813 // NOTE: Reads from unimplemented PMD registers return zero
1814 u64 val = (u64) ia64_get_pmd(reg);
1815 #ifdef DEBUG_PFMON
1816 printk("%lx=vcpu_get_pmd(%x)\n", val, reg);
1817 #endif
1818 *pval = val;
1819 return IA64_NO_FAULT;
1822 /**************************************************************************
1823 VCPU banked general register access routines
1824 **************************************************************************/
1825 #define vcpu_bsw0_unat(i,b0unat,b1unat,runat,IA64_PT_REGS_R16_SLOT) \
1826 do{ \
1827 __asm__ __volatile__ ( \
1828 ";;extr.u %0 = %3,%6,16;;\n" \
1829 "dep %1 = %0, %1, 0, 16;;\n" \
1830 "st8 [%4] = %1\n" \
1831 "extr.u %0 = %2, 16, 16;;\n" \
1832 "dep %3 = %0, %3, %6, 16;;\n" \
1833 "st8 [%5] = %3\n" \
1834 ::"r"(i),"r"(*b1unat),"r"(*b0unat),"r"(*runat),"r"(b1unat), \
1835 "r"(runat),"i"(IA64_PT_REGS_R16_SLOT):"memory"); \
1836 }while(0)
1838 IA64FAULT vcpu_bsw0(VCPU * vcpu)
1840 // TODO: Only allowed for current vcpu
1841 REGS *regs = vcpu_regs(vcpu);
1842 unsigned long *r = &regs->r16;
1843 unsigned long *b0 = &PSCB(vcpu, bank0_regs[0]);
1844 unsigned long *b1 = &PSCB(vcpu, bank1_regs[0]);
1845 unsigned long *runat = &regs->eml_unat;
1846 unsigned long *b0unat = &PSCB(vcpu, vbnat);
1847 unsigned long *b1unat = &PSCB(vcpu, vnat);
1849 unsigned long i;
1851 if (VMX_DOMAIN(vcpu)) {
1852 if (VCPU(vcpu, vpsr) & IA64_PSR_BN) {
1853 for (i = 0; i < 16; i++) {
1854 *b1++ = *r;
1855 *r++ = *b0++;
1857 vcpu_bsw0_unat(i, b0unat, b1unat, runat,
1858 IA64_PT_REGS_R16_SLOT);
1859 VCPU(vcpu, vpsr) &= ~IA64_PSR_BN;
1861 } else {
1862 if (PSCB(vcpu, banknum)) {
1863 for (i = 0; i < 16; i++) {
1864 *b1++ = *r;
1865 *r++ = *b0++;
1867 vcpu_bsw0_unat(i, b0unat, b1unat, runat,
1868 IA64_PT_REGS_R16_SLOT);
1869 PSCB(vcpu, banknum) = 0;
1872 return IA64_NO_FAULT;
1875 #define vcpu_bsw1_unat(i, b0unat, b1unat, runat, IA64_PT_REGS_R16_SLOT) \
1876 do { \
1877 __asm__ __volatile__ (";;extr.u %0 = %3,%6,16;;\n" \
1878 "dep %1 = %0, %1, 16, 16;;\n" \
1879 "st8 [%4] = %1\n" \
1880 "extr.u %0 = %2, 0, 16;;\n" \
1881 "dep %3 = %0, %3, %6, 16;;\n" \
1882 "st8 [%5] = %3\n" \
1883 ::"r"(i), "r"(*b0unat), "r"(*b1unat), \
1884 "r"(*runat), "r"(b0unat), "r"(runat), \
1885 "i"(IA64_PT_REGS_R16_SLOT): "memory"); \
1886 } while(0)
1888 IA64FAULT vcpu_bsw1(VCPU * vcpu)
1890 // TODO: Only allowed for current vcpu
1891 REGS *regs = vcpu_regs(vcpu);
1892 unsigned long *r = &regs->r16;
1893 unsigned long *b0 = &PSCB(vcpu, bank0_regs[0]);
1894 unsigned long *b1 = &PSCB(vcpu, bank1_regs[0]);
1895 unsigned long *runat = &regs->eml_unat;
1896 unsigned long *b0unat = &PSCB(vcpu, vbnat);
1897 unsigned long *b1unat = &PSCB(vcpu, vnat);
1899 unsigned long i;
1901 if (VMX_DOMAIN(vcpu)) {
1902 if (!(VCPU(vcpu, vpsr) & IA64_PSR_BN)) {
1903 for (i = 0; i < 16; i++) {
1904 *b0++ = *r;
1905 *r++ = *b1++;
1907 vcpu_bsw1_unat(i, b0unat, b1unat, runat,
1908 IA64_PT_REGS_R16_SLOT);
1909 VCPU(vcpu, vpsr) |= IA64_PSR_BN;
1911 } else {
1912 if (!PSCB(vcpu, banknum)) {
1913 for (i = 0; i < 16; i++) {
1914 *b0++ = *r;
1915 *r++ = *b1++;
1917 vcpu_bsw1_unat(i, b0unat, b1unat, runat,
1918 IA64_PT_REGS_R16_SLOT);
1919 PSCB(vcpu, banknum) = 1;
1922 return IA64_NO_FAULT;
1925 /**************************************************************************
1926 VCPU cpuid access routines
1927 **************************************************************************/
1929 IA64FAULT vcpu_get_cpuid(VCPU * vcpu, u64 reg, u64 * pval)
1931 // FIXME: This could get called as a result of a rsvd-reg fault
1932 // if reg > 3
1933 switch (reg) {
1934 case 0:
1935 memcpy(pval, "Xen/ia64", 8);
1936 break;
1937 case 1:
1938 *pval = 0;
1939 break;
1940 case 2:
1941 *pval = 0;
1942 break;
1943 case 3:
1944 *pval = ia64_get_cpuid(3);
1945 break;
1946 case 4:
1947 *pval = ia64_get_cpuid(4);
1948 break;
1949 default:
1950 if (reg > (ia64_get_cpuid(3) & 0xff))
1951 return IA64_RSVDREG_FAULT;
1952 *pval = ia64_get_cpuid(reg);
1953 break;
1955 return IA64_NO_FAULT;
1958 /**************************************************************************
1959 VCPU region register access routines
1960 **************************************************************************/
1962 unsigned long vcpu_get_rr_ve(VCPU * vcpu, u64 vadr)
1964 ia64_rr rr;
1966 rr.rrval = PSCB(vcpu, rrs)[vadr >> 61];
1967 return rr.ve;
1970 IA64FAULT vcpu_set_rr(VCPU * vcpu, u64 reg, u64 val)
1972 PSCB(vcpu, rrs)[reg >> 61] = val;
1973 // warning: set_one_rr() does it "live"
1974 set_one_rr(reg, val);
1975 return IA64_NO_FAULT;
1978 IA64FAULT vcpu_get_rr(VCPU * vcpu, u64 reg, u64 * pval)
1980 if (VMX_DOMAIN(vcpu))
1981 *pval = VMX(vcpu, vrr[reg >> 61]);
1982 else
1983 *pval = PSCB(vcpu, rrs)[reg >> 61];
1985 return IA64_NO_FAULT;
1988 /**************************************************************************
1989 VCPU protection key register access routines
1990 **************************************************************************/
1992 IA64FAULT vcpu_get_pkr(VCPU * vcpu, u64 reg, u64 * pval)
1994 #ifndef PKR_USE_FIXED
1995 printk("vcpu_get_pkr: called, not implemented yet\n");
1996 return IA64_ILLOP_FAULT;
1997 #else
1998 u64 val = (u64) ia64_get_pkr(reg);
1999 *pval = val;
2000 return IA64_NO_FAULT;
2001 #endif
2004 IA64FAULT vcpu_set_pkr(VCPU * vcpu, u64 reg, u64 val)
2006 #ifndef PKR_USE_FIXED
2007 printk("vcpu_set_pkr: called, not implemented yet\n");
2008 return IA64_ILLOP_FAULT;
2009 #else
2010 // if (reg >= NPKRS)
2011 // return IA64_ILLOP_FAULT;
2012 vcpu->pkrs[reg] = val;
2013 ia64_set_pkr(reg, val);
2014 return IA64_NO_FAULT;
2015 #endif
2018 /**************************************************************************
2019 VCPU translation register access routines
2020 **************************************************************************/
2022 static void
2023 vcpu_set_tr_entry_rid(TR_ENTRY * trp, u64 pte,
2024 u64 itir, u64 ifa, u64 rid)
2026 u64 ps;
2027 union pte_flags new_pte;
2029 trp->itir = itir;
2030 trp->rid = rid;
2031 ps = trp->ps;
2032 new_pte.val = pte;
2033 if (new_pte.pl < 2)
2034 new_pte.pl = 2;
2035 trp->vadr = ifa & ~0xfff;
2036 if (ps > 12) { // "ignore" relevant low-order bits
2037 new_pte.ppn &= ~((1UL << (ps - 12)) - 1);
2038 trp->vadr &= ~((1UL << ps) - 1);
2041 /* Atomic write. */
2042 trp->pte.val = new_pte.val;
2045 static inline void
2046 vcpu_set_tr_entry(TR_ENTRY * trp, u64 pte, u64 itir, u64 ifa)
2048 vcpu_set_tr_entry_rid(trp, pte, itir, ifa,
2049 VCPU(current, rrs[ifa >> 61]) & RR_RID_MASK);
2052 IA64FAULT vcpu_itr_d(VCPU * vcpu, u64 slot, u64 pte,
2053 u64 itir, u64 ifa)
2055 TR_ENTRY *trp;
2057 if (slot >= NDTRS)
2058 return IA64_RSVDREG_FAULT;
2060 vcpu_purge_tr_entry(&PSCBX(vcpu, dtlb));
2062 trp = &PSCBX(vcpu, dtrs[slot]);
2063 //printk("***** itr.d: setting slot %d: ifa=%p\n",slot,ifa);
2064 vcpu_set_tr_entry(trp, pte, itir, ifa);
2065 vcpu_quick_region_set(PSCBX(vcpu, dtr_regions), ifa);
2067 /*
2068 * FIXME According to spec, vhpt should be purged, but this
2069 * incurs considerable performance loss, since it is safe for
2070 * linux not to purge vhpt, vhpt purge is disabled until a
2071 * feasible way is found.
2073 * vcpu_flush_tlb_vhpt_range(ifa & itir_mask(itir), itir_ps(itir));
2074 */
2076 return IA64_NO_FAULT;
2079 IA64FAULT vcpu_itr_i(VCPU * vcpu, u64 slot, u64 pte,
2080 u64 itir, u64 ifa)
2082 TR_ENTRY *trp;
2084 if (slot >= NITRS)
2085 return IA64_RSVDREG_FAULT;
2087 vcpu_purge_tr_entry(&PSCBX(vcpu, itlb));
2089 trp = &PSCBX(vcpu, itrs[slot]);
2090 //printk("***** itr.i: setting slot %d: ifa=%p\n",slot,ifa);
2091 vcpu_set_tr_entry(trp, pte, itir, ifa);
2092 vcpu_quick_region_set(PSCBX(vcpu, itr_regions), ifa);
2094 /*
2095 * FIXME According to spec, vhpt should be purged, but this
2096 * incurs considerable performance loss, since it is safe for
2097 * linux not to purge vhpt, vhpt purge is disabled until a
2098 * feasible way is found.
2100 * vcpu_flush_tlb_vhpt_range(ifa & itir_mask(itir), itir_ps(itir));
2101 */
2103 return IA64_NO_FAULT;
2106 IA64FAULT vcpu_set_itr(VCPU * vcpu, u64 slot, u64 pte,
2107 u64 itir, u64 ifa, u64 rid)
2109 TR_ENTRY *trp;
2111 if (slot >= NITRS)
2112 return IA64_RSVDREG_FAULT;
2113 trp = &PSCBX(vcpu, itrs[slot]);
2114 vcpu_set_tr_entry_rid(trp, pte, itir, ifa, rid);
2116 /* Recompute the itr_region. */
2117 vcpu->arch.itr_regions = 0;
2118 for (trp = vcpu->arch.itrs; trp < &vcpu->arch.itrs[NITRS]; trp++)
2119 if (trp->pte.p)
2120 vcpu_quick_region_set(vcpu->arch.itr_regions,
2121 trp->vadr);
2122 return IA64_NO_FAULT;
2125 IA64FAULT vcpu_set_dtr(VCPU * vcpu, u64 slot, u64 pte,
2126 u64 itir, u64 ifa, u64 rid)
2128 TR_ENTRY *trp;
2130 if (slot >= NDTRS)
2131 return IA64_RSVDREG_FAULT;
2132 trp = &PSCBX(vcpu, dtrs[slot]);
2133 vcpu_set_tr_entry_rid(trp, pte, itir, ifa, rid);
2135 /* Recompute the dtr_region. */
2136 vcpu->arch.dtr_regions = 0;
2137 for (trp = vcpu->arch.dtrs; trp < &vcpu->arch.dtrs[NDTRS]; trp++)
2138 if (trp->pte.p)
2139 vcpu_quick_region_set(vcpu->arch.dtr_regions,
2140 trp->vadr);
2141 return IA64_NO_FAULT;
2144 /**************************************************************************
2145 VCPU translation cache access routines
2146 **************************************************************************/
2148 void
2149 vcpu_itc_no_srlz(VCPU * vcpu, u64 IorD, u64 vaddr, u64 pte,
2150 u64 mp_pte, u64 logps, struct p2m_entry *entry)
2152 unsigned long psr;
2153 unsigned long ps = (vcpu->domain == dom0) ? logps : PAGE_SHIFT;
2155 check_xen_space_overlap("itc", vaddr, 1UL << logps);
2157 // FIXME, must be inlined or potential for nested fault here!
2158 if ((vcpu->domain == dom0) && (logps < PAGE_SHIFT))
2159 panic_domain(NULL, "vcpu_itc_no_srlz: domain trying to use "
2160 "smaller page size!\n");
2162 BUG_ON(logps > PAGE_SHIFT);
2163 vcpu_tlb_track_insert_or_dirty(vcpu, vaddr, entry);
2164 psr = ia64_clear_ic();
2165 pte &= ~(_PAGE_RV2 | _PAGE_RV1); // Mask out the reserved bits.
2166 ia64_itc(IorD, vaddr, pte, ps); // FIXME: look for bigger mappings
2167 ia64_set_psr(psr);
2168 // ia64_srlz_i(); // no srls req'd, will rfi later
2169 #ifdef VHPT_GLOBAL
2170 if (vcpu->domain == dom0 && ((vaddr >> 61) == 7)) {
2171 // FIXME: this is dangerous... vhpt_flush_address ensures these
2172 // addresses never get flushed. More work needed if this
2173 // ever happens.
2174 //printk("vhpt_insert(%p,%p,%p)\n",vaddr,pte,1L<<logps);
2175 if (logps > PAGE_SHIFT)
2176 vhpt_multiple_insert(vaddr, pte, logps);
2177 else
2178 vhpt_insert(vaddr, pte, logps << 2);
2180 // even if domain pagesize is larger than PAGE_SIZE, just put
2181 // PAGE_SIZE mapping in the vhpt for now, else purging is complicated
2182 else
2183 vhpt_insert(vaddr, pte, PAGE_SHIFT << 2);
2184 #endif
2185 if (IorD & 0x4) /* don't place in 1-entry TLB */
2186 return;
2187 if (IorD & 0x1) {
2188 vcpu_set_tr_entry(&PSCBX(vcpu, itlb), mp_pte, ps << 2, vaddr);
2190 if (IorD & 0x2) {
2191 vcpu_set_tr_entry(&PSCBX(vcpu, dtlb), mp_pte, ps << 2, vaddr);
2195 IA64FAULT vcpu_itc_d(VCPU * vcpu, u64 pte, u64 itir, u64 ifa)
2197 unsigned long pteval, logps = itir_ps(itir);
2198 BOOLEAN swap_rr0 = (!(ifa >> 61) && PSCB(vcpu, metaphysical_mode));
2199 struct p2m_entry entry;
2201 if (logps < PAGE_SHIFT)
2202 panic_domain(NULL, "vcpu_itc_d: domain trying to use "
2203 "smaller page size!\n");
2205 again:
2206 //itir = (itir & ~0xfc) | (PAGE_SHIFT<<2); // ignore domain's pagesize
2207 pteval = translate_domain_pte(pte, ifa, itir, &logps, &entry);
2208 if (!pteval)
2209 return IA64_ILLOP_FAULT;
2210 if (swap_rr0)
2211 set_one_rr(0x0, PSCB(vcpu, rrs[0]));
2212 vcpu_itc_no_srlz(vcpu, 2, ifa, pteval, pte, logps, &entry);
2213 if (swap_rr0)
2214 set_metaphysical_rr0();
2215 if (p2m_entry_retry(&entry)) {
2216 vcpu_flush_tlb_vhpt_range(ifa, logps);
2217 goto again;
2219 return IA64_NO_FAULT;
2222 IA64FAULT vcpu_itc_i(VCPU * vcpu, u64 pte, u64 itir, u64 ifa)
2224 unsigned long pteval, logps = itir_ps(itir);
2225 BOOLEAN swap_rr0 = (!(ifa >> 61) && PSCB(vcpu, metaphysical_mode));
2226 struct p2m_entry entry;
2228 if (logps < PAGE_SHIFT)
2229 panic_domain(NULL, "vcpu_itc_i: domain trying to use "
2230 "smaller page size!\n");
2231 again:
2232 //itir = (itir & ~0xfc) | (PAGE_SHIFT<<2); // ignore domain's pagesize
2233 pteval = translate_domain_pte(pte, ifa, itir, &logps, &entry);
2234 if (!pteval)
2235 return IA64_ILLOP_FAULT;
2236 if (swap_rr0)
2237 set_one_rr(0x0, PSCB(vcpu, rrs[0]));
2238 vcpu_itc_no_srlz(vcpu, 1, ifa, pteval, pte, logps, &entry);
2239 if (swap_rr0)
2240 set_metaphysical_rr0();
2241 if (p2m_entry_retry(&entry)) {
2242 vcpu_flush_tlb_vhpt_range(ifa, logps);
2243 goto again;
2245 return IA64_NO_FAULT;
2248 IA64FAULT vcpu_ptc_l(VCPU * vcpu, u64 vadr, u64 log_range)
2250 BUG_ON(vcpu != current);
2252 check_xen_space_overlap("ptc_l", vadr, 1UL << log_range);
2254 /* Purge TC */
2255 vcpu_purge_tr_entry(&PSCBX(vcpu, dtlb));
2256 vcpu_purge_tr_entry(&PSCBX(vcpu, itlb));
2258 /* Purge all tlb and vhpt */
2259 vcpu_flush_tlb_vhpt_range(vadr, log_range);
2261 return IA64_NO_FAULT;
2264 // At privlvl=0, fc performs no access rights or protection key checks, while
2265 // at privlvl!=0, fc performs access rights checks as if it were a 1-byte
2266 // read but no protection key check. Thus in order to avoid an unexpected
2267 // access rights fault, we have to translate the virtual address to a
2268 // physical address (possibly via a metaphysical address) and do the fc
2269 // on the physical address, which is guaranteed to flush the same cache line
2270 IA64FAULT vcpu_fc(VCPU * vcpu, u64 vadr)
2272 // TODO: Only allowed for current vcpu
2273 u64 mpaddr, paddr;
2274 IA64FAULT fault;
2276 again:
2277 fault = vcpu_tpa(vcpu, vadr, &mpaddr);
2278 if (fault == IA64_NO_FAULT) {
2279 struct p2m_entry entry;
2280 paddr = translate_domain_mpaddr(mpaddr, &entry);
2281 ia64_fc(__va(paddr));
2282 if (p2m_entry_retry(&entry))
2283 goto again;
2285 return fault;
2288 IA64FAULT vcpu_ptc_e(VCPU * vcpu, u64 vadr)
2290 // Note that this only needs to be called once, i.e. the
2291 // architected loop to purge the entire TLB, should use
2292 // base = stride1 = stride2 = 0, count0 = count 1 = 1
2294 vcpu_flush_vtlb_all(current);
2296 return IA64_NO_FAULT;
2299 IA64FAULT vcpu_ptc_g(VCPU * vcpu, u64 vadr, u64 addr_range)
2301 printk("vcpu_ptc_g: called, not implemented yet\n");
2302 return IA64_ILLOP_FAULT;
2305 IA64FAULT vcpu_ptc_ga(VCPU * vcpu, u64 vadr, u64 addr_range)
2307 // FIXME: validate not flushing Xen addresses
2308 // if (Xen address) return(IA64_ILLOP_FAULT);
2309 // FIXME: ??breaks if domain PAGE_SIZE < Xen PAGE_SIZE
2310 //printk("######## vcpu_ptc_ga(%p,%p) ##############\n",vadr,addr_range);
2312 check_xen_space_overlap("ptc_ga", vadr, addr_range);
2314 domain_flush_vtlb_range(vcpu->domain, vadr, addr_range);
2316 return IA64_NO_FAULT;
2319 IA64FAULT vcpu_ptr_d(VCPU * vcpu, u64 vadr, u64 log_range)
2321 unsigned long region = vadr >> 61;
2322 u64 addr_range = 1UL << log_range;
2323 unsigned long rid, rr;
2324 int i;
2325 TR_ENTRY *trp;
2327 BUG_ON(vcpu != current);
2328 check_xen_space_overlap("ptr_d", vadr, 1UL << log_range);
2330 rr = PSCB(vcpu, rrs)[region];
2331 rid = rr & RR_RID_MASK;
2333 /* Purge TC */
2334 vcpu_purge_tr_entry(&PSCBX(vcpu, dtlb));
2336 /* Purge tr and recompute dtr_regions. */
2337 vcpu->arch.dtr_regions = 0;
2338 for (trp = vcpu->arch.dtrs, i = NDTRS; i; i--, trp++)
2339 if (vcpu_match_tr_entry_range
2340 (trp, rid, vadr, vadr + addr_range))
2341 vcpu_purge_tr_entry(trp);
2342 else if (trp->pte.p)
2343 vcpu_quick_region_set(vcpu->arch.dtr_regions,
2344 trp->vadr);
2346 vcpu_flush_tlb_vhpt_range(vadr, log_range);
2348 return IA64_NO_FAULT;
2351 IA64FAULT vcpu_ptr_i(VCPU * vcpu, u64 vadr, u64 log_range)
2353 unsigned long region = vadr >> 61;
2354 u64 addr_range = 1UL << log_range;
2355 unsigned long rid, rr;
2356 int i;
2357 TR_ENTRY *trp;
2359 BUG_ON(vcpu != current);
2360 check_xen_space_overlap("ptr_i", vadr, 1UL << log_range);
2362 rr = PSCB(vcpu, rrs)[region];
2363 rid = rr & RR_RID_MASK;
2365 /* Purge TC */
2366 vcpu_purge_tr_entry(&PSCBX(vcpu, itlb));
2368 /* Purge tr and recompute itr_regions. */
2369 vcpu->arch.itr_regions = 0;
2370 for (trp = vcpu->arch.itrs, i = NITRS; i; i--, trp++)
2371 if (vcpu_match_tr_entry_range
2372 (trp, rid, vadr, vadr + addr_range))
2373 vcpu_purge_tr_entry(trp);
2374 else if (trp->pte.p)
2375 vcpu_quick_region_set(vcpu->arch.itr_regions,
2376 trp->vadr);
2378 vcpu_flush_tlb_vhpt_range(vadr, log_range);
2380 return IA64_NO_FAULT;