ia64/xen-unstable

view xen/include/asm-ia64/linux-xen/asm/pgtable.h @ 10786:86e5d8458c08

[IA64] live migration

Shadow mode and live migration.

Virtualize Dirty bit.

Signed-off-by: Tristan Gingold <tristan.gingold@bull.net>
author awilliam@xenbuild.aw
date Wed Jul 26 09:36:36 2006 -0600 (2006-07-26)
parents f02d59f9b11f
children 27ccf13dc3b7
line source
1 #ifndef _ASM_IA64_PGTABLE_H
2 #define _ASM_IA64_PGTABLE_H
4 /*
5 * This file contains the functions and defines necessary to modify and use
6 * the IA-64 page table tree.
7 *
8 * This hopefully works with any (fixed) IA-64 page-size, as defined
9 * in <asm/page.h>.
10 *
11 * Copyright (C) 1998-2005 Hewlett-Packard Co
12 * David Mosberger-Tang <davidm@hpl.hp.com>
13 */
15 #include <linux/config.h>
17 #include <asm/mman.h>
18 #include <asm/page.h>
19 #include <asm/processor.h>
20 #include <asm/system.h>
21 #include <asm/types.h>
22 #ifdef XEN
23 #ifndef __ASSEMBLY__
24 #include <xen/sched.h> /* needed for mm_struct (via asm/domain.h) */
25 #endif
26 #endif
28 #define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */
30 /*
31 * First, define the various bits in a PTE. Note that the PTE format
32 * matches the VHPT short format, the firt doubleword of the VHPD long
33 * format, and the first doubleword of the TLB insertion format.
34 */
35 #define _PAGE_P_BIT 0
36 #define _PAGE_A_BIT 5
37 #define _PAGE_D_BIT 6
39 #define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */
40 #define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */
41 #define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */
42 #define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */
43 #define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */
44 #define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */
45 #define _PAGE_MA_MASK (0x7 << 2)
46 #define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */
47 #define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */
48 #define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */
49 #define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */
50 #define _PAGE_PL_MASK (3 << 7)
51 #define _PAGE_AR_R (0 << 9) /* read only */
52 #define _PAGE_AR_RX (1 << 9) /* read & execute */
53 #define _PAGE_AR_RW (2 << 9) /* read & write */
54 #define _PAGE_AR_RWX (3 << 9) /* read, write & execute */
55 #define _PAGE_AR_R_RW (4 << 9) /* read / read & write */
56 #define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */
57 #define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */
58 #define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */
59 #define _PAGE_AR_MASK (7 << 9)
60 #define _PAGE_AR_SHIFT 9
61 #define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */
62 #define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */
63 #define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
64 #define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */
65 #ifdef XEN
66 #define _PAGE_VIRT_D (__IA64_UL(1) << 53) /* Virtual dirty bit */
67 #define _PAGE_PROTNONE 0
68 #else
69 #define _PAGE_PROTNONE (__IA64_UL(1) << 63)
70 #endif
72 /* Valid only for a PTE with the present bit cleared: */
73 #define _PAGE_FILE (1 << 1) /* see swap & file pte remarks below */
75 #define _PFN_MASK _PAGE_PPN_MASK
76 /* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */
77 #define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED)
79 #define _PAGE_SIZE_4K 12
80 #define _PAGE_SIZE_8K 13
81 #define _PAGE_SIZE_16K 14
82 #define _PAGE_SIZE_64K 16
83 #define _PAGE_SIZE_256K 18
84 #define _PAGE_SIZE_1M 20
85 #define _PAGE_SIZE_4M 22
86 #define _PAGE_SIZE_16M 24
87 #define _PAGE_SIZE_64M 26
88 #define _PAGE_SIZE_256M 28
89 #define _PAGE_SIZE_1G 30
90 #define _PAGE_SIZE_4G 32
92 #define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
93 #define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
94 #define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED
96 /*
97 * Definitions for first level:
98 *
99 * PGDIR_SHIFT determines what a first-level page table entry can map.
100 */
101 #define PGDIR_SHIFT (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
102 #define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)
103 #define PGDIR_MASK (~(PGDIR_SIZE-1))
104 #define PTRS_PER_PGD (1UL << (PAGE_SHIFT-3))
105 #define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */
106 #define FIRST_USER_ADDRESS 0
108 /*
109 * Definitions for second level:
110 *
111 * PMD_SHIFT determines the size of the area a second-level page table
112 * can map.
113 */
114 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
115 #define PMD_SIZE (1UL << PMD_SHIFT)
116 #define PMD_MASK (~(PMD_SIZE-1))
117 #define PTRS_PER_PMD (1UL << (PAGE_SHIFT-3))
119 /*
120 * Definitions for third level:
121 */
122 #define PTRS_PER_PTE (__IA64_UL(1) << (PAGE_SHIFT-3))
124 /*
125 * All the normal masks have the "page accessed" bits on, as any time
126 * they are used, the page is accessed. They are cleared only by the
127 * page-out routines.
128 */
129 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A)
130 #define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
131 #define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
132 #define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
133 #define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
134 #define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
135 #define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX)
136 #define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
138 # ifndef __ASSEMBLY__
140 #include <asm/bitops.h>
141 #include <asm/cacheflush.h>
142 #include <asm/mmu_context.h>
143 #include <asm/processor.h>
145 /*
146 * Next come the mappings that determine how mmap() protection bits
147 * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The
148 * _P version gets used for a private shared memory segment, the _S
149 * version gets used for a shared memory segment with MAP_SHARED on.
150 * In a private shared memory segment, we do a copy-on-write if a task
151 * attempts to write to the page.
152 */
153 /* xwr */
154 #define __P000 PAGE_NONE
155 #define __P001 PAGE_READONLY
156 #define __P010 PAGE_READONLY /* write to priv pg -> copy & make writable */
157 #define __P011 PAGE_READONLY /* ditto */
158 #define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
159 #define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
160 #define __P110 PAGE_COPY_EXEC
161 #define __P111 PAGE_COPY_EXEC
163 #define __S000 PAGE_NONE
164 #define __S001 PAGE_READONLY
165 #define __S010 PAGE_SHARED /* we don't have (and don't need) write-only */
166 #define __S011 PAGE_SHARED
167 #define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
168 #define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
169 #define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
170 #define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
172 #define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
173 #define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
174 #define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
177 /*
178 * Some definitions to translate between mem_map, PTEs, and page addresses:
179 */
182 /* Quick test to see if ADDR is a (potentially) valid physical address. */
183 static inline long
184 ia64_phys_addr_valid (unsigned long addr)
185 {
186 return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
187 }
189 /*
190 * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
191 * memory. For the return value to be meaningful, ADDR must be >=
192 * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
193 * require a hash-, or multi-level tree-lookup or something of that
194 * sort) but it guarantees to return TRUE only if accessing the page
195 * at that address does not cause an error. Note that there may be
196 * addresses for which kern_addr_valid() returns FALSE even though an
197 * access would not cause an error (e.g., this is typically true for
198 * memory mapped I/O regions.
199 *
200 * XXX Need to implement this for IA-64.
201 */
202 #define kern_addr_valid(addr) (1)
205 /*
206 * Now come the defines and routines to manage and access the three-level
207 * page table.
208 */
210 /*
211 * On some architectures, special things need to be done when setting
212 * the PTE in a page table. Nothing special needs to be on IA-64.
213 */
214 #define set_pte(ptep, pteval) (*(ptep) = (pteval))
215 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
216 #ifdef XEN
217 static inline void
218 set_pte_rel(volatile pte_t* ptep, pte_t pteval)
219 {
220 #if CONFIG_SMP
221 asm volatile ("st8.rel [%0]=%1" ::
222 "r"(&pte_val(*ptep)), "r"(pte_val(pteval)) :
223 "memory");
224 #else
225 set_pte(ptep, pteval);
226 #endif
227 }
228 #endif
230 #define RGN_SIZE (1UL << 61)
231 #define RGN_KERNEL 7
233 #define VMALLOC_START 0xa000000200000000UL
234 #ifdef CONFIG_VIRTUAL_MEM_MAP
235 # define VMALLOC_END_INIT (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9)))
236 # define VMALLOC_END vmalloc_end
237 extern unsigned long vmalloc_end;
238 #else
239 # define VMALLOC_END (0xa000000000000000UL + (1UL << (4*PAGE_SHIFT - 9)))
240 #endif
242 /* fs/proc/kcore.c */
243 #define kc_vaddr_to_offset(v) ((v) - 0xa000000000000000UL)
244 #define kc_offset_to_vaddr(o) ((o) + 0xa000000000000000UL)
246 /*
247 * Conversion functions: convert page frame number (pfn) and a protection value to a page
248 * table entry (pte).
249 */
250 #define pfn_pte(pfn, pgprot) \
251 ({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; })
253 /* Extract pfn from pte. */
254 #define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
256 #define mk_pte(page, pgprot) pfn_pte(page_to_mfn(page), (pgprot))
258 /* This takes a physical page address that is used by the remapping functions */
259 #define mk_pte_phys(physpage, pgprot) \
260 ({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
262 #define pte_modify(_pte, newprot) \
263 (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
265 #define page_pte_prot(page,prot) mk_pte(page, prot)
266 #define page_pte(page) page_pte_prot(page, __pgprot(0))
268 #define pte_none(pte) (!pte_val(pte))
269 #define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
270 #define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL)
271 /* pte_page() returns the "struct page *" corresponding to the PTE: */
272 #define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
274 #define pmd_none(pmd) (!pmd_val(pmd))
275 #define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd)))
276 #define pmd_present(pmd) (pmd_val(pmd) != 0UL)
277 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
278 #define pmd_page_kernel(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
279 #define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
281 #define pud_none(pud) (!pud_val(pud))
282 #define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud)))
283 #define pud_present(pud) (pud_val(pud) != 0UL)
284 #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
286 #define pud_page(pud) ((unsigned long) __va(pud_val(pud) & _PFN_MASK))
288 /*
289 * The following have defined behavior only work if pte_present() is true.
290 */
291 #define pte_user(pte) ((pte_val(pte) & _PAGE_PL_MASK) == _PAGE_PL_3)
292 #define pte_read(pte) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) < 6)
293 #define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
294 #define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0)
295 #define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0)
296 #define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0)
297 #define pte_file(pte) ((pte_val(pte) & _PAGE_FILE) != 0)
298 #ifdef XEN
299 #define pte_mem(pte) \
300 (!(pte_val(pte) & (GPFN_IO_MASK | GPFN_INV_MASK)) && !pte_none(pte))
301 #endif
302 /*
303 * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
304 * access rights:
305 */
306 #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW))
307 #define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW))
308 #define pte_mkexec(pte) (__pte(pte_val(pte) | _PAGE_AR_RX))
309 #define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A))
310 #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A))
311 #define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D))
312 #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
313 #define pte_mkhuge(pte) (__pte(pte_val(pte) | _PAGE_P))
315 /*
316 * Macro to a page protection value as "uncacheable". Note that "protection" is really a
317 * misnomer here as the protection value contains the memory attribute bits, dirty bits,
318 * and various other bits as well.
319 */
320 #define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
322 /*
323 * Macro to make mark a page protection value as "write-combining".
324 * Note that "protection" is really a misnomer here as the protection
325 * value contains the memory attribute bits, dirty bits, and various
326 * other bits as well. Accesses through a write-combining translation
327 * works bypasses the caches, but does allow for consecutive writes to
328 * be combined into single (but larger) write transactions.
329 */
330 #define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
332 static inline unsigned long
333 pgd_index (unsigned long address)
334 {
335 unsigned long region = address >> 61;
336 unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
338 return (region << (PAGE_SHIFT - 6)) | l1index;
339 }
341 /* The offset in the 1-level directory is given by the 3 region bits
342 (61..63) and the level-1 bits. */
343 static inline pgd_t*
344 pgd_offset (struct mm_struct *mm, unsigned long address)
345 {
346 return mm->pgd + pgd_index(address);
347 }
349 /* In the kernel's mapped region we completely ignore the region number
350 (since we know it's in region number 5). */
351 #define pgd_offset_k(addr) \
352 (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
354 /* Look up a pgd entry in the gate area. On IA-64, the gate-area
355 resides in the kernel-mapped segment, hence we use pgd_offset_k()
356 here. */
357 #define pgd_offset_gate(mm, addr) pgd_offset_k(addr)
359 /* Find an entry in the second-level page table.. */
360 #define pmd_offset(dir,addr) \
361 ((pmd_t *) pud_page(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
363 /*
364 * Find an entry in the third-level page table. This looks more complicated than it
365 * should be because some platforms place page tables in high memory.
366 */
367 #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
368 #define pte_offset_kernel(dir,addr) ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(addr))
369 #define pte_offset_map(dir,addr) pte_offset_kernel(dir, addr)
370 #define pte_offset_map_nested(dir,addr) pte_offset_map(dir, addr)
371 #define pte_unmap(pte) do { } while (0)
372 #define pte_unmap_nested(pte) do { } while (0)
374 #ifndef XEN
375 /* atomic versions of the some PTE manipulations: */
377 static inline int
378 ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
379 {
380 #ifdef CONFIG_SMP
381 if (!pte_young(*ptep))
382 return 0;
383 return test_and_clear_bit(_PAGE_A_BIT, ptep);
384 #else
385 pte_t pte = *ptep;
386 if (!pte_young(pte))
387 return 0;
388 set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
389 return 1;
390 #endif
391 }
393 static inline int
394 ptep_test_and_clear_dirty (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
395 {
396 #ifdef CONFIG_SMP
397 if (!pte_dirty(*ptep))
398 return 0;
399 return test_and_clear_bit(_PAGE_D_BIT, ptep);
400 #else
401 pte_t pte = *ptep;
402 if (!pte_dirty(pte))
403 return 0;
404 set_pte_at(vma->vm_mm, addr, ptep, pte_mkclean(pte));
405 return 1;
406 #endif
407 }
408 #endif
410 #ifdef XEN
411 static inline pte_t
412 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
413 volatile pte_t *ptep)
414 #else
415 static inline pte_t
416 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
417 #endif
418 {
419 #ifdef CONFIG_SMP
420 return __pte(xchg((long *) ptep, 0));
421 #else
422 pte_t pte = *ptep;
423 pte_clear(mm, addr, ptep);
424 return pte;
425 #endif
426 }
428 #ifdef XEN
429 static inline pte_t
430 ptep_xchg(struct mm_struct *mm, unsigned long addr,
431 volatile pte_t *ptep, pte_t npte)
432 {
433 #ifdef CONFIG_SMP
434 return __pte(xchg((long *) ptep, pte_val(npte)));
435 #else
436 pte_t pte = *ptep;
437 set_pte (ptep, npte);
438 return pte;
439 #endif
440 }
442 static inline pte_t
443 ptep_cmpxchg_rel(struct mm_struct *mm, unsigned long addr,
444 volatile pte_t *ptep, pte_t old_pte, pte_t new_pte)
445 {
446 #ifdef CONFIG_SMP
447 return __pte(cmpxchg_rel(&pte_val(*ptep),
448 pte_val(old_pte), pte_val(new_pte)));
449 #else
450 pte_t pte = *ptep;
451 if (pte_val(pte) == pte_val(old_pte)) {
452 set_pte(ptep, npte);
453 }
454 return pte;
455 #endif
456 }
457 #endif
459 #ifndef XEN
460 static inline void
461 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
462 {
463 #ifdef CONFIG_SMP
464 unsigned long new, old;
466 do {
467 old = pte_val(*ptep);
468 new = pte_val(pte_wrprotect(__pte (old)));
469 } while (cmpxchg((unsigned long *) ptep, old, new) != old);
470 #else
471 pte_t old_pte = *ptep;
472 set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
473 #endif
474 }
476 static inline int
477 pte_same (pte_t a, pte_t b)
478 {
479 return pte_val(a) == pte_val(b);
480 }
482 #define update_mmu_cache(vma, address, pte) do { } while (0)
483 #endif /* XEN */
485 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
486 extern void paging_init (void);
488 /*
489 * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of
490 * bits in the swap-type field of the swap pte. It would be nice to
491 * enforce that, but we can't easily include <linux/swap.h> here.
492 * (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...).
493 *
494 * Format of swap pte:
495 * bit 0 : present bit (must be zero)
496 * bit 1 : _PAGE_FILE (must be zero)
497 * bits 2- 8: swap-type
498 * bits 9-62: swap offset
499 * bit 63 : _PAGE_PROTNONE bit
500 *
501 * Format of file pte:
502 * bit 0 : present bit (must be zero)
503 * bit 1 : _PAGE_FILE (must be one)
504 * bits 2-62: file_offset/PAGE_SIZE
505 * bit 63 : _PAGE_PROTNONE bit
506 */
507 #define __swp_type(entry) (((entry).val >> 2) & 0x7f)
508 #define __swp_offset(entry) (((entry).val << 1) >> 10)
509 #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((long) (offset) << 9) })
510 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
511 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
513 #define PTE_FILE_MAX_BITS 61
514 #define pte_to_pgoff(pte) ((pte_val(pte) << 1) >> 3)
515 #define pgoff_to_pte(off) ((pte_t) { ((off) << 2) | _PAGE_FILE })
517 /* XXX is this right? */
518 #define io_remap_page_range(vma, vaddr, paddr, size, prot) \
519 remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot)
521 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
522 remap_pfn_range(vma, vaddr, pfn, size, prot)
524 #define MK_IOSPACE_PFN(space, pfn) (pfn)
525 #define GET_IOSPACE(pfn) 0
526 #define GET_PFN(pfn) (pfn)
528 /*
529 * ZERO_PAGE is a global shared page that is always zero: used
530 * for zero-mapped memory areas etc..
531 */
532 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
533 #ifndef XEN
534 extern struct page *zero_page_memmap_ptr;
535 #define ZERO_PAGE(vaddr) (zero_page_memmap_ptr)
536 #endif
538 /* We provide our own get_unmapped_area to cope with VA holes for userland */
539 #define HAVE_ARCH_UNMAPPED_AREA
541 #ifdef CONFIG_HUGETLB_PAGE
542 #define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3))
543 #define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
544 #define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1))
545 struct mmu_gather;
546 void hugetlb_free_pgd_range(struct mmu_gather **tlb, unsigned long addr,
547 unsigned long end, unsigned long floor, unsigned long ceiling);
548 #endif
550 /*
551 * IA-64 doesn't have any external MMU info: the page tables contain all the necessary
552 * information. However, we use this routine to take care of any (delayed) i-cache
553 * flushing that may be necessary.
554 */
555 extern void lazy_mmu_prot_update (pte_t pte);
557 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
558 /*
559 * Update PTEP with ENTRY, which is guaranteed to be a less
560 * restrictive PTE. That is, ENTRY may have the ACCESSED, DIRTY, and
561 * WRITABLE bits turned on, when the value at PTEP did not. The
562 * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE.
563 *
564 * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without
565 * having to worry about races. On SMP machines, there are only two
566 * cases where this is true:
567 *
568 * (1) *PTEP has the PRESENT bit turned OFF
569 * (2) ENTRY has the DIRTY bit turned ON
570 *
571 * On ia64, we could implement this routine with a cmpxchg()-loop
572 * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY.
573 * However, like on x86, we can get a more streamlined version by
574 * observing that it is OK to drop ACCESSED bit updates when
575 * SAFELY_WRITABLE is FALSE. Besides being rare, all that would do is
576 * result in an extra Access-bit fault, which would then turn on the
577 * ACCESSED bit in the low-level fault handler (iaccess_bit or
578 * daccess_bit in ivt.S).
579 */
580 #ifdef CONFIG_SMP
581 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
582 do { \
583 if (__safely_writable) { \
584 set_pte(__ptep, __entry); \
585 flush_tlb_page(__vma, __addr); \
586 } \
587 } while (0)
588 #else
589 # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
590 ptep_establish(__vma, __addr, __ptep, __entry)
591 #endif
593 # ifdef CONFIG_VIRTUAL_MEM_MAP
594 /* arch mem_map init routine is needed due to holes in a virtual mem_map */
595 # define __HAVE_ARCH_MEMMAP_INIT
596 extern void memmap_init (unsigned long size, int nid, unsigned long zone,
597 unsigned long start_pfn);
598 # endif /* CONFIG_VIRTUAL_MEM_MAP */
599 # endif /* !__ASSEMBLY__ */
601 /*
602 * Identity-mapped regions use a large page size. We'll call such large pages
603 * "granules". If you can think of a better name that's unambiguous, let me
604 * know...
605 */
606 #if defined(CONFIG_IA64_GRANULE_64MB)
607 # define IA64_GRANULE_SHIFT _PAGE_SIZE_64M
608 #elif defined(CONFIG_IA64_GRANULE_16MB)
609 # define IA64_GRANULE_SHIFT _PAGE_SIZE_16M
610 #endif
611 #define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT)
612 /*
613 * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL):
614 */
615 #define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M
616 #define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT)
618 /*
619 * No page table caches to initialise
620 */
621 #define pgtable_cache_init() do { } while (0)
623 /* These tell get_user_pages() that the first gate page is accessible from user-level. */
624 #define FIXADDR_USER_START GATE_ADDR
625 #ifdef HAVE_BUGGY_SEGREL
626 # define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE)
627 #else
628 # define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
629 #endif
631 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
632 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
633 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
634 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
635 #define __HAVE_ARCH_PTE_SAME
636 #define __HAVE_ARCH_PGD_OFFSET_GATE
637 #define __HAVE_ARCH_LAZY_MMU_PROT_UPDATE
639 #include <asm-generic/pgtable-nopud.h>
640 #include <asm-generic/pgtable.h>
642 #endif /* _ASM_IA64_PGTABLE_H */