ia64/xen-unstable

view xen/include/asm-x86/x86_64/regs.h @ 15812:86a154e1ef5d

[HVM] Shadow: don't shadow the p2m table.
For HVM vcpus with paging disabled, we used to shadow the p2m table,
and skip the p2m lookup to go from gfn to mfn. Instead, we now
provide a simple pagetable that gives a one-to-one mapping of 4GB, and
shadow that, making the translations from gfn to mfn via the p2m.
This removes the paging-disabled special-case code from the shadow
fault handler, and allows us to expand the p2m interface, since all HVM
translations now go through the same p2m lookups.
Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
author Tim Deegan <Tim.Deegan@xensource.com>
date Fri Aug 31 11:06:22 2007 +0100 (2007-08-31)
parents 405573aedd24
children
line source
1 #ifndef _X86_64_REGS_H
2 #define _X86_64_REGS_H
4 #include <xen/types.h>
5 #include <public/xen.h>
7 #define vm86_mode(r) (0) /* No VM86 support in long mode. */
8 #define ring_0(r) (((r)->cs & 3) == 0)
9 #define ring_1(r) (((r)->cs & 3) == 1)
10 #define ring_2(r) (((r)->cs & 3) == 2)
11 #define ring_3(r) (((r)->cs & 3) == 3)
13 #define guest_kernel_mode(v, r) \
14 (!is_pv_32bit_vcpu(v) ? \
15 (ring_3(r) && ((v)->arch.flags & TF_kernel_mode)) : \
16 (ring_1(r)))
18 #define permit_softint(dpl, v, r) \
19 ((dpl) >= (guest_kernel_mode(v, r) ? 1 : 3))
21 /* Check for null trap callback handler: Is the EIP null? */
22 #define null_trap_bounce(v, tb) \
23 (!is_pv_32bit_vcpu(v) ? ((tb)->eip == 0) : (((tb)->cs & ~3) == 0))
25 /* Number of bytes of on-stack execution state to be context-switched. */
26 /* NB. Segment registers and bases are not saved/restored on x86/64 stack. */
27 #define CTXT_SWITCH_STACK_BYTES (offsetof(struct cpu_user_regs, es))
29 #endif