ia64/xen-unstable

view xen/include/asm-x86/mpspec_def.h @ 15812:86a154e1ef5d

[HVM] Shadow: don't shadow the p2m table.
For HVM vcpus with paging disabled, we used to shadow the p2m table,
and skip the p2m lookup to go from gfn to mfn. Instead, we now
provide a simple pagetable that gives a one-to-one mapping of 4GB, and
shadow that, making the translations from gfn to mfn via the p2m.
This removes the paging-disabled special-case code from the shadow
fault handler, and allows us to expand the p2m interface, since all HVM
translations now go through the same p2m lookups.
Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
author Tim Deegan <Tim.Deegan@xensource.com>
date Fri Aug 31 11:06:22 2007 +0100 (2007-08-31)
parents fd3f1e38fdcf
children
line source
1 #ifndef __ASM_MPSPEC_DEF_H
2 #define __ASM_MPSPEC_DEF_H
4 /*
5 * Structure definitions for SMP machines following the
6 * Intel Multiprocessing Specification 1.1 and 1.4.
7 */
9 /*
10 * This tag identifies where the SMP configuration
11 * information is.
12 */
14 #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_')
16 #define MAX_MPC_ENTRY 1024
17 #define MAX_APICS 256
19 struct intel_mp_floating
20 {
21 char mpf_signature[4]; /* "_MP_" */
22 unsigned int mpf_physptr; /* Configuration table address */
23 unsigned char mpf_length; /* Our length (paragraphs) */
24 unsigned char mpf_specification;/* Specification version */
25 unsigned char mpf_checksum; /* Checksum (makes sum 0) */
26 unsigned char mpf_feature1; /* Standard or configuration ? */
27 unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */
28 unsigned char mpf_feature3; /* Unused (0) */
29 unsigned char mpf_feature4; /* Unused (0) */
30 unsigned char mpf_feature5; /* Unused (0) */
31 };
33 struct mp_config_table
34 {
35 char mpc_signature[4];
36 #define MPC_SIGNATURE "PCMP"
37 unsigned short mpc_length; /* Size of table */
38 char mpc_spec; /* 0x01 */
39 char mpc_checksum;
40 char mpc_oem[8];
41 char mpc_productid[12];
42 unsigned int mpc_oemptr; /* 0 if not present */
43 unsigned short mpc_oemsize; /* 0 if not present */
44 unsigned short mpc_oemcount;
45 unsigned int mpc_lapic; /* APIC address */
46 unsigned int reserved;
47 };
49 /* Followed by entries */
51 #define MP_PROCESSOR 0
52 #define MP_BUS 1
53 #define MP_IOAPIC 2
54 #define MP_INTSRC 3
55 #define MP_LINTSRC 4
56 #define MP_TRANSLATION 192 /* Used by IBM NUMA-Q to describe node locality */
58 struct mpc_config_processor
59 {
60 unsigned char mpc_type;
61 unsigned char mpc_apicid; /* Local APIC number */
62 unsigned char mpc_apicver; /* Its versions */
63 unsigned char mpc_cpuflag;
64 #define CPU_ENABLED 1 /* Processor is available */
65 #define CPU_BOOTPROCESSOR 2 /* Processor is the BP */
66 unsigned int mpc_cpufeature;
67 #define CPU_STEPPING_MASK 0x0F
68 #define CPU_MODEL_MASK 0xF0
69 #define CPU_FAMILY_MASK 0xF00
70 unsigned int mpc_featureflag; /* CPUID feature value */
71 unsigned int mpc_reserved[2];
72 };
74 struct mpc_config_bus
75 {
76 unsigned char mpc_type;
77 unsigned char mpc_busid;
78 unsigned char mpc_bustype[6];
79 };
81 /* List of Bus Type string values, Intel MP Spec. */
82 #define BUSTYPE_EISA "EISA"
83 #define BUSTYPE_ISA "ISA"
84 #define BUSTYPE_INTERN "INTERN" /* Internal BUS */
85 #define BUSTYPE_MCA "MCA"
86 #define BUSTYPE_VL "VL" /* Local bus */
87 #define BUSTYPE_PCI "PCI"
88 #define BUSTYPE_PCMCIA "PCMCIA"
89 #define BUSTYPE_CBUS "CBUS"
90 #define BUSTYPE_CBUSII "CBUSII"
91 #define BUSTYPE_FUTURE "FUTURE"
92 #define BUSTYPE_MBI "MBI"
93 #define BUSTYPE_MBII "MBII"
94 #define BUSTYPE_MPI "MPI"
95 #define BUSTYPE_MPSA "MPSA"
96 #define BUSTYPE_NUBUS "NUBUS"
97 #define BUSTYPE_TC "TC"
98 #define BUSTYPE_VME "VME"
99 #define BUSTYPE_XPRESS "XPRESS"
100 #define BUSTYPE_NEC98 "NEC98"
102 struct mpc_config_ioapic
103 {
104 unsigned char mpc_type;
105 unsigned char mpc_apicid;
106 unsigned char mpc_apicver;
107 unsigned char mpc_flags;
108 #define MPC_APIC_USABLE 0x01
109 unsigned int mpc_apicaddr;
110 };
112 struct mpc_config_intsrc
113 {
114 unsigned char mpc_type;
115 unsigned char mpc_irqtype;
116 unsigned short mpc_irqflag;
117 unsigned char mpc_srcbus;
118 unsigned char mpc_srcbusirq;
119 unsigned char mpc_dstapic;
120 unsigned char mpc_dstirq;
121 };
123 enum mp_irq_source_types {
124 mp_INT = 0,
125 mp_NMI = 1,
126 mp_SMI = 2,
127 mp_ExtINT = 3
128 };
130 #define MP_IRQDIR_DEFAULT 0
131 #define MP_IRQDIR_HIGH 1
132 #define MP_IRQDIR_LOW 3
135 struct mpc_config_lintsrc
136 {
137 unsigned char mpc_type;
138 unsigned char mpc_irqtype;
139 unsigned short mpc_irqflag;
140 unsigned char mpc_srcbusid;
141 unsigned char mpc_srcbusirq;
142 unsigned char mpc_destapic;
143 #define MP_APIC_ALL 0xFF
144 unsigned char mpc_destapiclint;
145 };
147 struct mp_config_oemtable
148 {
149 char oem_signature[4];
150 #define MPC_OEM_SIGNATURE "_OEM"
151 unsigned short oem_length; /* Size of table */
152 char oem_rev; /* 0x01 */
153 char oem_checksum;
154 char mpc_oem[8];
155 };
157 struct mpc_config_translation
158 {
159 unsigned char mpc_type;
160 unsigned char trans_len;
161 unsigned char trans_type;
162 unsigned char trans_quad;
163 unsigned char trans_global;
164 unsigned char trans_local;
165 unsigned short trans_reserved;
166 };
168 /*
169 * Default configurations
170 *
171 * 1 2 CPU ISA 82489DX
172 * 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
173 * 3 2 CPU EISA 82489DX
174 * 4 2 CPU MCA 82489DX
175 * 5 2 CPU ISA+PCI
176 * 6 2 CPU EISA+PCI
177 * 7 2 CPU MCA+PCI
178 */
180 enum mp_bustype {
181 MP_BUS_ISA = 1,
182 MP_BUS_EISA,
183 MP_BUS_PCI,
184 MP_BUS_MCA,
185 MP_BUS_NEC98
186 };
187 #endif