ia64/xen-unstable

view xen/include/asm-x86/config.h @ 15812:86a154e1ef5d

[HVM] Shadow: don't shadow the p2m table.
For HVM vcpus with paging disabled, we used to shadow the p2m table,
and skip the p2m lookup to go from gfn to mfn. Instead, we now
provide a simple pagetable that gives a one-to-one mapping of 4GB, and
shadow that, making the translations from gfn to mfn via the p2m.
This removes the paging-disabled special-case code from the shadow
fault handler, and allows us to expand the p2m interface, since all HVM
translations now go through the same p2m lookups.
Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
author Tim Deegan <Tim.Deegan@xensource.com>
date Fri Aug 31 11:06:22 2007 +0100 (2007-08-31)
parents 3c28bc13a3f8
children 66fa2bc70e2a
line source
1 /******************************************************************************
2 * config.h
3 *
4 * A Linux-style configuration list.
5 */
7 #ifndef __X86_CONFIG_H__
8 #define __X86_CONFIG_H__
10 #if defined(__x86_64__)
11 # define CONFIG_PAGING_LEVELS 4
12 #elif defined(CONFIG_X86_PAE)
13 # define CONFIG_PAGING_LEVELS 3
14 #else
15 # define CONFIG_PAGING_LEVELS 2
16 #endif
18 #define CONFIG_X86 1
19 #define CONFIG_X86_HT 1
20 #define CONFIG_PAGING_ASSISTANCE 1
21 #define CONFIG_SMP 1
22 #define CONFIG_X86_LOCAL_APIC 1
23 #define CONFIG_X86_GOOD_APIC 1
24 #define CONFIG_X86_IO_APIC 1
25 #define CONFIG_X86_PM_TIMER 1
26 #define CONFIG_HPET_TIMER 1
27 #define CONFIG_X86_MCE_P4THERMAL 1
28 #define CONFIG_NUMA 1
29 #define CONFIG_DISCONTIGMEM 1
30 #define CONFIG_NUMA_EMU 1
32 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */
33 #define CONFIG_X86_L1_CACHE_SHIFT 7
35 #define CONFIG_ACPI 1
36 #define CONFIG_ACPI_BOOT 1
37 #define CONFIG_ACPI_SLEEP 1
38 #define CONFIG_ACPI_NUMA 1
39 #define CONFIG_ACPI_SRAT 1
41 #define CONFIG_VGA 1
43 #define CONFIG_HOTPLUG 1
44 #define CONFIG_HOTPLUG_CPU 1
46 #define HZ 100
48 #define OPT_CONSOLE_STR "com1,vga"
50 #ifdef MAX_PHYS_CPUS
51 #define NR_CPUS MAX_PHYS_CPUS
52 #else
53 #define NR_CPUS 32
54 #endif
56 #if defined(__i386__) && (NR_CPUS > 32)
57 #error "Maximum of 32 physical processors supported by Xen on x86_32"
58 #endif
60 #ifdef CONFIG_X86_SUPERVISOR_MODE_KERNEL
61 # define supervisor_mode_kernel (1)
62 #else
63 # define supervisor_mode_kernel (0)
64 #endif
66 /* Linkage for x86 */
67 #define __ALIGN .align 16,0x90
68 #define __ALIGN_STR ".align 16,0x90"
69 #ifdef __ASSEMBLY__
70 #define ALIGN __ALIGN
71 #define ALIGN_STR __ALIGN_STR
72 #define ENTRY(name) \
73 .globl name; \
74 ALIGN; \
75 name:
76 #endif
78 #define NR_hypercalls 64
80 #ifndef NDEBUG
81 #define MEMORY_GUARD
82 #endif
84 #ifdef __i386__
85 #define STACK_ORDER 2
86 #else
87 #define STACK_ORDER 3
88 #endif
89 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER)
91 /* Primary stack is restricted to 8kB by guard pages. */
92 #define PRIMARY_STACK_SIZE 8192
94 #define CONFIG_DMA_BITSIZE 32
96 #define BOOT_TRAMPOLINE 0x90000
97 #define bootsym_phys(sym) \
98 (((unsigned long)&(sym)-(unsigned long)&trampoline_start)+BOOT_TRAMPOLINE)
99 #define bootsym(sym) \
100 (*RELOC_HIDE((typeof(&(sym)))__va(__pa(&(sym))), \
101 BOOT_TRAMPOLINE-__pa(trampoline_start)))
102 #ifndef __ASSEMBLY__
103 extern char trampoline_start[], trampoline_end[];
104 extern char trampoline_realmode_entry[];
105 extern unsigned int trampoline_xen_phys_start;
106 extern unsigned char trampoline_cpu_started;
107 extern char wakeup_start[];
108 extern unsigned int video_mode, video_flags;
109 #endif
111 #if defined(__x86_64__)
113 #define CONFIG_X86_64 1
114 #define CONFIG_COMPAT 1
116 #define asmlinkage
118 #define XENHEAP_DEFAULT_MB (16)
120 #define PML4_ENTRY_BITS 39
121 #ifndef __ASSEMBLY__
122 #define PML4_ENTRY_BYTES (1UL << PML4_ENTRY_BITS)
123 #define PML4_ADDR(_slot) \
124 ((((_slot ## UL) >> 8) * 0xffff000000000000UL) | \
125 (_slot ## UL << PML4_ENTRY_BITS))
126 #else
127 #define PML4_ENTRY_BYTES (1 << PML4_ENTRY_BITS)
128 #define PML4_ADDR(_slot) \
129 (((_slot >> 8) * 0xffff000000000000) | (_slot << PML4_ENTRY_BITS))
130 #endif
132 /*
133 * Memory layout:
134 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255]
135 * Guest-defined use (see below for compatibility mode guests).
136 * 0x0000800000000000 - 0xffff7fffffffffff [16EB]
137 * Inaccessible: current arch only supports 48-bit sign-extended VAs.
138 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256]
139 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
140 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256]
141 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE).
142 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257]
143 * Reserved for future use.
144 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258]
145 * Guest linear page table.
146 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259]
147 * Shadow linear page table.
148 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260]
149 * Per-domain mappings (e.g., GDT, LDT).
150 * 0xffff828000000000 - 0xffff8283ffffffff [16GB, 2^34 bytes, PML4:261]
151 * Machine-to-phys translation table.
152 * 0xffff828400000000 - 0xffff8287ffffffff [16GB, 2^34 bytes, PML4:261]
153 * Page-frame information array.
154 * 0xffff828800000000 - 0xffff828bffffffff [16GB, 2^34 bytes, PML4:261]
155 * ioremap()/fixmap area.
156 * 0xffff828c00000000 - 0xffff828c3fffffff [1GB, 2^30 bytes, PML4:261]
157 * Compatibility machine-to-phys translation table.
158 * 0xffff828c40000000 - 0xffff828c7fffffff [1GB, 2^30 bytes, PML4:261]
159 * High read-only compatibility machine-to-phys translation table.
160 * 0xffff828c80000000 - 0xffff828cbfffffff [1GB, 2^30 bytes, PML4:261]
161 * Xen text, static data, bss.
162 * 0xffff828cc0000000 - 0xffff82ffffffffff [461GB, PML4:261]
163 * Reserved for future use.
164 * 0xffff830000000000 - 0xffff83ffffffffff [1TB, 2^40 bytes, PML4:262-263]
165 * 1:1 direct mapping of all physical memory.
166 * 0xffff840000000000 - 0xffff87ffffffffff [4TB, 2^42 bytes, PML4:264-271]
167 * Reserved for future use.
168 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511]
169 * Guest-defined use.
170 *
171 * Compatibility guest area layout:
172 * 0x0000000000000000 - 0x00000000f57fffff [3928MB, PML4:0]
173 * Guest-defined use.
174 * 0x00000000f5800000 - 0x00000000ffffffff [168MB, PML4:0]
175 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
176 * 0x0000000100000000 - 0x0000007fffffffff [508GB, PML4:0]
177 * Unused.
178 * 0x0000008000000000 - 0x000000ffffffffff [512GB, 2^39 bytes, PML4:1]
179 * Hypercall argument translation area.
180 * 0x0000010000000000 - 0x00007fffffffffff [127TB, 2^46 bytes, PML4:2-255]
181 * Reserved for future use.
182 */
185 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256
186 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271
187 #define ROOT_PAGETABLE_XEN_SLOTS \
188 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1)
190 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */
191 #define HYPERVISOR_VIRT_START (PML4_ADDR(256))
192 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16)
193 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */
194 #define RO_MPT_VIRT_START (PML4_ADDR(256))
195 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + PML4_ENTRY_BYTES/2)
196 /* Slot 258: linear page table (guest table). */
197 #define LINEAR_PT_VIRT_START (PML4_ADDR(258))
198 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
199 /* Slot 259: linear page table (shadow table). */
200 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259))
201 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
202 /* Slot 260: per-domain mappings. */
203 #define PERDOMAIN_VIRT_START (PML4_ADDR(260))
204 #define PERDOMAIN_VIRT_END (PERDOMAIN_VIRT_START + (PERDOMAIN_MBYTES<<20))
205 #define PERDOMAIN_MBYTES ((unsigned long)GDT_LDT_MBYTES)
206 /* Slot 261: machine-to-phys conversion table (16GB). */
207 #define RDWR_MPT_VIRT_START (PML4_ADDR(261))
208 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + (16UL<<30))
209 /* Slot 261: page-frame information array (16GB). */
210 #define FRAMETABLE_VIRT_START (RDWR_MPT_VIRT_END)
211 #define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + (16UL<<30))
212 /* Slot 261: ioremap()/fixmap area (16GB). */
213 #define IOREMAP_VIRT_START (FRAMETABLE_VIRT_END)
214 #define IOREMAP_VIRT_END (IOREMAP_VIRT_START + (16UL<<30))
215 /* Slot 261: compatibility machine-to-phys conversion table (1GB). */
216 #define RDWR_COMPAT_MPT_VIRT_START IOREMAP_VIRT_END
217 #define RDWR_COMPAT_MPT_VIRT_END (RDWR_COMPAT_MPT_VIRT_START + (1UL << 30))
218 /* Slot 261: high read-only compat machine-to-phys conversion table (1GB). */
219 #define HIRO_COMPAT_MPT_VIRT_START RDWR_COMPAT_MPT_VIRT_END
220 #define HIRO_COMPAT_MPT_VIRT_END (HIRO_COMPAT_MPT_VIRT_START + (1UL << 30))
221 /* Slot 261: xen text, static data and bss (1GB). */
222 #define XEN_VIRT_START (HIRO_COMPAT_MPT_VIRT_END)
223 #define XEN_VIRT_END (XEN_VIRT_START + (1UL << 30))
224 /* Slot 262-263: A direct 1:1 mapping of all of physical memory. */
225 #define DIRECTMAP_VIRT_START (PML4_ADDR(262))
226 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + PML4_ENTRY_BYTES*2)
228 #ifndef __ASSEMBLY__
230 /* This is not a fixed value, just a lower limit. */
231 #define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000
232 #define HYPERVISOR_COMPAT_VIRT_START(d) ((d)->arch.hv_compat_vstart)
233 #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START
234 #define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000
235 #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \
236 ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2)
238 #define COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) \
239 l2_table_offset(HYPERVISOR_COMPAT_VIRT_START(d))
240 #define COMPAT_L2_PAGETABLE_LAST_XEN_SLOT l2_table_offset(~0U)
241 #define COMPAT_L2_PAGETABLE_XEN_SLOTS(d) \
242 (COMPAT_L2_PAGETABLE_LAST_XEN_SLOT - COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) + 1)
244 #endif
246 #define COMPAT_ARG_XLAT_VIRT_BASE (1UL << ROOT_PAGETABLE_SHIFT)
247 #define COMPAT_ARG_XLAT_SHIFT 0
248 #define COMPAT_ARG_XLAT_PAGES (1U << COMPAT_ARG_XLAT_SHIFT)
249 #define COMPAT_ARG_XLAT_SIZE (COMPAT_ARG_XLAT_PAGES << PAGE_SHIFT)
250 #define COMPAT_ARG_XLAT_VIRT_START(vcpu_id) \
251 (COMPAT_ARG_XLAT_VIRT_BASE + ((unsigned long)(vcpu_id) << \
252 (PAGE_SHIFT + COMPAT_ARG_XLAT_SHIFT + 1)))
254 #define PGT_base_page_table PGT_l4_page_table
256 #define __HYPERVISOR_CS64 0xe008
257 #define __HYPERVISOR_CS32 0xe038
258 #define __HYPERVISOR_CS __HYPERVISOR_CS64
259 #define __HYPERVISOR_DS64 0x0000
260 #define __HYPERVISOR_DS32 0xe010
261 #define __HYPERVISOR_DS __HYPERVISOR_DS64
263 /* For generic assembly code: use macros to define operation/operand sizes. */
264 #define __OS "q" /* Operation Suffix */
265 #define __OP "r" /* Operand Prefix */
266 #define __FIXUP_ALIGN ".align 8"
267 #define __FIXUP_WORD ".quad"
269 #elif defined(__i386__)
271 #define CONFIG_X86_32 1
272 #define CONFIG_DOMAIN_PAGE 1
274 #define asmlinkage __attribute__((regparm(0)))
276 /*
277 * Memory layout (high to low): SIZE PAE-SIZE
278 * ------ ------
279 * I/O remapping area ( 4MB)
280 * Direct-map (1:1) area [Xen code/data/heap] (12MB)
281 * Per-domain mappings (inc. 4MB map_domain_page cache) ( 8MB)
282 * Shadow linear pagetable ( 4MB) ( 8MB)
283 * Guest linear pagetable ( 4MB) ( 8MB)
284 * Machine-to-physical translation table [writable] ( 4MB) (16MB)
285 * Frame-info table (24MB) (96MB)
286 * * Start of guest inaccessible area
287 * Machine-to-physical translation table [read-only] ( 4MB) (16MB)
288 * * Start of guest unmodifiable area
289 */
291 #define IOREMAP_MBYTES 4
292 #define DIRECTMAP_MBYTES 12
293 #define MAPCACHE_MBYTES 4
294 #define PERDOMAIN_MBYTES 8
296 #ifdef CONFIG_X86_PAE
297 # define LINEARPT_MBYTES 8
298 # define MACHPHYS_MBYTES 16 /* 1 MB needed per 1 GB memory */
299 # define FRAMETABLE_MBYTES (MACHPHYS_MBYTES * 6)
300 #else
301 # define LINEARPT_MBYTES 4
302 # define MACHPHYS_MBYTES 4
303 # define FRAMETABLE_MBYTES 24
304 #endif
306 #define IOREMAP_VIRT_END 0UL
307 #define IOREMAP_VIRT_START (IOREMAP_VIRT_END - (IOREMAP_MBYTES<<20))
308 #define DIRECTMAP_VIRT_END IOREMAP_VIRT_START
309 #define DIRECTMAP_VIRT_START (DIRECTMAP_VIRT_END - (DIRECTMAP_MBYTES<<20))
310 #define MAPCACHE_VIRT_END DIRECTMAP_VIRT_START
311 #define MAPCACHE_VIRT_START (MAPCACHE_VIRT_END - (MAPCACHE_MBYTES<<20))
312 #define PERDOMAIN_VIRT_END DIRECTMAP_VIRT_START
313 #define PERDOMAIN_VIRT_START (PERDOMAIN_VIRT_END - (PERDOMAIN_MBYTES<<20))
314 #define SH_LINEAR_PT_VIRT_END PERDOMAIN_VIRT_START
315 #define SH_LINEAR_PT_VIRT_START (SH_LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
316 #define LINEAR_PT_VIRT_END SH_LINEAR_PT_VIRT_START
317 #define LINEAR_PT_VIRT_START (LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
318 #define RDWR_MPT_VIRT_END LINEAR_PT_VIRT_START
319 #define RDWR_MPT_VIRT_START (RDWR_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
320 #define FRAMETABLE_VIRT_END RDWR_MPT_VIRT_START
321 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - (FRAMETABLE_MBYTES<<20))
322 #define RO_MPT_VIRT_END FRAMETABLE_VIRT_START
323 #define RO_MPT_VIRT_START (RO_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
325 #define XENHEAP_DEFAULT_MB (DIRECTMAP_MBYTES)
326 #define DIRECTMAP_PHYS_END (DIRECTMAP_MBYTES<<20)
328 /* Maximum linear address accessible via guest memory segments. */
329 #define GUEST_SEGMENT_MAX_ADDR RO_MPT_VIRT_END
331 #ifdef CONFIG_X86_PAE
332 /* Hypervisor owns top 168MB of virtual address space. */
333 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xF5800000)
334 #else
335 /* Hypervisor owns top 64MB of virtual address space. */
336 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xFC000000)
337 #endif
339 #define L2_PAGETABLE_FIRST_XEN_SLOT \
340 (HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT)
341 #define L2_PAGETABLE_LAST_XEN_SLOT \
342 (~0UL >> L2_PAGETABLE_SHIFT)
343 #define L2_PAGETABLE_XEN_SLOTS \
344 (L2_PAGETABLE_LAST_XEN_SLOT - L2_PAGETABLE_FIRST_XEN_SLOT + 1)
346 #ifdef CONFIG_X86_PAE
347 # define PGT_base_page_table PGT_l3_page_table
348 #else
349 # define PGT_base_page_table PGT_l2_page_table
350 #endif
352 #define __HYPERVISOR_CS 0xe008
353 #define __HYPERVISOR_DS 0xe010
355 /* For generic assembly code: use macros to define operation/operand sizes. */
356 #define __OS "l" /* Operation Suffix */
357 #define __OP "e" /* Operand Prefix */
358 #define __FIXUP_ALIGN ".align 4"
359 #define __FIXUP_WORD ".long"
361 #endif /* __i386__ */
363 #ifndef __ASSEMBLY__
364 extern unsigned long xen_phys_start, xenheap_phys_start, xenheap_phys_end;
365 #endif
367 /* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */
368 #define GDT_LDT_VCPU_SHIFT 5
369 #define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT)
370 #define GDT_LDT_MBYTES (MAX_VIRT_CPUS >> (20-GDT_LDT_VCPU_VA_SHIFT))
371 #define GDT_LDT_VIRT_START PERDOMAIN_VIRT_START
372 #define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20))
374 /* The address of a particular VCPU's GDT or LDT. */
375 #define GDT_VIRT_START(v) \
376 (PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT))
377 #define LDT_VIRT_START(v) \
378 (GDT_VIRT_START(v) + (64*1024))
380 #define PDPT_L1_ENTRIES \
381 ((PERDOMAIN_VIRT_END - PERDOMAIN_VIRT_START) >> PAGE_SHIFT)
382 #define PDPT_L2_ENTRIES \
383 ((PDPT_L1_ENTRIES + (1 << PAGETABLE_ORDER) - 1) >> PAGETABLE_ORDER)
385 #if defined(__x86_64__)
386 #define ELFSIZE 64
387 #else
388 #define ELFSIZE 32
389 #endif
391 #endif /* __X86_CONFIG_H__ */