ia64/xen-unstable

view xen/include/asm-x86/apicdef.h @ 15812:86a154e1ef5d

[HVM] Shadow: don't shadow the p2m table.
For HVM vcpus with paging disabled, we used to shadow the p2m table,
and skip the p2m lookup to go from gfn to mfn. Instead, we now
provide a simple pagetable that gives a one-to-one mapping of 4GB, and
shadow that, making the translations from gfn to mfn via the p2m.
This removes the paging-disabled special-case code from the shadow
fault handler, and allows us to expand the p2m interface, since all HVM
translations now go through the same p2m lookups.
Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
author Tim Deegan <Tim.Deegan@xensource.com>
date Fri Aug 31 11:06:22 2007 +0100 (2007-08-31)
parents f07cf18343f1
children 9fd00ff95068
line source
1 #ifndef __ASM_APICDEF_H
2 #define __ASM_APICDEF_H
4 /*
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
6 *
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
9 */
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
13 #define APIC_ID 0x20
14 #define APIC_ID_MASK (0xFFu<<24)
15 #define GET_APIC_ID(x) (((x)>>24)&0xFFu)
16 #define SET_APIC_ID(x) (((x)<<24))
17 #define APIC_LVR 0x30
18 #define APIC_LVR_MASK 0xFF00FF
19 #define GET_APIC_VERSION(x) ((x)&0xFF)
20 #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF)
21 #define APIC_INTEGRATED(x) ((x)&0xF0)
22 #define APIC_XAPIC(x) ((x) >= 0x14)
23 #define APIC_TASKPRI 0x80
24 #define APIC_TPRI_MASK 0xFF
25 #define APIC_ARBPRI 0x90
26 #define APIC_ARBPRI_MASK 0xFF
27 #define APIC_PROCPRI 0xA0
28 #define APIC_EOI 0xB0
29 #define APIC_EIO_ACK 0x0 /* Write this to the EOI register */
30 #define APIC_RRR 0xC0
31 #define APIC_LDR 0xD0
32 #define APIC_LDR_MASK (0xFF<<24)
33 #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF)
34 #define SET_APIC_LOGICAL_ID(x) (((x)<<24))
35 #define APIC_ALL_CPUS 0xFF
36 #define APIC_DFR 0xE0
37 #define APIC_DFR_CLUSTER 0x0FFFFFFFul
38 #define APIC_DFR_FLAT 0xFFFFFFFFul
39 #define APIC_SPIV 0xF0
40 #define APIC_SPIV_FOCUS_DISABLED (1<<9)
41 #define APIC_SPIV_APIC_ENABLED (1<<8)
42 #define APIC_ISR 0x100
43 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
44 #define APIC_TMR 0x180
45 #define APIC_IRR 0x200
46 #define APIC_ESR 0x280
47 #define APIC_ESR_SEND_CS 0x00001
48 #define APIC_ESR_RECV_CS 0x00002
49 #define APIC_ESR_SEND_ACC 0x00004
50 #define APIC_ESR_RECV_ACC 0x00008
51 #define APIC_ESR_SENDILL 0x00020
52 #define APIC_ESR_RECVILL 0x00040
53 #define APIC_ESR_ILLREGA 0x00080
54 #define APIC_ICR 0x300
55 #define APIC_DEST_SELF 0x40000
56 #define APIC_DEST_ALLINC 0x80000
57 #define APIC_DEST_ALLBUT 0xC0000
58 #define APIC_ICR_RR_MASK 0x30000
59 #define APIC_ICR_RR_INVALID 0x00000
60 #define APIC_ICR_RR_INPROG 0x10000
61 #define APIC_ICR_RR_VALID 0x20000
62 #define APIC_INT_LEVELTRIG 0x08000
63 #define APIC_INT_ASSERT 0x04000
64 #define APIC_ICR_BUSY 0x01000
65 #define APIC_DEST_LOGICAL 0x00800
66 #define APIC_DEST_PHYSICAL 0x00000
67 #define APIC_DM_FIXED 0x00000
68 #define APIC_DM_LOWEST 0x00100
69 #define APIC_DM_SMI 0x00200
70 #define APIC_DM_REMRD 0x00300
71 #define APIC_DM_NMI 0x00400
72 #define APIC_DM_INIT 0x00500
73 #define APIC_DM_STARTUP 0x00600
74 #define APIC_DM_EXTINT 0x00700
75 #define APIC_VECTOR_MASK 0x000FF
76 #define APIC_ICR2 0x310
77 #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF)
78 #define SET_APIC_DEST_FIELD(x) ((x)<<24)
79 #define APIC_LVTT 0x320
80 #define APIC_LVTTHMR 0x330
81 #define APIC_LVTPC 0x340
82 #define APIC_LVT0 0x350
83 #define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
84 #define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
85 #define SET_APIC_TIMER_BASE(x) (((x)<<18))
86 #define APIC_TIMER_BASE_CLKIN 0x0
87 #define APIC_TIMER_BASE_TMBASE 0x1
88 #define APIC_TIMER_BASE_DIV 0x2
89 #define APIC_LVT_TIMER_PERIODIC (1<<17)
90 #define APIC_LVT_MASKED (1<<16)
91 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
92 #define APIC_LVT_REMOTE_IRR (1<<14)
93 #define APIC_INPUT_POLARITY (1<<13)
94 #define APIC_SEND_PENDING (1<<12)
95 #define APIC_MODE_MASK 0x700
96 #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
97 #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
98 #define APIC_MODE_FIXED 0x0
99 #define APIC_MODE_NMI 0x4
100 #define APIC_MODE_EXTINT 0x7
101 #define APIC_LVT1 0x360
102 #define APIC_LVTERR 0x370
103 #define APIC_TMICT 0x380
104 #define APIC_TMCCT 0x390
105 #define APIC_TDCR 0x3E0
106 #define APIC_TDR_DIV_TMBASE (1<<2)
107 #define APIC_TDR_DIV_1 0xB
108 #define APIC_TDR_DIV_2 0x0
109 #define APIC_TDR_DIV_4 0x1
110 #define APIC_TDR_DIV_8 0x2
111 #define APIC_TDR_DIV_16 0x3
112 #define APIC_TDR_DIV_32 0x8
113 #define APIC_TDR_DIV_64 0x9
114 #define APIC_TDR_DIV_128 0xA
116 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
118 #ifdef __i386__
119 #define MAX_IO_APICS 64
120 #else
121 #define MAX_IO_APICS 128
122 #endif
124 /*
125 * the local APIC register structure, memory mapped. Not terribly well
126 * tested, but we might eventually use this one in the future - the
127 * problem why we cannot use it right now is the P5 APIC, it has an
128 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
129 */
130 #define u32 unsigned int
132 #define lapic ((volatile struct local_apic *)APIC_BASE)
134 #ifndef __ASSEMBLY__
135 struct local_apic {
137 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
139 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
141 /*020*/ struct { /* APIC ID Register */
142 u32 __reserved_1 : 24,
143 phys_apic_id : 4,
144 __reserved_2 : 4;
145 u32 __reserved[3];
146 } id;
148 /*030*/ const
149 struct { /* APIC Version Register */
150 u32 version : 8,
151 __reserved_1 : 8,
152 max_lvt : 8,
153 __reserved_2 : 8;
154 u32 __reserved[3];
155 } version;
157 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
159 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
161 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
163 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
165 /*080*/ struct { /* Task Priority Register */
166 u32 priority : 8,
167 __reserved_1 : 24;
168 u32 __reserved_2[3];
169 } tpr;
171 /*090*/ const
172 struct { /* Arbitration Priority Register */
173 u32 priority : 8,
174 __reserved_1 : 24;
175 u32 __reserved_2[3];
176 } apr;
178 /*0A0*/ const
179 struct { /* Processor Priority Register */
180 u32 priority : 8,
181 __reserved_1 : 24;
182 u32 __reserved_2[3];
183 } ppr;
185 /*0B0*/ struct { /* End Of Interrupt Register */
186 u32 eoi;
187 u32 __reserved[3];
188 } eoi;
190 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
192 /*0D0*/ struct { /* Logical Destination Register */
193 u32 __reserved_1 : 24,
194 logical_dest : 8;
195 u32 __reserved_2[3];
196 } ldr;
198 /*0E0*/ struct { /* Destination Format Register */
199 u32 __reserved_1 : 28,
200 model : 4;
201 u32 __reserved_2[3];
202 } dfr;
204 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
205 u32 spurious_vector : 8,
206 apic_enabled : 1,
207 focus_cpu : 1,
208 __reserved_2 : 22;
209 u32 __reserved_3[3];
210 } svr;
212 /*100*/ struct { /* In Service Register */
213 /*170*/ u32 bitfield;
214 u32 __reserved[3];
215 } isr [8];
217 /*180*/ struct { /* Trigger Mode Register */
218 /*1F0*/ u32 bitfield;
219 u32 __reserved[3];
220 } tmr [8];
222 /*200*/ struct { /* Interrupt Request Register */
223 /*270*/ u32 bitfield;
224 u32 __reserved[3];
225 } irr [8];
227 /*280*/ union { /* Error Status Register */
228 struct {
229 u32 send_cs_error : 1,
230 receive_cs_error : 1,
231 send_accept_error : 1,
232 receive_accept_error : 1,
233 __reserved_1 : 1,
234 send_illegal_vector : 1,
235 receive_illegal_vector : 1,
236 illegal_register_address : 1,
237 __reserved_2 : 24;
238 u32 __reserved_3[3];
239 } error_bits;
240 struct {
241 u32 errors;
242 u32 __reserved_3[3];
243 } all_errors;
244 } esr;
246 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
248 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
250 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
252 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
254 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
256 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
258 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
260 /*300*/ struct { /* Interrupt Command Register 1 */
261 u32 vector : 8,
262 delivery_mode : 3,
263 destination_mode : 1,
264 delivery_status : 1,
265 __reserved_1 : 1,
266 level : 1,
267 trigger : 1,
268 __reserved_2 : 2,
269 shorthand : 2,
270 __reserved_3 : 12;
271 u32 __reserved_4[3];
272 } icr1;
274 /*310*/ struct { /* Interrupt Command Register 2 */
275 union {
276 u32 __reserved_1 : 24,
277 phys_dest : 4,
278 __reserved_2 : 4;
279 u32 __reserved_3 : 24,
280 logical_dest : 8;
281 } dest;
282 u32 __reserved_4[3];
283 } icr2;
285 /*320*/ struct { /* LVT - Timer */
286 u32 vector : 8,
287 __reserved_1 : 4,
288 delivery_status : 1,
289 __reserved_2 : 3,
290 mask : 1,
291 timer_mode : 1,
292 __reserved_3 : 14;
293 u32 __reserved_4[3];
294 } lvt_timer;
296 /*330*/ struct { /* LVT - Thermal Sensor */
297 u32 vector : 8,
298 delivery_mode : 3,
299 __reserved_1 : 1,
300 delivery_status : 1,
301 __reserved_2 : 3,
302 mask : 1,
303 __reserved_3 : 15;
304 u32 __reserved_4[3];
305 } lvt_thermal;
307 /*340*/ struct { /* LVT - Performance Counter */
308 u32 vector : 8,
309 delivery_mode : 3,
310 __reserved_1 : 1,
311 delivery_status : 1,
312 __reserved_2 : 3,
313 mask : 1,
314 __reserved_3 : 15;
315 u32 __reserved_4[3];
316 } lvt_pc;
318 /*350*/ struct { /* LVT - LINT0 */
319 u32 vector : 8,
320 delivery_mode : 3,
321 __reserved_1 : 1,
322 delivery_status : 1,
323 polarity : 1,
324 remote_irr : 1,
325 trigger : 1,
326 mask : 1,
327 __reserved_2 : 15;
328 u32 __reserved_3[3];
329 } lvt_lint0;
331 /*360*/ struct { /* LVT - LINT1 */
332 u32 vector : 8,
333 delivery_mode : 3,
334 __reserved_1 : 1,
335 delivery_status : 1,
336 polarity : 1,
337 remote_irr : 1,
338 trigger : 1,
339 mask : 1,
340 __reserved_2 : 15;
341 u32 __reserved_3[3];
342 } lvt_lint1;
344 /*370*/ struct { /* LVT - Error */
345 u32 vector : 8,
346 __reserved_1 : 4,
347 delivery_status : 1,
348 __reserved_2 : 3,
349 mask : 1,
350 __reserved_3 : 15;
351 u32 __reserved_4[3];
352 } lvt_error;
354 /*380*/ struct { /* Timer Initial Count Register */
355 u32 initial_count;
356 u32 __reserved_2[3];
357 } timer_icr;
359 /*390*/ const
360 struct { /* Timer Current Count Register */
361 u32 curr_count;
362 u32 __reserved_2[3];
363 } timer_ccr;
365 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
367 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
369 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
371 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
373 /*3E0*/ struct { /* Timer Divide Configuration Register */
374 u32 divisor : 4,
375 __reserved_1 : 28;
376 u32 __reserved_2[3];
377 } timer_dcr;
379 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
381 } __attribute__ ((packed));
382 #endif /* !__ASSEMBLY__ */
384 #undef u32
386 #endif