ia64/xen-unstable

view linux-2.4-xen-sparse/include/asm-xen/processor.h @ 6538:84ee014ebd41

Merge xen-vtx-unstable.hg
author adsharma@los-vmm.sc.intel.com
date Wed Aug 17 12:34:38 2005 -0800 (2005-08-17)
parents 23979fb12c49 f294acb25858
children 99914b54f7bf
line source
1 /*
2 * include/asm-i386/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
7 #ifndef __ASM_I386_PROCESSOR_H
8 #define __ASM_I386_PROCESSOR_H
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/page.h>
14 #include <asm/types.h>
15 #include <asm/sigcontext.h>
16 #include <asm/cpufeature.h>
17 #include <linux/cache.h>
18 #include <linux/config.h>
19 #include <linux/threads.h>
21 /*
22 * Default implementation of macro that returns current
23 * instruction pointer ("program counter").
24 */
25 #define current_text_addr() ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
27 /*
28 * CPU type and hardware bug flags. Kept separately for each CPU.
29 * Members of this structure are referenced in head.S, so think twice
30 * before touching them. [mj]
31 */
33 struct cpuinfo_x86 {
34 __u8 x86; /* CPU family */
35 __u8 x86_vendor; /* CPU vendor */
36 __u8 x86_model;
37 __u8 x86_mask;
38 char wp_works_ok; /* It doesn't on 386's */
39 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
40 char hard_math;
41 char rfu;
42 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
43 __u32 x86_capability[NCAPINTS];
44 char x86_vendor_id[16];
45 char x86_model_id[64];
46 int x86_cache_size; /* in KB - valid for CPUS which support this
47 call */
48 int fdiv_bug;
49 int f00f_bug;
50 int coma_bug;
51 unsigned long loops_per_jiffy;
52 unsigned long *pgd_quick;
53 unsigned long *pmd_quick;
54 unsigned long *pte_quick;
55 unsigned long pgtable_cache_sz;
56 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
58 #define X86_VENDOR_INTEL 0
59 #define X86_VENDOR_CYRIX 1
60 #define X86_VENDOR_AMD 2
61 #define X86_VENDOR_UMC 3
62 #define X86_VENDOR_NEXGEN 4
63 #define X86_VENDOR_CENTAUR 5
64 #define X86_VENDOR_RISE 6
65 #define X86_VENDOR_TRANSMETA 7
66 #define X86_VENDOR_NSC 8
67 #define X86_VENDOR_SIS 9
68 #define X86_VENDOR_UNKNOWN 0xff
70 /*
71 * capabilities of CPUs
72 */
74 extern struct cpuinfo_x86 boot_cpu_data;
75 extern struct tss_struct init_tss[NR_CPUS];
77 #ifdef CONFIG_SMP
78 extern struct cpuinfo_x86 cpu_data[];
79 #define current_cpu_data cpu_data[smp_processor_id()]
80 #else
81 #define cpu_data (&boot_cpu_data)
82 #define current_cpu_data boot_cpu_data
83 #endif
85 extern char ignore_irq13;
87 extern void identify_cpu(struct cpuinfo_x86 *);
88 extern void print_cpu_info(struct cpuinfo_x86 *);
90 /*
91 * EFLAGS bits
92 */
93 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
94 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
95 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
96 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
97 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
98 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
99 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
100 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
101 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
102 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
103 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
104 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
105 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
106 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
107 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
108 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
109 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
111 /*
112 * Generic CPUID function
113 */
114 static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
115 {
116 __asm__("cpuid"
117 : "=a" (*eax),
118 "=b" (*ebx),
119 "=c" (*ecx),
120 "=d" (*edx)
121 : "0" (op));
122 }
124 /*
125 * CPUID functions returning a single datum
126 */
127 static inline unsigned int cpuid_eax(unsigned int op)
128 {
129 unsigned int eax;
131 __asm__("cpuid"
132 : "=a" (eax)
133 : "0" (op)
134 : "bx", "cx", "dx");
135 return eax;
136 }
137 static inline unsigned int cpuid_ebx(unsigned int op)
138 {
139 unsigned int eax, ebx;
141 __asm__("cpuid"
142 : "=a" (eax), "=b" (ebx)
143 : "0" (op)
144 : "cx", "dx" );
145 return ebx;
146 }
147 static inline unsigned int cpuid_ecx(unsigned int op)
148 {
149 unsigned int eax, ecx;
151 __asm__("cpuid"
152 : "=a" (eax), "=c" (ecx)
153 : "0" (op)
154 : "bx", "dx" );
155 return ecx;
156 }
157 static inline unsigned int cpuid_edx(unsigned int op)
158 {
159 unsigned int eax, edx;
161 __asm__("cpuid"
162 : "=a" (eax), "=d" (edx)
163 : "0" (op)
164 : "bx", "cx");
165 return edx;
166 }
168 /*
169 * Intel CPU features in CR4
170 */
171 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
172 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
173 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
174 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
175 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
176 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
177 #define X86_CR4_MCE 0x0040 /* Machine check enable */
178 #define X86_CR4_PGE 0x0080 /* enable global pages */
179 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
180 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
181 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
183 #define load_cr3(pgdir) \
184 asm volatile("movl %0,%%cr3": :"r" (__pa(pgdir)));
186 extern unsigned long mmu_cr4_features;
188 #include <asm/hypervisor.h>
190 static inline void set_in_cr4 (unsigned long mask)
191 {
192 BUG();
193 }
195 static inline void clear_in_cr4 (unsigned long mask)
196 {
197 BUG();
198 }
200 /*
201 * Cyrix CPU configuration register indexes
202 */
203 #define CX86_CCR0 0xc0
204 #define CX86_CCR1 0xc1
205 #define CX86_CCR2 0xc2
206 #define CX86_CCR3 0xc3
207 #define CX86_CCR4 0xe8
208 #define CX86_CCR5 0xe9
209 #define CX86_CCR6 0xea
210 #define CX86_CCR7 0xeb
211 #define CX86_DIR0 0xfe
212 #define CX86_DIR1 0xff
213 #define CX86_ARR_BASE 0xc4
214 #define CX86_RCR_BASE 0xdc
216 /*
217 * Cyrix CPU indexed register access macros
218 */
220 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
222 #define setCx86(reg, data) do { \
223 outb((reg), 0x22); \
224 outb((data), 0x23); \
225 } while (0)
227 /*
228 * Bus types (default is ISA, but people can check others with these..)
229 */
230 #ifdef CONFIG_EISA
231 extern int EISA_bus;
232 #else
233 #define EISA_bus (0)
234 #endif
235 extern int MCA_bus;
237 /* from system description table in BIOS. Mostly for MCA use, but
238 others may find it useful. */
239 extern unsigned int machine_id;
240 extern unsigned int machine_submodel_id;
241 extern unsigned int BIOS_revision;
242 extern unsigned int mca_pentium_flag;
244 /*
245 * User space process size: 3GB (default).
246 */
247 #define TASK_SIZE (PAGE_OFFSET)
249 /* This decides where the kernel will search for a free chunk of vm
250 * space during mmap's.
251 */
252 #define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
254 /*
255 * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
256 */
257 #define IO_BITMAP_SIZE 32
258 #define IO_BITMAP_BYTES (IO_BITMAP_SIZE * 4)
259 #define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
260 #define INVALID_IO_BITMAP_OFFSET 0x8000
262 struct i387_fsave_struct {
263 long cwd;
264 long swd;
265 long twd;
266 long fip;
267 long fcs;
268 long foo;
269 long fos;
270 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
271 long status; /* software status information */
272 };
274 struct i387_fxsave_struct {
275 unsigned short cwd;
276 unsigned short swd;
277 unsigned short twd;
278 unsigned short fop;
279 long fip;
280 long fcs;
281 long foo;
282 long fos;
283 long mxcsr;
284 long reserved;
285 long st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
286 long xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
287 long padding[56];
288 } __attribute__ ((aligned (16)));
290 struct i387_soft_struct {
291 long cwd;
292 long swd;
293 long twd;
294 long fip;
295 long fcs;
296 long foo;
297 long fos;
298 long st_space[20]; /* 8*10 bytes for each FP-reg = 80 bytes */
299 unsigned char ftop, changed, lookahead, no_update, rm, alimit;
300 struct info *info;
301 unsigned long entry_eip;
302 };
304 union i387_union {
305 struct i387_fsave_struct fsave;
306 struct i387_fxsave_struct fxsave;
307 struct i387_soft_struct soft;
308 };
310 typedef struct {
311 unsigned long seg;
312 } mm_segment_t;
314 struct tss_struct {
315 unsigned short back_link,__blh;
316 unsigned long esp0;
317 unsigned short ss0,__ss0h;
318 unsigned long esp1;
319 unsigned short ss1,__ss1h;
320 unsigned long esp2;
321 unsigned short ss2,__ss2h;
322 unsigned long __cr3;
323 unsigned long eip;
324 unsigned long eflags;
325 unsigned long eax,ecx,edx,ebx;
326 unsigned long esp;
327 unsigned long ebp;
328 unsigned long esi;
329 unsigned long edi;
330 unsigned short es, __esh;
331 unsigned short cs, __csh;
332 unsigned short ss, __ssh;
333 unsigned short ds, __dsh;
334 unsigned short fs, __fsh;
335 unsigned short gs, __gsh;
336 unsigned short ldt, __ldth;
337 unsigned short trace, bitmap;
338 unsigned long io_bitmap[IO_BITMAP_SIZE+1];
339 /*
340 * pads the TSS to be cacheline-aligned (size is 0x100)
341 */
342 unsigned long __cacheline_filler[5];
343 };
345 struct thread_struct {
346 unsigned long esp0;
347 unsigned long eip;
348 unsigned long esp;
349 unsigned long fs;
350 unsigned long gs;
351 unsigned int io_pl;
352 /* Hardware debugging registers */
353 unsigned long debugreg[8]; /* %%db0-7 debug registers */
354 /* fault info */
355 unsigned long cr2, trap_no, error_code;
356 /* floating point info */
357 union i387_union i387;
358 /* virtual 86 mode info */
359 struct vm86_struct * vm86_info;
360 unsigned long screen_bitmap;
361 unsigned long v86flags, v86mask, saved_esp0;
362 };
364 #define INIT_THREAD { sizeof(init_stack) + (long) &init_stack, \
365 0, 0, 0, 0, 0, 0, {0}, 0, 0, 0, {{0}}, 0, 0, 0, 0, 0 }
367 #define INIT_TSS { \
368 0,0, /* back_link, __blh */ \
369 sizeof(init_stack) + (long) &init_stack, /* esp0 */ \
370 __KERNEL_DS, 0, /* ss0 */ \
371 0,0,0,0,0,0, /* stack1, stack2 */ \
372 0, /* cr3 */ \
373 0,0, /* eip,eflags */ \
374 0,0,0,0, /* eax,ecx,edx,ebx */ \
375 0,0,0,0, /* esp,ebp,esi,edi */ \
376 0,0,0,0,0,0, /* es,cs,ss */ \
377 0,0,0,0,0,0, /* ds,fs,gs */ \
378 0,0, /* ldt */ \
379 0, INVALID_IO_BITMAP_OFFSET, /* tace, bitmap */ \
380 {~0, } /* ioperm */ \
381 }
383 #define start_thread(regs, new_eip, new_esp) do { \
384 __asm__("movl %0,%%fs ; movl %0,%%gs": :"r" (0)); \
385 set_fs(USER_DS); \
386 regs->xds = __USER_DS; \
387 regs->xes = __USER_DS; \
388 regs->xss = __USER_DS; \
389 regs->xcs = __USER_CS; \
390 regs->eip = new_eip; \
391 regs->esp = new_esp; \
392 } while (0)
394 /* Forward declaration, a strange C thing */
395 struct task_struct;
396 struct mm_struct;
398 /* Free all resources held by a thread. */
399 extern void release_thread(struct task_struct *);
400 /*
401 * create a kernel thread without removing it from tasklists
402 */
403 extern int arch_kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
405 /* Copy and release all segment info associated with a VM
406 * Unusable due to lack of error handling, use {init_new,destroy}_context
407 * instead.
408 */
409 static inline void copy_segments(struct task_struct *p, struct mm_struct * mm) { }
410 static inline void release_segments(struct mm_struct * mm) { }
412 /*
413 * Return saved PC of a blocked thread.
414 */
415 static inline unsigned long thread_saved_pc(struct thread_struct *t)
416 {
417 return ((unsigned long *)t->esp)[3];
418 }
420 unsigned long get_wchan(struct task_struct *p);
421 #define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1019])
422 #define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)))[1022])
424 #define THREAD_SIZE (2*PAGE_SIZE)
425 #define alloc_task_struct() ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
426 #define free_task_struct(p) free_pages((unsigned long) (p), 1)
427 #define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
429 #define init_task (init_task_union.task)
430 #define init_stack (init_task_union.stack)
432 struct microcode {
433 unsigned int hdrver;
434 unsigned int rev;
435 unsigned int date;
436 unsigned int sig;
437 unsigned int cksum;
438 unsigned int ldrver;
439 unsigned int pf;
440 unsigned int reserved[5];
441 unsigned int bits[500];
442 };
444 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
445 #define MICROCODE_IOCFREE _IO('6',0)
447 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
448 static inline void rep_nop(void)
449 {
450 __asm__ __volatile__("rep;nop" ::: "memory");
451 }
453 #define cpu_relax() rep_nop()
455 /* Prefetch instructions for Pentium III and AMD Athlon */
456 #if defined(CONFIG_MPENTIUMIII) || defined (CONFIG_MPENTIUM4)
458 #define ARCH_HAS_PREFETCH
459 extern inline void prefetch(const void *x)
460 {
461 __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
462 }
464 #elif CONFIG_X86_USE_3DNOW
466 #define ARCH_HAS_PREFETCH
467 #define ARCH_HAS_PREFETCHW
468 #define ARCH_HAS_SPINLOCK_PREFETCH
470 extern inline void prefetch(const void *x)
471 {
472 __asm__ __volatile__ ("prefetch (%0)" : : "r"(x));
473 }
475 extern inline void prefetchw(const void *x)
476 {
477 __asm__ __volatile__ ("prefetchw (%0)" : : "r"(x));
478 }
479 #define spin_lock_prefetch(x) prefetchw(x)
481 #endif
483 #endif /* __ASM_I386_PROCESSOR_H */