ia64/xen-unstable

view xen/include/asm-x86/processor.h @ 19169:8303bd33d030

x86: recover pat value for bsp after S3 resume.

host pat is set to cover all memory types by Xen, which is
necessary to support guest mtrr/pat, especially when device
is passthroughed with VT-d. However pat on bsp is not=20
recovered which could make assigned device defunct after S3
resume

Signed-off-by Kevin Tian <kevin.tian@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Feb 05 12:14:09 2009 +0000 (2009-02-05)
parents 9f9ba1a7cc92
children 0e1449d6f231
line source
2 /* Portions are: Copyright (c) 1994 Linus Torvalds */
4 #ifndef __ASM_X86_PROCESSOR_H
5 #define __ASM_X86_PROCESSOR_H
7 #ifndef __ASSEMBLY__
8 #include <xen/config.h>
9 #include <xen/cache.h>
10 #include <xen/types.h>
11 #include <xen/smp.h>
12 #include <xen/percpu.h>
13 #include <public/xen.h>
14 #include <asm/types.h>
15 #include <asm/cpufeature.h>
16 #include <asm/desc.h>
17 #endif
19 /*
20 * CPU vendor IDs
21 */
22 #define X86_VENDOR_INTEL 0
23 #define X86_VENDOR_CYRIX 1
24 #define X86_VENDOR_AMD 2
25 #define X86_VENDOR_UMC 3
26 #define X86_VENDOR_NEXGEN 4
27 #define X86_VENDOR_CENTAUR 5
28 #define X86_VENDOR_RISE 6
29 #define X86_VENDOR_TRANSMETA 7
30 #define X86_VENDOR_NSC 8
31 #define X86_VENDOR_NUM 9
32 #define X86_VENDOR_UNKNOWN 0xff
34 /*
35 * EFLAGS bits
36 */
37 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
38 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
39 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
40 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
41 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
42 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
43 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
44 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
45 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
46 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
47 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
48 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
49 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
50 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
51 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
52 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
53 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
55 /*
56 * Intel CPU flags in CR0
57 */
58 #define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */
59 #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */
60 #define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */
61 #define X86_CR0_TS 0x00000008 /* Task Switched (RW) */
62 #define X86_CR0_ET 0x00000010 /* Extension type (RO) */
63 #define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */
64 #define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */
65 #define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */
66 #define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */
67 #define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */
68 #define X86_CR0_PG 0x80000000 /* Paging (RW) */
70 /*
71 * Intel CPU features in CR4
72 */
73 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
74 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
75 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
76 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
77 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
78 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
79 #define X86_CR4_MCE 0x0040 /* Machine check enable */
80 #define X86_CR4_PGE 0x0080 /* enable global pages */
81 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
82 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
83 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
84 #define X86_CR4_VMXE 0x2000 /* enable VMX */
85 #define X86_CR4_SMXE 0x4000 /* enable SMX */
87 /*
88 * Trap/fault mnemonics.
89 */
90 #define TRAP_divide_error 0
91 #define TRAP_debug 1
92 #define TRAP_nmi 2
93 #define TRAP_int3 3
94 #define TRAP_overflow 4
95 #define TRAP_bounds 5
96 #define TRAP_invalid_op 6
97 #define TRAP_no_device 7
98 #define TRAP_double_fault 8
99 #define TRAP_copro_seg 9
100 #define TRAP_invalid_tss 10
101 #define TRAP_no_segment 11
102 #define TRAP_stack_error 12
103 #define TRAP_gp_fault 13
104 #define TRAP_page_fault 14
105 #define TRAP_spurious_int 15
106 #define TRAP_copro_error 16
107 #define TRAP_alignment_check 17
108 #define TRAP_machine_check 18
109 #define TRAP_simd_error 19
111 /* Set for entry via SYSCALL. Informs return code to use SYSRETQ not IRETQ. */
112 /* NB. Same as VGCF_in_syscall. No bits in common with any other TRAP_ defn. */
113 #define TRAP_syscall 256
115 /* Boolean return code: the reason for a fault has been fixed. */
116 #define EXCRET_fault_fixed 1
118 /* 'trap_bounce' flags values */
119 #define TBF_EXCEPTION 1
120 #define TBF_EXCEPTION_ERRCODE 2
121 #define TBF_INTERRUPT 8
122 #define TBF_FAILSAFE 16
124 /* 'arch_vcpu' flags values */
125 #define _TF_kernel_mode 0
126 #define TF_kernel_mode (1<<_TF_kernel_mode)
128 /* #PF error code values. */
129 #define PFEC_page_present (1U<<0)
130 #define PFEC_write_access (1U<<1)
131 #define PFEC_user_mode (1U<<2)
132 #define PFEC_reserved_bit (1U<<3)
133 #define PFEC_insn_fetch (1U<<4)
135 #ifndef __ASSEMBLY__
137 struct domain;
138 struct vcpu;
140 /*
141 * Default implementation of macro that returns current
142 * instruction pointer ("program counter").
143 */
144 #ifdef __x86_64__
145 #define current_text_addr() ({ \
146 void *pc; \
147 asm ( "leaq 1f(%%rip),%0\n1:" : "=r" (pc) ); \
148 pc; \
149 })
150 #else
151 #define current_text_addr() ({ \
152 void *pc; \
153 asm ( "movl $1f,%0\n1:" : "=g" (pc) ); \
154 pc; \
155 })
156 #endif
158 struct cpuinfo_x86 {
159 __u8 x86; /* CPU family */
160 __u8 x86_vendor; /* CPU vendor */
161 __u8 x86_model;
162 __u8 x86_mask;
163 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
164 unsigned int x86_capability[NCAPINTS];
165 char x86_vendor_id[16];
166 char x86_model_id[64];
167 int x86_cache_size; /* in KB - valid for CPUS which support this call */
168 int x86_cache_alignment; /* In bytes */
169 int x86_power;
170 __u32 x86_max_cores; /* cpuid returned max cores value */
171 __u32 booted_cores; /* number of cores as seen by OS */
172 __u32 x86_num_siblings; /* cpuid logical cpus per chip value */
173 __u32 apicid;
174 unsigned short x86_clflush_size;
175 } __cacheline_aligned;
177 /*
178 * capabilities of CPUs
179 */
181 extern struct cpuinfo_x86 boot_cpu_data;
183 #ifdef CONFIG_SMP
184 extern struct cpuinfo_x86 cpu_data[];
185 #define current_cpu_data cpu_data[smp_processor_id()]
186 #else
187 #define cpu_data (&boot_cpu_data)
188 #define current_cpu_data boot_cpu_data
189 #endif
191 extern u64 host_pat;
192 extern int phys_proc_id[NR_CPUS];
193 extern int cpu_core_id[NR_CPUS];
195 extern void identify_cpu(struct cpuinfo_x86 *);
196 extern void setup_clear_cpu_cap(unsigned int);
197 extern void print_cpu_info(struct cpuinfo_x86 *);
198 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
199 extern void dodgy_tsc(void);
201 #ifdef CONFIG_X86_HT
202 extern void detect_ht(struct cpuinfo_x86 *c);
203 #else
204 static always_inline void detect_ht(struct cpuinfo_x86 *c) {}
205 #endif
207 /*
208 * Generic CPUID function
209 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
210 * resulting in stale register contents being returned.
211 */
212 #define cpuid(_op,_eax,_ebx,_ecx,_edx) \
213 asm ( "cpuid" \
214 : "=a" (*(int *)(_eax)), \
215 "=b" (*(int *)(_ebx)), \
216 "=c" (*(int *)(_ecx)), \
217 "=d" (*(int *)(_edx)) \
218 : "0" (_op), "2" (0) )
220 /* Some CPUID calls want 'count' to be placed in ecx */
221 static inline void cpuid_count(
222 int op,
223 int count,
224 unsigned int *eax,
225 unsigned int *ebx,
226 unsigned int *ecx,
227 unsigned int *edx)
228 {
229 asm ( "cpuid"
230 : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
231 : "0" (op), "c" (count) );
232 }
234 /*
235 * CPUID functions returning a single datum
236 */
237 static always_inline unsigned int cpuid_eax(unsigned int op)
238 {
239 unsigned int eax;
241 asm ( "cpuid"
242 : "=a" (eax)
243 : "0" (op)
244 : "bx", "cx", "dx" );
245 return eax;
246 }
248 static always_inline unsigned int cpuid_ebx(unsigned int op)
249 {
250 unsigned int eax, ebx;
252 asm ( "cpuid"
253 : "=a" (eax), "=b" (ebx)
254 : "0" (op)
255 : "cx", "dx" );
256 return ebx;
257 }
259 static always_inline unsigned int cpuid_ecx(unsigned int op)
260 {
261 unsigned int eax, ecx;
263 asm ( "cpuid"
264 : "=a" (eax), "=c" (ecx)
265 : "0" (op)
266 : "bx", "dx" );
267 return ecx;
268 }
270 static always_inline unsigned int cpuid_edx(unsigned int op)
271 {
272 unsigned int eax, edx;
274 asm ( "cpuid"
275 : "=a" (eax), "=d" (edx)
276 : "0" (op)
277 : "bx", "cx" );
278 return edx;
279 }
281 static inline unsigned long read_cr0(void)
282 {
283 unsigned long cr0;
284 asm volatile ( "mov %%cr0,%0\n\t" : "=r" (cr0) );
285 return cr0;
286 }
288 static inline void write_cr0(unsigned long val)
289 {
290 asm volatile ( "mov %0,%%cr0" : : "r" ((unsigned long)val) );
291 }
293 static inline unsigned long read_cr2(void)
294 {
295 unsigned long cr2;
296 asm volatile ( "mov %%cr2,%0\n\t" : "=r" (cr2) );
297 return cr2;
298 }
300 DECLARE_PER_CPU(unsigned long, cr4);
302 static inline unsigned long read_cr4(void)
303 {
304 return this_cpu(cr4);
305 }
307 static inline void write_cr4(unsigned long val)
308 {
309 this_cpu(cr4) = val;
310 asm volatile ( "mov %0,%%cr4" : : "r" (val) );
311 }
313 /* Clear and set 'TS' bit respectively */
314 static inline void clts(void)
315 {
316 asm volatile ( "clts" );
317 }
319 static inline void stts(void)
320 {
321 write_cr0(X86_CR0_TS|read_cr0());
322 }
324 /*
325 * Save the cr4 feature set we're using (ie
326 * Pentium 4MB enable and PPro Global page
327 * enable), so that any CPU's that boot up
328 * after us can get the correct flags.
329 */
330 extern unsigned long mmu_cr4_features;
332 static always_inline void set_in_cr4 (unsigned long mask)
333 {
334 mmu_cr4_features |= mask;
335 write_cr4(read_cr4() | mask);
336 }
338 static always_inline void clear_in_cr4 (unsigned long mask)
339 {
340 mmu_cr4_features &= ~mask;
341 write_cr4(read_cr4() & ~mask);
342 }
344 /*
345 * NSC/Cyrix CPU configuration register indexes
346 */
348 #define CX86_PCR0 0x20
349 #define CX86_GCR 0xb8
350 #define CX86_CCR0 0xc0
351 #define CX86_CCR1 0xc1
352 #define CX86_CCR2 0xc2
353 #define CX86_CCR3 0xc3
354 #define CX86_CCR4 0xe8
355 #define CX86_CCR5 0xe9
356 #define CX86_CCR6 0xea
357 #define CX86_CCR7 0xeb
358 #define CX86_PCR1 0xf0
359 #define CX86_DIR0 0xfe
360 #define CX86_DIR1 0xff
361 #define CX86_ARR_BASE 0xc4
362 #define CX86_RCR_BASE 0xdc
364 /*
365 * NSC/Cyrix CPU indexed register access macros
366 */
368 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
370 #define setCx86(reg, data) do { \
371 outb((reg), 0x22); \
372 outb((data), 0x23); \
373 } while (0)
375 /* Stop speculative execution */
376 static inline void sync_core(void)
377 {
378 int tmp;
379 asm volatile (
380 "cpuid"
381 : "=a" (tmp)
382 : "0" (1)
383 : "ebx","ecx","edx","memory" );
384 }
386 static always_inline void __monitor(const void *eax, unsigned long ecx,
387 unsigned long edx)
388 {
389 /* "monitor %eax,%ecx,%edx;" */
390 asm volatile (
391 ".byte 0x0f,0x01,0xc8;"
392 : : "a" (eax), "c" (ecx), "d"(edx) );
393 }
395 static always_inline void __mwait(unsigned long eax, unsigned long ecx)
396 {
397 /* "mwait %eax,%ecx;" */
398 asm volatile (
399 ".byte 0x0f,0x01,0xc9;"
400 : : "a" (eax), "c" (ecx) );
401 }
403 #define IOBMP_BYTES 8192
404 #define IOBMP_INVALID_OFFSET 0x8000
406 struct tss_struct {
407 unsigned short back_link,__blh;
408 #ifdef __x86_64__
409 union { u64 rsp0, esp0; };
410 union { u64 rsp1, esp1; };
411 union { u64 rsp2, esp2; };
412 u64 reserved1;
413 u64 ist[7];
414 u64 reserved2;
415 u16 reserved3;
416 #else
417 u32 esp0;
418 u16 ss0,__ss0h;
419 u32 esp1;
420 u16 ss1,__ss1h;
421 u32 esp2;
422 u16 ss2,__ss2h;
423 u32 __cr3;
424 u32 eip;
425 u32 eflags;
426 u32 eax,ecx,edx,ebx;
427 u32 esp;
428 u32 ebp;
429 u32 esi;
430 u32 edi;
431 u16 es, __esh;
432 u16 cs, __csh;
433 u16 ss, __ssh;
434 u16 ds, __dsh;
435 u16 fs, __fsh;
436 u16 gs, __gsh;
437 u16 ldt, __ldth;
438 u16 trace;
439 #endif
440 u16 bitmap;
441 /* Pads the TSS to be cacheline-aligned (total size is 0x80). */
442 u8 __cacheline_filler[24];
443 } __cacheline_aligned __attribute__((packed));
445 #ifdef __x86_64__
446 # define IST_DF 1UL
447 # define IST_NMI 2UL
448 # define IST_MCE 3UL
449 # define IST_MAX 3UL
450 #endif
452 #define IDT_ENTRIES 256
453 extern idt_entry_t idt_table[];
454 extern idt_entry_t *idt_tables[];
456 extern struct tss_struct init_tss[NR_CPUS];
458 extern void init_int80_direct_trap(struct vcpu *v);
460 #if defined(CONFIG_X86_32)
462 #define set_int80_direct_trap(_ed) \
463 (memcpy(idt_tables[(_ed)->processor] + 0x80, \
464 &((_ed)->arch.int80_desc), 8))
466 #else
468 #define set_int80_direct_trap(_ed) ((void)0)
470 #endif
472 extern int gpf_emulate_4gb(struct cpu_user_regs *regs);
474 extern void write_ptbase(struct vcpu *v);
476 void destroy_gdt(struct vcpu *d);
477 long set_gdt(struct vcpu *d,
478 unsigned long *frames,
479 unsigned int entries);
481 #define write_debugreg(reg, val) do { \
482 unsigned long __val = val; \
483 asm volatile ( "mov %0,%%db" #reg : : "r" (__val) ); \
484 } while (0)
485 #define read_debugreg(reg) ({ \
486 unsigned long __val; \
487 asm volatile ( "mov %%db" #reg ",%0" : "=r" (__val) ); \
488 __val; \
489 })
490 long set_debugreg(struct vcpu *p, int reg, unsigned long value);
492 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
493 static always_inline void rep_nop(void)
494 {
495 asm volatile ( "rep;nop" : : : "memory" );
496 }
498 #define cpu_relax() rep_nop()
500 /* Prefetch instructions for Pentium III and AMD Athlon */
501 #ifdef CONFIG_MPENTIUMIII
503 #define ARCH_HAS_PREFETCH
504 extern always_inline void prefetch(const void *x)
505 {
506 asm volatile ( "prefetchnta (%0)" : : "r"(x) );
507 }
509 #elif CONFIG_X86_USE_3DNOW
511 #define ARCH_HAS_PREFETCH
512 #define ARCH_HAS_PREFETCHW
513 #define ARCH_HAS_SPINLOCK_PREFETCH
515 extern always_inline void prefetch(const void *x)
516 {
517 asm volatile ( "prefetch (%0)" : : "r"(x) );
518 }
520 extern always_inline void prefetchw(const void *x)
521 {
522 asm volatile ( "prefetchw (%0)" : : "r"(x) );
523 }
524 #define spin_lock_prefetch(x) prefetchw(x)
526 #endif
528 void show_stack(struct cpu_user_regs *regs);
529 void show_stack_overflow(unsigned int cpu, unsigned long esp);
530 void show_registers(struct cpu_user_regs *regs);
531 void show_execution_state(struct cpu_user_regs *regs);
532 void show_page_walk(unsigned long addr);
533 asmlinkage void fatal_trap(int trapnr, struct cpu_user_regs *regs);
535 #ifdef CONFIG_COMPAT
536 void compat_show_guest_stack(struct cpu_user_regs *, int lines);
537 #else
538 #define compat_show_guest_stack(regs, lines) ((void)0)
539 #endif
541 extern void mtrr_ap_init(void);
542 extern void mtrr_bp_init(void);
544 void mcheck_init(struct cpuinfo_x86 *c);
545 asmlinkage void do_machine_check(struct cpu_user_regs *regs);
546 void cpu_mcheck_distribute_cmci(void);
547 void cpu_mcheck_disable(void);
549 int cpuid_hypervisor_leaves(
550 uint32_t idx, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
551 int rdmsr_hypervisor_regs(
552 uint32_t idx, uint32_t *eax, uint32_t *edx);
553 int wrmsr_hypervisor_regs(
554 uint32_t idx, uint32_t eax, uint32_t edx);
556 int microcode_update(XEN_GUEST_HANDLE(const_void), unsigned long len);
557 int microcode_resume_cpu(int cpu);
559 #endif /* !__ASSEMBLY__ */
561 #endif /* __ASM_X86_PROCESSOR_H */
563 /*
564 * Local variables:
565 * mode: C
566 * c-set-style: "BSD"
567 * c-basic-offset: 4
568 * tab-width: 4
569 * indent-tabs-mode: nil
570 * End:
571 */