ia64/xen-unstable

view xen/include/public/arch-x86/hvm/save.h @ 19823:82bbce59b65d

save/restore : Save guest's preferred TSC frequency in image

For save/restore or live migration between two different frequency
platforms, guest's preferred TSC frequency is required to caculate
guest's TSC after resotre, so save it in the image header.

Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Jun 24 10:48:21 2009 +0100 (2009-06-24)
parents f0e2df69a8eb
children
line source
1 /*
2 * Structure definitions for HVM state that is held by Xen and must
3 * be saved along with the domain's memory and device-model state.
4 *
5 * Copyright (c) 2007 XenSource Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to
9 * deal in the Software without restriction, including without limitation the
10 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
11 * sell copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
26 #ifndef __XEN_PUBLIC_HVM_SAVE_X86_H__
27 #define __XEN_PUBLIC_HVM_SAVE_X86_H__
29 /*
30 * Save/restore header: general info about the save file.
31 */
33 #define HVM_FILE_MAGIC 0x54381286
34 #define HVM_FILE_VERSION 0x00000001
36 struct hvm_save_header {
37 uint32_t magic; /* Must be HVM_FILE_MAGIC */
38 uint32_t version; /* File format version */
39 uint64_t changeset; /* Version of Xen that saved this file */
40 uint32_t cpuid; /* CPUID[0x01][%eax] on the saving machine */
41 uint32_t gtsc_khz; /* Guest's TSC frequency in kHz */
42 };
44 DECLARE_HVM_SAVE_TYPE(HEADER, 1, struct hvm_save_header);
47 /*
48 * Processor
49 */
51 struct hvm_hw_cpu {
52 uint8_t fpu_regs[512];
54 uint64_t rax;
55 uint64_t rbx;
56 uint64_t rcx;
57 uint64_t rdx;
58 uint64_t rbp;
59 uint64_t rsi;
60 uint64_t rdi;
61 uint64_t rsp;
62 uint64_t r8;
63 uint64_t r9;
64 uint64_t r10;
65 uint64_t r11;
66 uint64_t r12;
67 uint64_t r13;
68 uint64_t r14;
69 uint64_t r15;
71 uint64_t rip;
72 uint64_t rflags;
74 uint64_t cr0;
75 uint64_t cr2;
76 uint64_t cr3;
77 uint64_t cr4;
79 uint64_t dr0;
80 uint64_t dr1;
81 uint64_t dr2;
82 uint64_t dr3;
83 uint64_t dr6;
84 uint64_t dr7;
86 uint32_t cs_sel;
87 uint32_t ds_sel;
88 uint32_t es_sel;
89 uint32_t fs_sel;
90 uint32_t gs_sel;
91 uint32_t ss_sel;
92 uint32_t tr_sel;
93 uint32_t ldtr_sel;
95 uint32_t cs_limit;
96 uint32_t ds_limit;
97 uint32_t es_limit;
98 uint32_t fs_limit;
99 uint32_t gs_limit;
100 uint32_t ss_limit;
101 uint32_t tr_limit;
102 uint32_t ldtr_limit;
103 uint32_t idtr_limit;
104 uint32_t gdtr_limit;
106 uint64_t cs_base;
107 uint64_t ds_base;
108 uint64_t es_base;
109 uint64_t fs_base;
110 uint64_t gs_base;
111 uint64_t ss_base;
112 uint64_t tr_base;
113 uint64_t ldtr_base;
114 uint64_t idtr_base;
115 uint64_t gdtr_base;
117 uint32_t cs_arbytes;
118 uint32_t ds_arbytes;
119 uint32_t es_arbytes;
120 uint32_t fs_arbytes;
121 uint32_t gs_arbytes;
122 uint32_t ss_arbytes;
123 uint32_t tr_arbytes;
124 uint32_t ldtr_arbytes;
126 uint64_t sysenter_cs;
127 uint64_t sysenter_esp;
128 uint64_t sysenter_eip;
130 /* msr for em64t */
131 uint64_t shadow_gs;
133 /* msr content saved/restored. */
134 uint64_t msr_flags;
135 uint64_t msr_lstar;
136 uint64_t msr_star;
137 uint64_t msr_cstar;
138 uint64_t msr_syscall_mask;
139 uint64_t msr_efer;
141 /* guest's idea of what rdtsc() would return */
142 uint64_t tsc;
144 /* pending event, if any */
145 union {
146 uint32_t pending_event;
147 struct {
148 uint8_t pending_vector:8;
149 uint8_t pending_type:3;
150 uint8_t pending_error_valid:1;
151 uint32_t pending_reserved:19;
152 uint8_t pending_valid:1;
153 };
154 };
155 /* error code for pending event */
156 uint32_t error_code;
157 };
159 DECLARE_HVM_SAVE_TYPE(CPU, 2, struct hvm_hw_cpu);
162 /*
163 * PIC
164 */
166 struct hvm_hw_vpic {
167 /* IR line bitmasks. */
168 uint8_t irr;
169 uint8_t imr;
170 uint8_t isr;
172 /* Line IRx maps to IRQ irq_base+x */
173 uint8_t irq_base;
175 /*
176 * Where are we in ICW2-4 initialisation (0 means no init in progress)?
177 * Bits 0-1 (=x): Next write at A=1 sets ICW(x+1).
178 * Bit 2: ICW1.IC4 (1 == ICW4 included in init sequence)
179 * Bit 3: ICW1.SNGL (0 == ICW3 included in init sequence)
180 */
181 uint8_t init_state:4;
183 /* IR line with highest priority. */
184 uint8_t priority_add:4;
186 /* Reads from A=0 obtain ISR or IRR? */
187 uint8_t readsel_isr:1;
189 /* Reads perform a polling read? */
190 uint8_t poll:1;
192 /* Automatically clear IRQs from the ISR during INTA? */
193 uint8_t auto_eoi:1;
195 /* Automatically rotate IRQ priorities during AEOI? */
196 uint8_t rotate_on_auto_eoi:1;
198 /* Exclude slave inputs when considering in-service IRQs? */
199 uint8_t special_fully_nested_mode:1;
201 /* Special mask mode excludes masked IRs from AEOI and priority checks. */
202 uint8_t special_mask_mode:1;
204 /* Is this a master PIC or slave PIC? (NB. This is not programmable.) */
205 uint8_t is_master:1;
207 /* Edge/trigger selection. */
208 uint8_t elcr;
210 /* Virtual INT output. */
211 uint8_t int_output;
212 };
214 DECLARE_HVM_SAVE_TYPE(PIC, 3, struct hvm_hw_vpic);
217 /*
218 * IO-APIC
219 */
221 #ifdef __ia64__
222 #define VIOAPIC_IS_IOSAPIC 1
223 #define VIOAPIC_NUM_PINS 24
224 #else
225 #define VIOAPIC_NUM_PINS 48 /* 16 ISA IRQs, 32 non-legacy PCI IRQS. */
226 #endif
228 struct hvm_hw_vioapic {
229 uint64_t base_address;
230 uint32_t ioregsel;
231 uint32_t id;
232 union vioapic_redir_entry
233 {
234 uint64_t bits;
235 struct {
236 uint8_t vector;
237 uint8_t delivery_mode:3;
238 uint8_t dest_mode:1;
239 uint8_t delivery_status:1;
240 uint8_t polarity:1;
241 uint8_t remote_irr:1;
242 uint8_t trig_mode:1;
243 uint8_t mask:1;
244 uint8_t reserve:7;
245 #if !VIOAPIC_IS_IOSAPIC
246 uint8_t reserved[4];
247 uint8_t dest_id;
248 #else
249 uint8_t reserved[3];
250 uint16_t dest_id;
251 #endif
252 } fields;
253 } redirtbl[VIOAPIC_NUM_PINS];
254 };
256 DECLARE_HVM_SAVE_TYPE(IOAPIC, 4, struct hvm_hw_vioapic);
259 /*
260 * LAPIC
261 */
263 struct hvm_hw_lapic {
264 uint64_t apic_base_msr;
265 uint32_t disabled; /* VLAPIC_xx_DISABLED */
266 uint32_t timer_divisor;
267 };
269 DECLARE_HVM_SAVE_TYPE(LAPIC, 5, struct hvm_hw_lapic);
271 struct hvm_hw_lapic_regs {
272 uint8_t data[1024];
273 };
275 DECLARE_HVM_SAVE_TYPE(LAPIC_REGS, 6, struct hvm_hw_lapic_regs);
278 /*
279 * IRQs
280 */
282 struct hvm_hw_pci_irqs {
283 /*
284 * Virtual interrupt wires for a single PCI bus.
285 * Indexed by: device*4 + INTx#.
286 */
287 union {
288 unsigned long i[16 / sizeof (unsigned long)]; /* DECLARE_BITMAP(i, 32*4); */
289 uint64_t pad[2];
290 };
291 };
293 DECLARE_HVM_SAVE_TYPE(PCI_IRQ, 7, struct hvm_hw_pci_irqs);
295 struct hvm_hw_isa_irqs {
296 /*
297 * Virtual interrupt wires for ISA devices.
298 * Indexed by ISA IRQ (assumes no ISA-device IRQ sharing).
299 */
300 union {
301 unsigned long i[1]; /* DECLARE_BITMAP(i, 16); */
302 uint64_t pad[1];
303 };
304 };
306 DECLARE_HVM_SAVE_TYPE(ISA_IRQ, 8, struct hvm_hw_isa_irqs);
308 struct hvm_hw_pci_link {
309 /*
310 * PCI-ISA interrupt router.
311 * Each PCI <device:INTx#> is 'wire-ORed' into one of four links using
312 * the traditional 'barber's pole' mapping ((device + INTx#) & 3).
313 * The router provides a programmable mapping from each link to a GSI.
314 */
315 uint8_t route[4];
316 uint8_t pad0[4];
317 };
319 DECLARE_HVM_SAVE_TYPE(PCI_LINK, 9, struct hvm_hw_pci_link);
321 /*
322 * PIT
323 */
325 struct hvm_hw_pit {
326 struct hvm_hw_pit_channel {
327 uint32_t count; /* can be 65536 */
328 uint16_t latched_count;
329 uint8_t count_latched;
330 uint8_t status_latched;
331 uint8_t status;
332 uint8_t read_state;
333 uint8_t write_state;
334 uint8_t write_latch;
335 uint8_t rw_mode;
336 uint8_t mode;
337 uint8_t bcd; /* not supported */
338 uint8_t gate; /* timer start */
339 } channels[3]; /* 3 x 16 bytes */
340 uint32_t speaker_data_on;
341 uint32_t pad0;
342 };
344 DECLARE_HVM_SAVE_TYPE(PIT, 10, struct hvm_hw_pit);
347 /*
348 * RTC
349 */
351 #define RTC_CMOS_SIZE 14
352 struct hvm_hw_rtc {
353 /* CMOS bytes */
354 uint8_t cmos_data[RTC_CMOS_SIZE];
355 /* Index register for 2-part operations */
356 uint8_t cmos_index;
357 uint8_t pad0;
358 };
360 DECLARE_HVM_SAVE_TYPE(RTC, 11, struct hvm_hw_rtc);
363 /*
364 * HPET
365 */
367 #define HPET_TIMER_NUM 3 /* 3 timers supported now */
368 struct hvm_hw_hpet {
369 /* Memory-mapped, software visible registers */
370 uint64_t capability; /* capabilities */
371 uint64_t res0; /* reserved */
372 uint64_t config; /* configuration */
373 uint64_t res1; /* reserved */
374 uint64_t isr; /* interrupt status reg */
375 uint64_t res2[25]; /* reserved */
376 uint64_t mc64; /* main counter */
377 uint64_t res3; /* reserved */
378 struct { /* timers */
379 uint64_t config; /* configuration/cap */
380 uint64_t cmp; /* comparator */
381 uint64_t fsb; /* FSB route, not supported now */
382 uint64_t res4; /* reserved */
383 } timers[HPET_TIMER_NUM];
384 uint64_t res5[4*(24-HPET_TIMER_NUM)]; /* reserved, up to 0x3ff */
386 /* Hidden register state */
387 uint64_t period[HPET_TIMER_NUM]; /* Last value written to comparator */
388 };
390 DECLARE_HVM_SAVE_TYPE(HPET, 12, struct hvm_hw_hpet);
393 /*
394 * PM timer
395 */
397 struct hvm_hw_pmtimer {
398 uint32_t tmr_val; /* PM_TMR_BLK.TMR_VAL: 32bit free-running counter */
399 uint16_t pm1a_sts; /* PM1a_EVT_BLK.PM1a_STS: status register */
400 uint16_t pm1a_en; /* PM1a_EVT_BLK.PM1a_EN: enable register */
401 };
403 DECLARE_HVM_SAVE_TYPE(PMTIMER, 13, struct hvm_hw_pmtimer);
405 /*
406 * MTRR MSRs
407 */
409 struct hvm_hw_mtrr {
410 #define MTRR_VCNT 8
411 #define NUM_FIXED_MSR 11
412 uint64_t msr_pat_cr;
413 /* mtrr physbase & physmask msr pair*/
414 uint64_t msr_mtrr_var[MTRR_VCNT*2];
415 uint64_t msr_mtrr_fixed[NUM_FIXED_MSR];
416 uint64_t msr_mtrr_cap;
417 uint64_t msr_mtrr_def_type;
418 };
420 DECLARE_HVM_SAVE_TYPE(MTRR, 14, struct hvm_hw_mtrr);
422 /*
423 * Viridian hypervisor context.
424 */
426 struct hvm_viridian_context {
427 uint64_t hypercall_gpa;
428 uint64_t guest_os_id;
429 };
431 DECLARE_HVM_SAVE_TYPE(VIRIDIAN, 15, struct hvm_viridian_context);
433 /*
434 * Largest type-code in use
435 */
436 #define HVM_SAVE_CODE_MAX 15
438 #endif /* __XEN_PUBLIC_HVM_SAVE_X86_H__ */