ia64/xen-unstable

view xen/include/asm-ia64/linux-xen/asm/mca_asm.h @ 10673:80e04aa530b8

[IA64] Fix LOAD_PHYSCAL macro

This fix is workaround. Now LOAD_PHYSCAL is used only
by MCA/INIT handler.

Signed-off-by: Akio Takebe <takebe_akio@jp.fujitsu.com>
author awilliam@xenbuild.aw
date Thu Jul 06 10:04:57 2006 -0600 (2006-07-06)
parents 59b142b0884e
children efb346a02e70
line source
1 /*
2 * File: mca_asm.h
3 *
4 * Copyright (C) 1999 Silicon Graphics, Inc.
5 * Copyright (C) Vijay Chander (vijay@engr.sgi.com)
6 * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
7 * Copyright (C) 2000 Hewlett-Packard Co.
8 * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 2002 Intel Corp.
10 * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
11 */
12 #ifndef _ASM_IA64_MCA_ASM_H
13 #define _ASM_IA64_MCA_ASM_H
15 #define PSR_IC 13
16 #define PSR_I 14
17 #define PSR_DT 17
18 #define PSR_RT 27
19 #define PSR_MC 35
20 #define PSR_IT 36
21 #define PSR_BN 44
23 /*
24 * This macro converts a instruction virtual address to a physical address
25 * Right now for simulation purposes the virtual addresses are
26 * direct mapped to physical addresses.
27 * 1. Lop off bits 61 thru 63 in the virtual address
28 */
29 #ifdef XEN
30 #define INST_VA_TO_PA(addr) \
31 dep addr = 0, addr, 60, 4
32 #else
33 #define INST_VA_TO_PA(addr) \
34 dep addr = 0, addr, 61, 3
35 #endif
36 /*
37 * This macro converts a data virtual address to a physical address
38 * Right now for simulation purposes the virtual addresses are
39 * direct mapped to physical addresses.
40 * 1. Lop off bits 61 thru 63 in the virtual address
41 */
42 #define DATA_VA_TO_PA(addr) \
43 tpa addr = addr
44 /*
45 * This macro converts a data physical address to a virtual address
46 * Right now for simulation purposes the virtual addresses are
47 * direct mapped to physical addresses.
48 * 1. Put 0x7 in bits 61 thru 63.
49 */
50 #ifdef XEN
51 #define DATA_PA_TO_VA(addr,temp) \
52 mov temp = 0xf ;; \
53 dep addr = temp, addr, 60, 4
54 #else
55 #define DATA_PA_TO_VA(addr,temp) \
56 mov temp = 0x7 ;; \
57 dep addr = temp, addr, 61, 3
58 #endif
60 #ifdef XEN
61 #define GET_THIS_PADDR(reg, var) \
62 movl reg = THIS_CPU(var) \
63 tpa reg = reg
64 #else
65 #define GET_THIS_PADDR(reg, var) \
66 mov reg = IA64_KR(PER_CPU_DATA);; \
67 addl reg = THIS_CPU(var), reg
68 #endif
70 /*
71 * This macro jumps to the instruction at the given virtual address
72 * and starts execution in physical mode with all the address
73 * translations turned off.
74 * 1. Save the current psr
75 * 2. Make sure that all the upper 32 bits are off
76 *
77 * 3. Clear the interrupt enable and interrupt state collection bits
78 * in the psr before updating the ipsr and iip.
79 *
80 * 4. Turn off the instruction, data and rse translation bits of the psr
81 * and store the new value into ipsr
82 * Also make sure that the interrupts are disabled.
83 * Ensure that we are in little endian mode.
84 * [psr.{rt, it, dt, i, be} = 0]
85 *
86 * 5. Get the physical address corresponding to the virtual address
87 * of the next instruction bundle and put it in iip.
88 * (Using magic numbers 24 and 40 in the deposint instruction since
89 * the IA64_SDK code directly maps to lower 24bits as physical address
90 * from a virtual address).
91 *
92 * 6. Do an rfi to move the values from ipsr to psr and iip to ip.
93 */
94 #define PHYSICAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
95 mov old_psr = psr; \
96 ;; \
97 dep old_psr = 0, old_psr, 32, 32; \
98 \
99 mov ar.rsc = 0 ; \
100 ;; \
101 srlz.d; \
102 mov temp2 = ar.bspstore; \
103 ;; \
104 DATA_VA_TO_PA(temp2); \
105 ;; \
106 mov temp1 = ar.rnat; \
107 ;; \
108 mov ar.bspstore = temp2; \
109 ;; \
110 mov ar.rnat = temp1; \
111 mov temp1 = psr; \
112 mov temp2 = psr; \
113 ;; \
114 \
115 dep temp2 = 0, temp2, PSR_IC, 2; \
116 ;; \
117 mov psr.l = temp2; \
118 ;; \
119 srlz.d; \
120 dep temp1 = 0, temp1, 32, 32; \
121 ;; \
122 dep temp1 = 0, temp1, PSR_IT, 1; \
123 ;; \
124 dep temp1 = 0, temp1, PSR_DT, 1; \
125 ;; \
126 dep temp1 = 0, temp1, PSR_RT, 1; \
127 ;; \
128 dep temp1 = 0, temp1, PSR_I, 1; \
129 ;; \
130 dep temp1 = 0, temp1, PSR_IC, 1; \
131 ;; \
132 dep temp1 = -1, temp1, PSR_MC, 1; \
133 ;; \
134 mov cr.ipsr = temp1; \
135 ;; \
136 LOAD_PHYSICAL(p0, temp2, start_addr); \
137 ;; \
138 mov cr.iip = temp2; \
139 mov cr.ifs = r0; \
140 DATA_VA_TO_PA(sp); \
141 DATA_VA_TO_PA(gp); \
142 ;; \
143 srlz.i; \
144 ;; \
145 nop 1; \
146 nop 2; \
147 nop 1; \
148 nop 2; \
149 rfi; \
150 ;;
152 /*
153 * This macro jumps to the instruction at the given virtual address
154 * and starts execution in virtual mode with all the address
155 * translations turned on.
156 * 1. Get the old saved psr
157 *
158 * 2. Clear the interrupt state collection bit in the current psr.
159 *
160 * 3. Set the instruction translation bit back in the old psr
161 * Note we have to do this since we are right now saving only the
162 * lower 32-bits of old psr.(Also the old psr has the data and
163 * rse translation bits on)
164 *
165 * 4. Set ipsr to this old_psr with "it" bit set and "bn" = 1.
166 *
167 * 5. Reset the current thread pointer (r13).
168 *
169 * 6. Set iip to the virtual address of the next instruction bundle.
170 *
171 * 7. Do an rfi to move ipsr to psr and iip to ip.
172 */
174 #define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr) \
175 mov temp2 = psr; \
176 ;; \
177 mov old_psr = temp2; \
178 ;; \
179 dep temp2 = 0, temp2, PSR_IC, 2; \
180 ;; \
181 mov psr.l = temp2; \
182 mov ar.rsc = 0; \
183 ;; \
184 srlz.d; \
185 mov r13 = ar.k6; \
186 mov temp2 = ar.bspstore; \
187 ;; \
188 DATA_PA_TO_VA(temp2,temp1); \
189 ;; \
190 mov temp1 = ar.rnat; \
191 ;; \
192 mov ar.bspstore = temp2; \
193 ;; \
194 mov ar.rnat = temp1; \
195 ;; \
196 mov temp1 = old_psr; \
197 ;; \
198 mov temp2 = 1; \
199 ;; \
200 dep temp1 = temp2, temp1, PSR_IC, 1; \
201 ;; \
202 dep temp1 = temp2, temp1, PSR_IT, 1; \
203 ;; \
204 dep temp1 = temp2, temp1, PSR_DT, 1; \
205 ;; \
206 dep temp1 = temp2, temp1, PSR_RT, 1; \
207 ;; \
208 dep temp1 = temp2, temp1, PSR_BN, 1; \
209 ;; \
210 \
211 mov cr.ipsr = temp1; \
212 movl temp2 = start_addr; \
213 ;; \
214 mov cr.iip = temp2; \
215 ;; \
216 DATA_PA_TO_VA(sp, temp1); \
217 DATA_PA_TO_VA(gp, temp2); \
218 srlz.i; \
219 ;; \
220 nop 1; \
221 nop 2; \
222 nop 1; \
223 rfi \
224 ;;
226 /*
227 * The following offsets capture the order in which the
228 * RSE related registers from the old context are
229 * saved onto the new stack frame.
230 *
231 * +-----------------------+
232 * |NDIRTY [BSP - BSPSTORE]|
233 * +-----------------------+
234 * | RNAT |
235 * +-----------------------+
236 * | BSPSTORE |
237 * +-----------------------+
238 * | IFS |
239 * +-----------------------+
240 * | PFS |
241 * +-----------------------+
242 * | RSC |
243 * +-----------------------+ <-------- Bottom of new stack frame
244 */
245 #define rse_rsc_offset 0
246 #define rse_pfs_offset (rse_rsc_offset+0x08)
247 #define rse_ifs_offset (rse_pfs_offset+0x08)
248 #define rse_bspstore_offset (rse_ifs_offset+0x08)
249 #define rse_rnat_offset (rse_bspstore_offset+0x08)
250 #define rse_ndirty_offset (rse_rnat_offset+0x08)
252 /*
253 * rse_switch_context
254 *
255 * 1. Save old RSC onto the new stack frame
256 * 2. Save PFS onto new stack frame
257 * 3. Cover the old frame and start a new frame.
258 * 4. Save IFS onto new stack frame
259 * 5. Save the old BSPSTORE on the new stack frame
260 * 6. Save the old RNAT on the new stack frame
261 * 7. Write BSPSTORE with the new backing store pointer
262 * 8. Read and save the new BSP to calculate the #dirty registers
263 * NOTE: Look at pages 11-10, 11-11 in PRM Vol 2
264 */
265 #define rse_switch_context(temp,p_stackframe,p_bspstore) \
266 ;; \
267 mov temp=ar.rsc;; \
268 st8 [p_stackframe]=temp,8;; \
269 mov temp=ar.pfs;; \
270 st8 [p_stackframe]=temp,8; \
271 cover ;; \
272 mov temp=cr.ifs;; \
273 st8 [p_stackframe]=temp,8;; \
274 mov temp=ar.bspstore;; \
275 st8 [p_stackframe]=temp,8;; \
276 mov temp=ar.rnat;; \
277 st8 [p_stackframe]=temp,8; \
278 mov ar.bspstore=p_bspstore;; \
279 mov temp=ar.bsp;; \
280 sub temp=temp,p_bspstore;; \
281 st8 [p_stackframe]=temp,8;;
283 /*
284 * rse_return_context
285 * 1. Allocate a zero-sized frame
286 * 2. Store the number of dirty registers RSC.loadrs field
287 * 3. Issue a loadrs to insure that any registers from the interrupted
288 * context which were saved on the new stack frame have been loaded
289 * back into the stacked registers
290 * 4. Restore BSPSTORE
291 * 5. Restore RNAT
292 * 6. Restore PFS
293 * 7. Restore IFS
294 * 8. Restore RSC
295 * 9. Issue an RFI
296 */
297 #define rse_return_context(psr_mask_reg,temp,p_stackframe) \
298 ;; \
299 alloc temp=ar.pfs,0,0,0,0; \
300 add p_stackframe=rse_ndirty_offset,p_stackframe;; \
301 ld8 temp=[p_stackframe];; \
302 shl temp=temp,16;; \
303 mov ar.rsc=temp;; \
304 loadrs;; \
305 add p_stackframe=-rse_ndirty_offset+rse_bspstore_offset,p_stackframe;;\
306 ld8 temp=[p_stackframe];; \
307 mov ar.bspstore=temp;; \
308 add p_stackframe=-rse_bspstore_offset+rse_rnat_offset,p_stackframe;;\
309 ld8 temp=[p_stackframe];; \
310 mov ar.rnat=temp;; \
311 add p_stackframe=-rse_rnat_offset+rse_pfs_offset,p_stackframe;; \
312 ld8 temp=[p_stackframe];; \
313 mov ar.pfs=temp;; \
314 add p_stackframe=-rse_pfs_offset+rse_ifs_offset,p_stackframe;; \
315 ld8 temp=[p_stackframe];; \
316 mov cr.ifs=temp;; \
317 add p_stackframe=-rse_ifs_offset+rse_rsc_offset,p_stackframe;; \
318 ld8 temp=[p_stackframe];; \
319 mov ar.rsc=temp ; \
320 mov temp=psr;; \
321 or temp=temp,psr_mask_reg;; \
322 mov cr.ipsr=temp;; \
323 mov temp=ip;; \
324 add temp=0x30,temp;; \
325 mov cr.iip=temp;; \
326 srlz.i;; \
327 rfi;;
329 #endif /* _ASM_IA64_MCA_ASM_H */