ia64/xen-unstable

view linux-2.6-xen-sparse/arch/ia64/kernel/setup.c @ 8946:8005fbd31d8b

Update ia64 sparse tree to Linux 2.6.16-rc4.

Signed-off-by: Alex Williamson <alex.williamson@hp.com>
author cl349@firebug.cl.cam.ac.uk
date Tue Feb 21 16:25:56 2006 +0000 (2006-02-21)
parents 776ab80f5a6c
children 6c43118bdba8
line source
1 /*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 *
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
24 */
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
29 #include <linux/acpi.h>
30 #include <linux/bootmem.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
33 #include <linux/kernel.h>
34 #include <linux/reboot.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/string.h>
38 #include <linux/threads.h>
39 #include <linux/tty.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
44 #include <linux/platform.h>
45 #include <linux/pm.h>
46 #include <linux/cpufreq.h>
48 #include <asm/ia32.h>
49 #include <asm/machvec.h>
50 #include <asm/mca.h>
51 #include <asm/meminit.h>
52 #include <asm/page.h>
53 #include <asm/patch.h>
54 #include <asm/pgtable.h>
55 #include <asm/processor.h>
56 #include <asm/sal.h>
57 #include <asm/sections.h>
58 #include <asm/serial.h>
59 #include <asm/setup.h>
60 #include <asm/smp.h>
61 #include <asm/system.h>
62 #include <asm/unistd.h>
63 #include <asm/system.h>
65 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
66 # error "struct cpuinfo_ia64 too big!"
67 #endif
69 #ifdef CONFIG_SMP
70 unsigned long __per_cpu_offset[NR_CPUS];
71 EXPORT_SYMBOL(__per_cpu_offset);
72 #endif
74 extern void ia64_setup_printk_clock(void);
76 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
77 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
78 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
79 unsigned long ia64_cycles_per_usec;
80 struct ia64_boot_param *ia64_boot_param;
81 struct screen_info screen_info;
82 unsigned long vga_console_iobase;
83 unsigned long vga_console_membase;
85 static struct resource data_resource = {
86 .name = "Kernel data",
87 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
88 };
90 static struct resource code_resource = {
91 .name = "Kernel code",
92 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
93 };
94 extern void efi_initialize_iomem_resources(struct resource *,
95 struct resource *);
96 extern char _text[], _end[], _etext[];
98 unsigned long ia64_max_cacheline_size;
100 int dma_get_cache_alignment(void)
101 {
102 return ia64_max_cacheline_size;
103 }
104 EXPORT_SYMBOL(dma_get_cache_alignment);
106 unsigned long ia64_iobase; /* virtual address for I/O accesses */
107 EXPORT_SYMBOL(ia64_iobase);
108 struct io_space io_space[MAX_IO_SPACES];
109 EXPORT_SYMBOL(io_space);
110 unsigned int num_io_spaces;
112 /*
113 * "flush_icache_range()" needs to know what processor dependent stride size to use
114 * when it makes i-cache(s) coherent with d-caches.
115 */
116 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
117 unsigned long ia64_i_cache_stride_shift = ~0;
119 /*
120 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
121 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
122 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
123 * address of the second buffer must be aligned to (merge_mask+1) in order to be
124 * mergeable). By default, we assume there is no I/O MMU which can merge physically
125 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
126 * page-size of 2^64.
127 */
128 unsigned long ia64_max_iommu_merge_mask = ~0UL;
129 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
131 /*
132 * We use a special marker for the end of memory and it uses the extra (+1) slot
133 */
134 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
135 int num_rsvd_regions;
138 /*
139 * Filter incoming memory segments based on the primitive map created from the boot
140 * parameters. Segments contained in the map are removed from the memory ranges. A
141 * caller-specified function is called with the memory ranges that remain after filtering.
142 * This routine does not assume the incoming segments are sorted.
143 */
144 int
145 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
146 {
147 unsigned long range_start, range_end, prev_start;
148 void (*func)(unsigned long, unsigned long, int);
149 int i;
151 #if IGNORE_PFN0
152 if (start == PAGE_OFFSET) {
153 printk(KERN_WARNING "warning: skipping physical page 0\n");
154 start += PAGE_SIZE;
155 if (start >= end) return 0;
156 }
157 #endif
158 /*
159 * lowest possible address(walker uses virtual)
160 */
161 prev_start = PAGE_OFFSET;
162 func = arg;
164 for (i = 0; i < num_rsvd_regions; ++i) {
165 range_start = max(start, prev_start);
166 range_end = min(end, rsvd_region[i].start);
168 if (range_start < range_end)
169 call_pernode_memory(__pa(range_start), range_end - range_start, func);
171 /* nothing more available in this segment */
172 if (range_end == end) return 0;
174 prev_start = rsvd_region[i].end;
175 }
176 /* end of memory marker allows full processing inside loop body */
177 return 0;
178 }
180 static void
181 sort_regions (struct rsvd_region *rsvd_region, int max)
182 {
183 int j;
185 /* simple bubble sorting */
186 while (max--) {
187 for (j = 0; j < max; ++j) {
188 if (rsvd_region[j].start > rsvd_region[j+1].start) {
189 struct rsvd_region tmp;
190 tmp = rsvd_region[j];
191 rsvd_region[j] = rsvd_region[j + 1];
192 rsvd_region[j + 1] = tmp;
193 }
194 }
195 }
196 }
198 /*
199 * Request address space for all standard resources
200 */
201 static int __init register_memory(void)
202 {
203 code_resource.start = ia64_tpa(_text);
204 code_resource.end = ia64_tpa(_etext) - 1;
205 data_resource.start = ia64_tpa(_etext);
206 data_resource.end = ia64_tpa(_end) - 1;
207 efi_initialize_iomem_resources(&code_resource, &data_resource);
209 return 0;
210 }
212 __initcall(register_memory);
214 /**
215 * reserve_memory - setup reserved memory areas
216 *
217 * Setup the reserved memory areas set aside for the boot parameters,
218 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
219 * see include/asm-ia64/meminit.h if you need to define more.
220 */
221 void
222 reserve_memory (void)
223 {
224 int n = 0;
226 /*
227 * none of the entries in this table overlap
228 */
229 rsvd_region[n].start = (unsigned long) ia64_boot_param;
230 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
231 n++;
233 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
234 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
235 n++;
237 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
238 rsvd_region[n].end = (rsvd_region[n].start
239 + strlen(__va(ia64_boot_param->command_line)) + 1);
240 n++;
242 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
243 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
244 n++;
246 #ifdef CONFIG_BLK_DEV_INITRD
247 if (ia64_boot_param->initrd_start) {
248 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
249 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
250 n++;
251 }
252 #endif
254 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
255 n++;
257 /* end of memory marker */
258 rsvd_region[n].start = ~0UL;
259 rsvd_region[n].end = ~0UL;
260 n++;
262 num_rsvd_regions = n;
264 sort_regions(rsvd_region, num_rsvd_regions);
265 }
267 /**
268 * find_initrd - get initrd parameters from the boot parameter structure
269 *
270 * Grab the initrd start and end from the boot parameter struct given us by
271 * the boot loader.
272 */
273 void
274 find_initrd (void)
275 {
276 #ifdef CONFIG_BLK_DEV_INITRD
277 if (ia64_boot_param->initrd_start) {
278 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
279 initrd_end = initrd_start+ia64_boot_param->initrd_size;
281 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
282 initrd_start, ia64_boot_param->initrd_size);
283 }
284 #endif
285 }
287 static void __init
288 io_port_init (void)
289 {
290 unsigned long phys_iobase;
292 /*
293 * Set `iobase' based on the EFI memory map or, failing that, the
294 * value firmware left in ar.k0.
295 *
296 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
297 * the port's virtual address, so ia32_load_state() loads it with a
298 * user virtual address. But in ia64 mode, glibc uses the
299 * *physical* address in ar.k0 to mmap the appropriate area from
300 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
301 * cases, user-mode can only use the legacy 0-64K I/O port space.
302 *
303 * ar.k0 is not involved in kernel I/O port accesses, which can use
304 * any of the I/O port spaces and are done via MMIO using the
305 * virtual mmio_base from the appropriate io_space[].
306 */
307 phys_iobase = efi_get_iobase();
308 if (!phys_iobase) {
309 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
310 printk(KERN_INFO "No I/O port range found in EFI memory map, "
311 "falling back to AR.KR0 (0x%lx)\n", phys_iobase);
312 }
313 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
314 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
316 /* setup legacy IO port space */
317 io_space[0].mmio_base = ia64_iobase;
318 io_space[0].sparse = 1;
319 num_io_spaces = 1;
320 }
322 /**
323 * early_console_setup - setup debugging console
324 *
325 * Consoles started here require little enough setup that we can start using
326 * them very early in the boot process, either right after the machine
327 * vector initialization, or even before if the drivers can detect their hw.
328 *
329 * Returns non-zero if a console couldn't be setup.
330 */
331 static inline int __init
332 early_console_setup (char *cmdline)
333 {
334 int earlycons = 0;
336 #ifdef CONFIG_XEN
337 if (!early_xen_console_setup(cmdline))
338 earlycons++;
339 #endif
340 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
341 {
342 extern int sn_serial_console_early_setup(void);
343 if (!sn_serial_console_early_setup())
344 earlycons++;
345 }
346 #endif
347 #ifdef CONFIG_EFI_PCDP
348 if (!efi_setup_pcdp_console(cmdline))
349 earlycons++;
350 #endif
351 #ifdef CONFIG_SERIAL_8250_CONSOLE
352 if (!early_serial_console_init(cmdline))
353 earlycons++;
354 #endif
356 return (earlycons) ? 0 : -1;
357 }
359 static inline void
360 mark_bsp_online (void)
361 {
362 #ifdef CONFIG_SMP
363 /* If we register an early console, allow CPU 0 to printk */
364 cpu_set(smp_processor_id(), cpu_online_map);
365 #endif
366 }
368 #ifdef CONFIG_SMP
369 static void
370 check_for_logical_procs (void)
371 {
372 pal_logical_to_physical_t info;
373 s64 status;
375 status = ia64_pal_logical_to_phys(0, &info);
376 if (status == -1) {
377 printk(KERN_INFO "No logical to physical processor mapping "
378 "available\n");
379 return;
380 }
381 if (status) {
382 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
383 status);
384 return;
385 }
386 /*
387 * Total number of siblings that BSP has. Though not all of them
388 * may have booted successfully. The correct number of siblings
389 * booted is in info.overview_num_log.
390 */
391 smp_num_siblings = info.overview_tpc;
392 smp_num_cpucores = info.overview_cpp;
393 }
394 #endif
396 void __init
397 setup_arch (char **cmdline_p)
398 {
399 unw_init();
401 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
403 *cmdline_p = __va(ia64_boot_param->command_line);
404 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
406 efi_init();
407 io_port_init();
409 #ifdef CONFIG_IA64_GENERIC
410 {
411 const char *mvec_name = strstr (*cmdline_p, "machvec=");
412 char str[64];
414 if (mvec_name) {
415 const char *end;
416 size_t len;
418 mvec_name += 8;
419 end = strchr (mvec_name, ' ');
420 if (end)
421 len = end - mvec_name;
422 else
423 len = strlen (mvec_name);
424 len = min(len, sizeof (str) - 1);
425 strncpy (str, mvec_name, len);
426 str[len] = '\0';
427 mvec_name = str;
428 } else
429 mvec_name = acpi_get_sysname();
430 machvec_init(mvec_name);
431 }
432 #endif
434 if (early_console_setup(*cmdline_p) == 0)
435 mark_bsp_online();
437 parse_early_param();
438 #ifdef CONFIG_ACPI
439 /* Initialize the ACPI boot-time table parser */
440 acpi_table_init();
441 # ifdef CONFIG_ACPI_NUMA
442 acpi_numa_init();
443 # endif
444 #else
445 # ifdef CONFIG_SMP
446 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
447 # endif
448 #endif /* CONFIG_APCI_BOOT */
450 find_memory();
452 /* process SAL system table: */
453 ia64_sal_init(efi.sal_systab);
455 ia64_setup_printk_clock();
457 #ifdef CONFIG_SMP
458 cpu_physical_id(0) = hard_smp_processor_id();
460 cpu_set(0, cpu_sibling_map[0]);
461 cpu_set(0, cpu_core_map[0]);
463 check_for_logical_procs();
464 if (smp_num_cpucores > 1)
465 printk(KERN_INFO
466 "cpu package is Multi-Core capable: number of cores=%d\n",
467 smp_num_cpucores);
468 if (smp_num_siblings > 1)
469 printk(KERN_INFO
470 "cpu package is Multi-Threading capable: number of siblings=%d\n",
471 smp_num_siblings);
472 #endif
474 cpu_init(); /* initialize the bootstrap CPU */
475 mmu_context_init(); /* initialize context_id bitmap */
477 #ifdef CONFIG_ACPI
478 acpi_boot_init();
479 #endif
481 #ifdef CONFIG_VT
482 if (!conswitchp) {
483 # if defined(CONFIG_DUMMY_CONSOLE)
484 conswitchp = &dummy_con;
485 # endif
486 # if defined(CONFIG_VGA_CONSOLE)
487 /*
488 * Non-legacy systems may route legacy VGA MMIO range to system
489 * memory. vga_con probes the MMIO hole, so memory looks like
490 * a VGA device to it. The EFI memory map can tell us if it's
491 * memory so we can avoid this problem.
492 */
493 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
494 conswitchp = &vga_con;
495 # endif
496 }
497 #endif
499 /* enable IA-64 Machine Check Abort Handling unless disabled */
500 if (!strstr(saved_command_line, "nomca"))
501 ia64_mca_init();
503 platform_setup(cmdline_p);
504 paging_init();
505 }
507 /*
508 * Display cpu info for all cpu's.
509 */
510 static int
511 show_cpuinfo (struct seq_file *m, void *v)
512 {
513 #ifdef CONFIG_SMP
514 # define lpj c->loops_per_jiffy
515 # define cpunum c->cpu
516 #else
517 # define lpj loops_per_jiffy
518 # define cpunum 0
519 #endif
520 static struct {
521 unsigned long mask;
522 const char *feature_name;
523 } feature_bits[] = {
524 { 1UL << 0, "branchlong" },
525 { 1UL << 1, "spontaneous deferral"},
526 { 1UL << 2, "16-byte atomic ops" }
527 };
528 char family[32], features[128], *cp, sep;
529 struct cpuinfo_ia64 *c = v;
530 unsigned long mask;
531 unsigned long proc_freq;
532 int i;
534 mask = c->features;
536 switch (c->family) {
537 case 0x07: memcpy(family, "Itanium", 8); break;
538 case 0x1f: memcpy(family, "Itanium 2", 10); break;
539 default: sprintf(family, "%u", c->family); break;
540 }
542 /* build the feature string: */
543 memcpy(features, " standard", 10);
544 cp = features;
545 sep = 0;
546 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
547 if (mask & feature_bits[i].mask) {
548 if (sep)
549 *cp++ = sep;
550 sep = ',';
551 *cp++ = ' ';
552 strcpy(cp, feature_bits[i].feature_name);
553 cp += strlen(feature_bits[i].feature_name);
554 mask &= ~feature_bits[i].mask;
555 }
556 }
557 if (mask) {
558 /* print unknown features as a hex value: */
559 if (sep)
560 *cp++ = sep;
561 sprintf(cp, " 0x%lx", mask);
562 }
564 proc_freq = cpufreq_quick_get(cpunum);
565 if (!proc_freq)
566 proc_freq = c->proc_freq / 1000;
568 seq_printf(m,
569 "processor : %d\n"
570 "vendor : %s\n"
571 "arch : IA-64\n"
572 "family : %s\n"
573 "model : %u\n"
574 "revision : %u\n"
575 "archrev : %u\n"
576 "features :%s\n" /* don't change this---it _is_ right! */
577 "cpu number : %lu\n"
578 "cpu regs : %u\n"
579 "cpu MHz : %lu.%06lu\n"
580 "itc MHz : %lu.%06lu\n"
581 "BogoMIPS : %lu.%02lu\n",
582 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
583 features, c->ppn, c->number,
584 proc_freq / 1000, proc_freq % 1000,
585 c->itc_freq / 1000000, c->itc_freq % 1000000,
586 lpj*HZ/500000, (lpj*HZ/5000) % 100);
587 #ifdef CONFIG_SMP
588 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
589 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
590 seq_printf(m,
591 "physical id: %u\n"
592 "core id : %u\n"
593 "thread id : %u\n",
594 c->socket_id, c->core_id, c->thread_id);
595 #endif
596 seq_printf(m,"\n");
598 return 0;
599 }
601 static void *
602 c_start (struct seq_file *m, loff_t *pos)
603 {
604 #ifdef CONFIG_SMP
605 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
606 ++*pos;
607 #endif
608 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
609 }
611 static void *
612 c_next (struct seq_file *m, void *v, loff_t *pos)
613 {
614 ++*pos;
615 return c_start(m, pos);
616 }
618 static void
619 c_stop (struct seq_file *m, void *v)
620 {
621 }
623 struct seq_operations cpuinfo_op = {
624 .start = c_start,
625 .next = c_next,
626 .stop = c_stop,
627 .show = show_cpuinfo
628 };
630 void
631 identify_cpu (struct cpuinfo_ia64 *c)
632 {
633 union {
634 unsigned long bits[5];
635 struct {
636 /* id 0 & 1: */
637 char vendor[16];
639 /* id 2 */
640 u64 ppn; /* processor serial number */
642 /* id 3: */
643 unsigned number : 8;
644 unsigned revision : 8;
645 unsigned model : 8;
646 unsigned family : 8;
647 unsigned archrev : 8;
648 unsigned reserved : 24;
650 /* id 4: */
651 u64 features;
652 } field;
653 } cpuid;
654 pal_vm_info_1_u_t vm1;
655 pal_vm_info_2_u_t vm2;
656 pal_status_t status;
657 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
658 int i;
660 for (i = 0; i < 5; ++i)
661 cpuid.bits[i] = ia64_get_cpuid(i);
663 memcpy(c->vendor, cpuid.field.vendor, 16);
664 #ifdef CONFIG_SMP
665 c->cpu = smp_processor_id();
667 /* below default values will be overwritten by identify_siblings()
668 * for Multi-Threading/Multi-Core capable cpu's
669 */
670 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
671 c->socket_id = -1;
673 identify_siblings(c);
674 #endif
675 c->ppn = cpuid.field.ppn;
676 c->number = cpuid.field.number;
677 c->revision = cpuid.field.revision;
678 c->model = cpuid.field.model;
679 c->family = cpuid.field.family;
680 c->archrev = cpuid.field.archrev;
681 c->features = cpuid.field.features;
683 status = ia64_pal_vm_summary(&vm1, &vm2);
684 if (status == PAL_STATUS_SUCCESS) {
685 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
686 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
687 }
688 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
689 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
690 }
692 void
693 setup_per_cpu_areas (void)
694 {
695 /* start_kernel() requires this... */
696 #ifdef CONFIG_ACPI_HOTPLUG_CPU
697 prefill_possible_map();
698 #endif
699 }
701 /*
702 * Calculate the max. cache line size.
703 *
704 * In addition, the minimum of the i-cache stride sizes is calculated for
705 * "flush_icache_range()".
706 */
707 static void
708 get_max_cacheline_size (void)
709 {
710 unsigned long line_size, max = 1;
711 unsigned int cache_size = 0;
712 u64 l, levels, unique_caches;
713 pal_cache_config_info_t cci;
714 s64 status;
716 status = ia64_pal_cache_summary(&levels, &unique_caches);
717 if (status != 0) {
718 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
719 __FUNCTION__, status);
720 max = SMP_CACHE_BYTES;
721 /* Safest setup for "flush_icache_range()" */
722 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
723 goto out;
724 }
726 for (l = 0; l < levels; ++l) {
727 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
728 &cci);
729 if (status != 0) {
730 printk(KERN_ERR
731 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
732 __FUNCTION__, l, status);
733 max = SMP_CACHE_BYTES;
734 /* The safest setup for "flush_icache_range()" */
735 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
736 cci.pcci_unified = 1;
737 }
738 line_size = 1 << cci.pcci_line_size;
739 if (line_size > max)
740 max = line_size;
741 if (cache_size < cci.pcci_cache_size)
742 cache_size = cci.pcci_cache_size;
743 if (!cci.pcci_unified) {
744 status = ia64_pal_cache_config_info(l,
745 /* cache_type (instruction)= */ 1,
746 &cci);
747 if (status != 0) {
748 printk(KERN_ERR
749 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
750 __FUNCTION__, l, status);
751 /* The safest setup for "flush_icache_range()" */
752 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
753 }
754 }
755 if (cci.pcci_stride < ia64_i_cache_stride_shift)
756 ia64_i_cache_stride_shift = cci.pcci_stride;
757 }
758 out:
759 #ifdef CONFIG_SMP
760 max_cache_size = max(max_cache_size, cache_size);
761 #endif
762 if (max > ia64_max_cacheline_size)
763 ia64_max_cacheline_size = max;
764 }
766 /*
767 * cpu_init() initializes state that is per-CPU. This function acts
768 * as a 'CPU state barrier', nothing should get across.
769 */
770 void
771 cpu_init (void)
772 {
773 extern void __devinit ia64_mmu_init (void *);
774 unsigned long num_phys_stacked;
775 pal_vm_info_2_u_t vmi;
776 unsigned int max_ctx;
777 struct cpuinfo_ia64 *cpu_info;
778 void *cpu_data;
780 cpu_data = per_cpu_init();
782 /*
783 * We set ar.k3 so that assembly code in MCA handler can compute
784 * physical addresses of per cpu variables with a simple:
785 * phys = ar.k3 + &per_cpu_var
786 */
787 ia64_set_kr(IA64_KR_PER_CPU_DATA,
788 ia64_tpa(cpu_data) - (long) __per_cpu_start);
790 get_max_cacheline_size();
792 /*
793 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
794 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
795 * depends on the data returned by identify_cpu(). We break the dependency by
796 * accessing cpu_data() through the canonical per-CPU address.
797 */
798 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
799 identify_cpu(cpu_info);
801 #ifdef CONFIG_MCKINLEY
802 {
803 # define FEATURE_SET 16
804 struct ia64_pal_retval iprv;
806 if (cpu_info->family == 0x1f) {
807 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
808 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
809 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
810 (iprv.v1 | 0x80), FEATURE_SET, 0);
811 }
812 }
813 #endif
815 /* Clear the stack memory reserved for pt_regs: */
816 memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
818 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
820 /*
821 * Initialize the page-table base register to a global
822 * directory with all zeroes. This ensure that we can handle
823 * TLB-misses to user address-space even before we created the
824 * first user address-space. This may happen, e.g., due to
825 * aggressive use of lfetch.fault.
826 */
827 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
829 /*
830 * Initialize default control register to defer speculative faults except
831 * for those arising from TLB misses, which are not deferred. The
832 * kernel MUST NOT depend on a particular setting of these bits (in other words,
833 * the kernel must have recovery code for all speculative accesses). Turn on
834 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
835 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
836 * be fine).
837 */
838 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
839 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
840 atomic_inc(&init_mm.mm_count);
841 current->active_mm = &init_mm;
842 if (current->mm)
843 BUG();
845 ia64_mmu_init(ia64_imva(cpu_data));
846 ia64_mca_cpu_init(ia64_imva(cpu_data));
848 #ifdef CONFIG_IA32_SUPPORT
849 ia32_cpu_init();
850 #endif
852 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
853 ia64_set_itc(0);
855 /* disable all local interrupt sources: */
856 ia64_set_itv(1 << 16);
857 ia64_set_lrr0(1 << 16);
858 ia64_set_lrr1(1 << 16);
859 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
860 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
862 /* clear TPR & XTP to enable all interrupt classes: */
863 ia64_setreg(_IA64_REG_CR_TPR, 0);
864 #ifdef CONFIG_SMP
865 normal_xtp();
866 #endif
868 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
869 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
870 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
871 else {
872 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
873 max_ctx = (1U << 15) - 1; /* use architected minimum */
874 }
875 while (max_ctx < ia64_ctx.max_ctx) {
876 unsigned int old = ia64_ctx.max_ctx;
877 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
878 break;
879 }
881 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
882 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
883 "stacked regs\n");
884 num_phys_stacked = 96;
885 }
886 /* size of physical stacked register partition plus 8 bytes: */
887 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
888 platform_cpu_init();
889 pm_idle = default_idle;
890 }
892 /*
893 * On SMP systems, when the scheduler does migration-cost autodetection,
894 * it needs a way to flush as much of the CPU's caches as possible.
895 */
896 void sched_cacheflush(void)
897 {
898 ia64_sal_cache_flush(3);
899 }
901 void
902 check_bugs (void)
903 {
904 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
905 (unsigned long) __end___mckinley_e9_bundles);
906 }