ia64/xen-unstable

view tools/ioemu/target-i386-dm/exec-dm.c @ 13027:7fdf6e0f12db

Fix deadlock when accessing IO memory.

Signed-off-by: Steven Hand <steven@xensource.com>
author Steven Hand <steven@xensource.com>
date Thu Dec 14 12:35:23 2006 +0000 (2006-12-14)
parents 0946c90c1105
children 4a347a6ed5dc
line source
1 /*
2 * virtual page mapping and translated block handling
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #ifdef _WIN32
22 #include <windows.h>
23 #else
24 #include <sys/types.h>
25 #include <sys/mman.h>
26 #endif
27 #include <stdlib.h>
28 #include <stdio.h>
29 #include <stdarg.h>
30 #include <string.h>
31 #include <errno.h>
32 #include <unistd.h>
33 #include <inttypes.h>
35 #include <xen/hvm/e820.h>
37 #include "cpu.h"
38 #include "exec-all.h"
39 #include "vl.h"
41 //#define DEBUG_TB_INVALIDATE
42 //#define DEBUG_FLUSH
43 //#define DEBUG_TLB
45 /* make various TB consistency checks */
46 //#define DEBUG_TB_CHECK
47 //#define DEBUG_TLB_CHECK
49 #ifndef CONFIG_DM
50 /* threshold to flush the translated code buffer */
51 #define CODE_GEN_BUFFER_MAX_SIZE (CODE_GEN_BUFFER_SIZE - CODE_GEN_MAX_SIZE)
53 #define SMC_BITMAP_USE_THRESHOLD 10
55 #define MMAP_AREA_START 0x00000000
56 #define MMAP_AREA_END 0xa8000000
58 TranslationBlock tbs[CODE_GEN_MAX_BLOCKS];
59 TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
60 TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
61 int nb_tbs;
62 /* any access to the tbs or the page table must use this lock */
63 spinlock_t tb_lock = SPIN_LOCK_UNLOCKED;
65 uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
66 uint8_t *code_gen_ptr;
67 #endif /* !CONFIG_DM */
69 uint64_t phys_ram_size;
70 extern uint64_t ram_size;
71 int phys_ram_fd;
72 uint8_t *phys_ram_base;
73 uint8_t *phys_ram_dirty;
75 CPUState *first_cpu;
76 /* current CPU in the current thread. It is only valid inside
77 cpu_exec() */
78 CPUState *cpu_single_env;
80 typedef struct PageDesc {
81 /* list of TBs intersecting this ram page */
82 TranslationBlock *first_tb;
83 /* in order to optimize self modifying code, we count the number
84 of lookups we do to a given page to use a bitmap */
85 unsigned int code_write_count;
86 uint8_t *code_bitmap;
87 #if defined(CONFIG_USER_ONLY)
88 unsigned long flags;
89 #endif
90 } PageDesc;
92 typedef struct PhysPageDesc {
93 /* offset in host memory of the page + io_index in the low 12 bits */
94 unsigned long phys_offset;
95 } PhysPageDesc;
97 typedef struct VirtPageDesc {
98 /* physical address of code page. It is valid only if 'valid_tag'
99 matches 'virt_valid_tag' */
100 target_ulong phys_addr;
101 unsigned int valid_tag;
102 #if !defined(CONFIG_SOFTMMU)
103 /* original page access rights. It is valid only if 'valid_tag'
104 matches 'virt_valid_tag' */
105 unsigned int prot;
106 #endif
107 } VirtPageDesc;
109 #define L2_BITS 10
110 #define L1_BITS (32 - L2_BITS - TARGET_PAGE_BITS)
112 #define L1_SIZE (1 << L1_BITS)
113 #define L2_SIZE (1 << L2_BITS)
115 unsigned long qemu_real_host_page_size;
116 unsigned long qemu_host_page_bits;
117 unsigned long qemu_host_page_size;
118 unsigned long qemu_host_page_mask;
120 /* io memory support */
121 CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
122 CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
123 void *io_mem_opaque[IO_MEM_NB_ENTRIES];
124 static int io_mem_nb = 1;
126 /* log support */
127 char *logfilename = "/tmp/qemu.log";
128 FILE *logfile;
129 int loglevel;
131 void cpu_exec_init(CPUState *env)
132 {
133 CPUState **penv;
134 int cpu_index;
136 env->next_cpu = NULL;
137 penv = &first_cpu;
138 cpu_index = 0;
139 while (*penv != NULL) {
140 penv = (CPUState **)&(*penv)->next_cpu;
141 cpu_index++;
142 }
143 env->cpu_index = cpu_index;
144 *penv = env;
146 /* alloc dirty bits array */
147 phys_ram_dirty = qemu_malloc(phys_ram_size >> TARGET_PAGE_BITS);
148 }
150 /* enable or disable low levels log */
151 void cpu_set_log(int log_flags)
152 {
153 loglevel = log_flags;
154 if (!logfile) {
155 logfile = fopen(logfilename, "w");
156 if (!logfile) {
157 perror(logfilename);
158 _exit(1);
159 }
160 #if !defined(CONFIG_SOFTMMU)
161 /* must avoid mmap() usage of glibc by setting a buffer "by hand" */
162 {
163 static uint8_t logfile_buf[4096];
164 setvbuf(logfile, logfile_buf, _IOLBF, sizeof(logfile_buf));
165 }
166 #else
167 setvbuf(logfile, NULL, _IOLBF, 0);
168 #endif
169 stdout = logfile;
170 stderr = logfile;
171 }
172 }
174 void cpu_set_log_filename(const char *filename)
175 {
176 logfilename = strdup(filename);
177 }
179 /* mask must never be zero, except for A20 change call */
180 void cpu_interrupt(CPUState *env, int mask)
181 {
182 env->interrupt_request |= mask;
183 }
185 void cpu_reset_interrupt(CPUState *env, int mask)
186 {
187 env->interrupt_request &= ~mask;
188 }
190 CPULogItem cpu_log_items[] = {
191 { CPU_LOG_TB_OUT_ASM, "out_asm",
192 "show generated host assembly code for each compiled TB" },
193 { CPU_LOG_TB_IN_ASM, "in_asm",
194 "show target assembly code for each compiled TB" },
195 { CPU_LOG_TB_OP, "op",
196 "show micro ops for each compiled TB (only usable if 'in_asm' used)" },
197 #ifdef TARGET_I386
198 { CPU_LOG_TB_OP_OPT, "op_opt",
199 "show micro ops after optimization for each compiled TB" },
200 #endif
201 { CPU_LOG_INT, "int",
202 "show interrupts/exceptions in short format" },
203 { CPU_LOG_EXEC, "exec",
204 "show trace before each executed TB (lots of logs)" },
205 { CPU_LOG_TB_CPU, "cpu",
206 "show CPU state before bloc translation" },
207 #ifdef TARGET_I386
208 { CPU_LOG_PCALL, "pcall",
209 "show protected mode far calls/returns/exceptions" },
210 #endif
211 #ifdef DEBUG_IOPORT
212 { CPU_LOG_IOPORT, "ioport",
213 "show all i/o ports accesses" },
214 #endif
215 { 0, NULL, NULL },
216 };
218 static int cmp1(const char *s1, int n, const char *s2)
219 {
220 if (strlen(s2) != n)
221 return 0;
222 return memcmp(s1, s2, n) == 0;
223 }
225 /* takes a comma separated list of log masks. Return 0 if error. */
226 int cpu_str_to_log_mask(const char *str)
227 {
228 CPULogItem *item;
229 int mask;
230 const char *p, *p1;
232 p = str;
233 mask = 0;
234 for(;;) {
235 p1 = strchr(p, ',');
236 if (!p1)
237 p1 = p + strlen(p);
238 if(cmp1(p,p1-p,"all")) {
239 for(item = cpu_log_items; item->mask != 0; item++) {
240 mask |= item->mask;
241 }
242 } else {
243 for(item = cpu_log_items; item->mask != 0; item++) {
244 if (cmp1(p, p1 - p, item->name))
245 goto found;
246 }
247 return 0;
248 }
249 found:
250 mask |= item->mask;
251 if (*p1 != ',')
252 break;
253 p = p1 + 1;
254 }
255 return mask;
256 }
258 void cpu_abort(CPUState *env, const char *fmt, ...)
259 {
260 va_list ap;
262 va_start(ap, fmt);
263 fprintf(stderr, "qemu: fatal: ");
264 vfprintf(stderr, fmt, ap);
265 fprintf(stderr, "\n");
266 va_end(ap);
267 abort();
268 }
271 /* XXX: Simple implementation. Fix later */
272 #define MAX_MMIO 32
273 struct mmio_space {
274 target_phys_addr_t start;
275 unsigned long size;
276 unsigned long io_index;
277 } mmio[MAX_MMIO];
278 unsigned long mmio_cnt;
280 /* register physical memory. 'size' must be a multiple of the target
281 page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
282 io memory page */
283 void cpu_register_physical_memory(target_phys_addr_t start_addr,
284 unsigned long size,
285 unsigned long phys_offset)
286 {
287 int i;
289 for (i = 0; i < mmio_cnt; i++) {
290 if(mmio[i].start == start_addr) {
291 mmio[i].io_index = phys_offset;
292 mmio[i].size = size;
293 return;
294 }
295 }
297 if (mmio_cnt == MAX_MMIO) {
298 fprintf(logfile, "too many mmio regions\n");
299 exit(-1);
300 }
302 mmio[mmio_cnt].io_index = phys_offset;
303 mmio[mmio_cnt].start = start_addr;
304 mmio[mmio_cnt++].size = size;
305 }
307 /* mem_read and mem_write are arrays of functions containing the
308 function to access byte (index 0), word (index 1) and dword (index
309 2). All functions must be supplied. If io_index is non zero, the
310 corresponding io zone is modified. If it is zero, a new io zone is
311 allocated. The return value can be used with
312 cpu_register_physical_memory(). (-1) is returned if error. */
313 int cpu_register_io_memory(int io_index,
314 CPUReadMemoryFunc **mem_read,
315 CPUWriteMemoryFunc **mem_write,
316 void *opaque)
317 {
318 int i;
320 if (io_index <= 0) {
321 if (io_index >= IO_MEM_NB_ENTRIES)
322 return -1;
323 io_index = io_mem_nb++;
324 } else {
325 if (io_index >= IO_MEM_NB_ENTRIES)
326 return -1;
327 }
329 for(i = 0;i < 3; i++) {
330 io_mem_read[io_index][i] = mem_read[i];
331 io_mem_write[io_index][i] = mem_write[i];
332 }
333 io_mem_opaque[io_index] = opaque;
334 return io_index << IO_MEM_SHIFT;
335 }
337 CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index)
338 {
339 return io_mem_write[io_index >> IO_MEM_SHIFT];
340 }
342 CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index)
343 {
344 return io_mem_read[io_index >> IO_MEM_SHIFT];
345 }
347 #ifdef __ia64__
348 /* IA64 has seperate I/D cache, with coherence maintained by DMA controller.
349 * So to emulate right behavior that guest OS is assumed, we need to flush
350 * I/D cache here.
351 */
352 static void sync_icache(unsigned long address, int len)
353 {
354 int l;
356 for(l = 0; l < (len + 32); l += 32)
357 __ia64_fc(address + l);
359 ia64_sync_i();
360 ia64_srlz_i();
361 }
362 #endif
364 /* physical memory access (slow version, mainly for debug) */
365 #if defined(CONFIG_USER_ONLY)
366 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
367 int len, int is_write)
368 {
369 int l, flags;
370 target_ulong page;
372 while (len > 0) {
373 page = addr & TARGET_PAGE_MASK;
374 l = (page + TARGET_PAGE_SIZE) - addr;
375 if (l > len)
376 l = len;
377 flags = page_get_flags(page);
378 if (!(flags & PAGE_VALID))
379 return;
380 if (is_write) {
381 if (!(flags & PAGE_WRITE))
382 return;
383 memcpy((uint8_t *)addr, buf, len);
384 } else {
385 if (!(flags & PAGE_READ))
386 return;
387 memcpy(buf, (uint8_t *)addr, len);
388 }
389 len -= l;
390 buf += l;
391 addr += l;
392 }
393 }
394 #else
396 int iomem_index(target_phys_addr_t addr)
397 {
398 int i;
400 for (i = 0; i < mmio_cnt; i++) {
401 unsigned long start, end;
403 start = mmio[i].start;
404 end = mmio[i].start + mmio[i].size;
406 if ((addr >= start) && (addr < end)){
407 return (mmio[i].io_index >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
408 }
409 }
410 return 0;
411 }
413 static inline int paddr_is_ram(target_phys_addr_t addr)
414 {
415 /* Is this guest physical address RAM-backed? */
416 #if defined(CONFIG_DM) && (defined(__i386__) || defined(__x86_64__))
417 if (ram_size <= HVM_BELOW_4G_RAM_END)
418 /* RAM is contiguous */
419 return (addr < ram_size);
420 else
421 /* There is RAM below and above the MMIO hole */
422 return ((addr < HVM_BELOW_4G_MMIO_START) ||
423 ((addr >= HVM_BELOW_4G_MMIO_START + HVM_BELOW_4G_MMIO_LENGTH)
424 && (addr < ram_size + HVM_BELOW_4G_MMIO_LENGTH)));
425 #else
426 return (addr < ram_size);
427 #endif
428 }
430 #if defined(__i386__) || defined(__x86_64__)
431 #define phys_ram_addr(x) (qemu_map_cache(x))
432 #elif defined(__ia64__)
433 #define phys_ram_addr(x) (phys_ram_base + (x))
434 #endif
436 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
437 int len, int is_write)
438 {
439 int l, io_index;
440 uint8_t *ptr;
441 uint32_t val;
443 #if defined(__i386__) || defined(__x86_64__)
444 static pthread_mutex_t mutex = PTHREAD_RECURSIVE_MUTEX_INITIALIZER_NP;
445 pthread_mutex_lock(&mutex);
446 #endif
448 while (len > 0) {
449 /* How much can we copy before the next page boundary? */
450 l = TARGET_PAGE_SIZE - (addr & ~TARGET_PAGE_MASK);
451 if (l > len)
452 l = len;
454 io_index = iomem_index(addr);
455 if (is_write) {
456 if (io_index) {
457 if (l >= 4 && ((addr & 3) == 0)) {
458 /* 32 bit read access */
459 val = ldl_raw(buf);
460 io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
461 l = 4;
462 } else if (l >= 2 && ((addr & 1) == 0)) {
463 /* 16 bit read access */
464 val = lduw_raw(buf);
465 io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
466 l = 2;
467 } else {
468 /* 8 bit access */
469 val = ldub_raw(buf);
470 io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val);
471 l = 1;
472 }
473 } else if (paddr_is_ram(addr)) {
474 /* Reading from RAM */
475 ptr = phys_ram_addr(addr);
476 memcpy(ptr, buf, l);
477 #ifdef __ia64__
478 sync_icache(ptr, l);
479 #endif
480 }
481 } else {
482 if (io_index) {
483 if (l >= 4 && ((addr & 3) == 0)) {
484 /* 32 bit read access */
485 val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
486 stl_raw(buf, val);
487 l = 4;
488 } else if (l >= 2 && ((addr & 1) == 0)) {
489 /* 16 bit read access */
490 val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
491 stw_raw(buf, val);
492 l = 2;
493 } else {
494 /* 8 bit access */
495 val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr);
496 stb_raw(buf, val);
497 l = 1;
498 }
499 } else if (paddr_is_ram(addr)) {
500 /* Reading from RAM */
501 ptr = phys_ram_addr(addr);
502 memcpy(buf, ptr, l);
503 } else {
504 /* Neither RAM nor known MMIO space */
505 memset(buf, 0xff, len);
506 }
507 }
508 len -= l;
509 buf += l;
510 addr += l;
511 }
513 #if defined(__i386__) || defined(__x86_64__)
514 pthread_mutex_unlock(&mutex);
515 #endif
516 }
517 #endif
519 /* virtual memory access for debug */
520 int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
521 uint8_t *buf, int len, int is_write)
522 {
523 int l;
524 target_ulong page, phys_addr;
526 while (len > 0) {
527 page = addr & TARGET_PAGE_MASK;
528 phys_addr = cpu_get_phys_page_debug(env, page);
529 /* if no physical page mapped, return an error */
530 if (phys_addr == -1)
531 return -1;
532 l = (page + TARGET_PAGE_SIZE) - addr;
533 if (l > len)
534 l = len;
535 cpu_physical_memory_rw(phys_addr + (addr & ~TARGET_PAGE_MASK),
536 buf, l, is_write);
537 len -= l;
538 buf += l;
539 addr += l;
540 }
541 return 0;
542 }
544 void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
545 int dirty_flags)
546 {
547 unsigned long length;
548 int i, mask, len;
549 uint8_t *p;
551 start &= TARGET_PAGE_MASK;
552 end = TARGET_PAGE_ALIGN(end);
554 length = end - start;
555 if (length == 0)
556 return;
557 mask = ~dirty_flags;
558 p = phys_ram_dirty + (start >> TARGET_PAGE_BITS);
559 len = length >> TARGET_PAGE_BITS;
560 for(i = 0; i < len; i++)
561 p[i] &= mask;
563 return;
564 }