ia64/xen-unstable

view linux-2.6-xen-sparse/arch/xen/i386/kernel/smp.c @ 6283:7f9b024a509e

Actually make suspending SMP domUs work: the previous commit didn't
bring the other vcpus up correctly.

Signed-off-by: Steven Smith, sos22@cam.ac.uk
author sos22@douglas.cl.cam.ac.uk
date Thu Aug 18 15:27:55 2005 +0000 (2005-08-18)
parents 56a63f9f378f
children 5a7efe0cf5fb
line source
1 /*
2 * Intel SMP support routines.
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
6 *
7 * This code is released under the GNU General Public License version 2 or
8 * later.
9 */
11 #include <linux/init.h>
13 #include <linux/mm.h>
14 #include <linux/irq.h>
15 #include <linux/delay.h>
16 #include <linux/spinlock.h>
17 #include <linux/smp_lock.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/cache.h>
21 #include <linux/interrupt.h>
22 #include <linux/cpu.h>
24 #include <asm/mtrr.h>
25 #include <asm/tlbflush.h>
26 #if 0
27 #include <mach_apic.h>
28 #endif
29 #include <asm-xen/evtchn.h>
31 #define xxprint(msg) HYPERVISOR_console_io(CONSOLEIO_write, strlen(msg), msg)
33 /*
34 * Some notes on x86 processor bugs affecting SMP operation:
35 *
36 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
37 * The Linux implications for SMP are handled as follows:
38 *
39 * Pentium III / [Xeon]
40 * None of the E1AP-E3AP errata are visible to the user.
41 *
42 * E1AP. see PII A1AP
43 * E2AP. see PII A2AP
44 * E3AP. see PII A3AP
45 *
46 * Pentium II / [Xeon]
47 * None of the A1AP-A3AP errata are visible to the user.
48 *
49 * A1AP. see PPro 1AP
50 * A2AP. see PPro 2AP
51 * A3AP. see PPro 7AP
52 *
53 * Pentium Pro
54 * None of 1AP-9AP errata are visible to the normal user,
55 * except occasional delivery of 'spurious interrupt' as trap #15.
56 * This is very rare and a non-problem.
57 *
58 * 1AP. Linux maps APIC as non-cacheable
59 * 2AP. worked around in hardware
60 * 3AP. fixed in C0 and above steppings microcode update.
61 * Linux does not use excessive STARTUP_IPIs.
62 * 4AP. worked around in hardware
63 * 5AP. symmetric IO mode (normal Linux operation) not affected.
64 * 'noapic' mode has vector 0xf filled out properly.
65 * 6AP. 'noapic' mode might be affected - fixed in later steppings
66 * 7AP. We do not assume writes to the LVT deassering IRQs
67 * 8AP. We do not enable low power mode (deep sleep) during MP bootup
68 * 9AP. We do not use mixed mode
69 *
70 * Pentium
71 * There is a marginal case where REP MOVS on 100MHz SMP
72 * machines with B stepping processors can fail. XXX should provide
73 * an L1cache=Writethrough or L1cache=off option.
74 *
75 * B stepping CPUs may hang. There are hardware work arounds
76 * for this. We warn about it in case your board doesn't have the work
77 * arounds. Basically thats so I can tell anyone with a B stepping
78 * CPU and SMP problems "tough".
79 *
80 * Specific items [From Pentium Processor Specification Update]
81 *
82 * 1AP. Linux doesn't use remote read
83 * 2AP. Linux doesn't trust APIC errors
84 * 3AP. We work around this
85 * 4AP. Linux never generated 3 interrupts of the same priority
86 * to cause a lost local interrupt.
87 * 5AP. Remote read is never used
88 * 6AP. not affected - worked around in hardware
89 * 7AP. not affected - worked around in hardware
90 * 8AP. worked around in hardware - we get explicit CS errors if not
91 * 9AP. only 'noapic' mode affected. Might generate spurious
92 * interrupts, we log only the first one and count the
93 * rest silently.
94 * 10AP. not affected - worked around in hardware
95 * 11AP. Linux reads the APIC between writes to avoid this, as per
96 * the documentation. Make sure you preserve this as it affects
97 * the C stepping chips too.
98 * 12AP. not affected - worked around in hardware
99 * 13AP. not affected - worked around in hardware
100 * 14AP. we always deassert INIT during bootup
101 * 15AP. not affected - worked around in hardware
102 * 16AP. not affected - worked around in hardware
103 * 17AP. not affected - worked around in hardware
104 * 18AP. not affected - worked around in hardware
105 * 19AP. not affected - worked around in BIOS
106 *
107 * If this sounds worrying believe me these bugs are either ___RARE___,
108 * or are signal timing bugs worked around in hardware and there's
109 * about nothing of note with C stepping upwards.
110 */
112 DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0, };
114 /*
115 * the following functions deal with sending IPIs between CPUs.
116 *
117 * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
118 */
120 static inline int __prepare_ICR (unsigned int shortcut, int vector)
121 {
122 return APIC_DM_FIXED | shortcut | vector | APIC_DEST_LOGICAL;
123 }
125 static inline int __prepare_ICR2 (unsigned int mask)
126 {
127 return SET_APIC_DEST_FIELD(mask);
128 }
130 DECLARE_PER_CPU(int, ipi_to_evtchn[NR_IPIS]);
132 unsigned uber_debug;
134 static inline void __send_IPI_one(unsigned int cpu, int vector)
135 {
136 unsigned int evtchn;
137 int r;
139 evtchn = per_cpu(ipi_to_evtchn, cpu)[vector];
140 // printk("send_IPI_mask_bitmask cpu %d vector %d evtchn %d\n", cpu, vector, evtchn);
141 if (evtchn) {
142 #if 0
143 shared_info_t *s = HYPERVISOR_shared_info;
144 while (synch_test_bit(evtchn, &s->evtchn_pending[0]) ||
145 synch_test_bit(evtchn, &s->evtchn_mask[0]))
146 ;
147 #endif
148 if (uber_debug)
149 printk("<0>Notifying on evtchn %d.\n", evtchn);
150 if ((r = notify_via_evtchn(evtchn)) != 0)
151 printk("<0>Hypervisor stopped us sending an IPI: %d.\n",
152 r);
153 } else
154 printk("send_IPI to unbound port %d/%d",
155 cpu, vector);
156 }
158 void __send_IPI_shortcut(unsigned int shortcut, int vector)
159 {
160 int cpu;
162 switch (shortcut) {
163 case APIC_DEST_SELF:
164 __send_IPI_one(smp_processor_id(), vector);
165 break;
166 case APIC_DEST_ALLBUT:
167 for (cpu = 0; cpu < NR_CPUS; ++cpu) {
168 if (cpu == smp_processor_id())
169 continue;
170 if (cpu_isset(cpu, cpu_online_map)) {
171 if (uber_debug)
172 printk("<0>Sending ipi to %d.\n", cpu);
173 __send_IPI_one(cpu, vector);
174 }
175 }
176 break;
177 default:
178 printk("XXXXXX __send_IPI_shortcut %08x vector %d\n", shortcut,
179 vector);
180 break;
181 }
182 }
184 void fastcall send_IPI_self(int vector)
185 {
186 __send_IPI_shortcut(APIC_DEST_SELF, vector);
187 }
189 /*
190 * This is only used on smaller machines.
191 */
192 void send_IPI_mask_bitmask(cpumask_t mask, int vector)
193 {
194 unsigned long flags;
195 unsigned int cpu;
197 local_irq_save(flags);
198 WARN_ON(cpus_addr(mask)[0] & ~cpus_addr(cpu_online_map)[0]);
200 for (cpu = 0; cpu < NR_CPUS; ++cpu) {
201 if (cpu_isset(cpu, mask)) {
202 __send_IPI_one(cpu, vector);
203 }
204 }
206 local_irq_restore(flags);
207 }
209 void send_IPI_mask_sequence(cpumask_t mask, int vector)
210 {
212 send_IPI_mask_bitmask(mask, vector);
213 }
215 #include <mach_ipi.h> /* must come after the send_IPI functions above for inlining */
217 #if 0 /* XEN */
218 /*
219 * Smarter SMP flushing macros.
220 * c/o Linus Torvalds.
221 *
222 * These mean you can really definitely utterly forget about
223 * writing to user space from interrupts. (Its not allowed anyway).
224 *
225 * Optimizations Manfred Spraul <manfred@colorfullife.com>
226 */
228 static cpumask_t flush_cpumask;
229 static struct mm_struct * flush_mm;
230 static unsigned long flush_va;
231 static DEFINE_SPINLOCK(tlbstate_lock);
232 #define FLUSH_ALL 0xffffffff
234 /*
235 * We cannot call mmdrop() because we are in interrupt context,
236 * instead update mm->cpu_vm_mask.
237 *
238 * We need to reload %cr3 since the page tables may be going
239 * away from under us..
240 */
241 static inline void leave_mm (unsigned long cpu)
242 {
243 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
244 BUG();
245 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
246 load_cr3(swapper_pg_dir);
247 }
249 /*
250 *
251 * The flush IPI assumes that a thread switch happens in this order:
252 * [cpu0: the cpu that switches]
253 * 1) switch_mm() either 1a) or 1b)
254 * 1a) thread switch to a different mm
255 * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
256 * Stop ipi delivery for the old mm. This is not synchronized with
257 * the other cpus, but smp_invalidate_interrupt ignore flush ipis
258 * for the wrong mm, and in the worst case we perform a superflous
259 * tlb flush.
260 * 1a2) set cpu_tlbstate to TLBSTATE_OK
261 * Now the smp_invalidate_interrupt won't call leave_mm if cpu0
262 * was in lazy tlb mode.
263 * 1a3) update cpu_tlbstate[].active_mm
264 * Now cpu0 accepts tlb flushes for the new mm.
265 * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
266 * Now the other cpus will send tlb flush ipis.
267 * 1a4) change cr3.
268 * 1b) thread switch without mm change
269 * cpu_tlbstate[].active_mm is correct, cpu0 already handles
270 * flush ipis.
271 * 1b1) set cpu_tlbstate to TLBSTATE_OK
272 * 1b2) test_and_set the cpu bit in cpu_vm_mask.
273 * Atomically set the bit [other cpus will start sending flush ipis],
274 * and test the bit.
275 * 1b3) if the bit was 0: leave_mm was called, flush the tlb.
276 * 2) switch %%esp, ie current
277 *
278 * The interrupt must handle 2 special cases:
279 * - cr3 is changed before %%esp, ie. it cannot use current->{active_,}mm.
280 * - the cpu performs speculative tlb reads, i.e. even if the cpu only
281 * runs in kernel space, the cpu could load tlb entries for user space
282 * pages.
283 *
284 * The good news is that cpu_tlbstate is local to each cpu, no
285 * write/read ordering problems.
286 */
288 /*
289 * TLB flush IPI:
290 *
291 * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
292 * 2) Leave the mm if we are in the lazy tlb mode.
293 */
295 irqreturn_t smp_invalidate_interrupt(int irq, void *dev_id,
296 struct pt_regs *regs)
297 {
298 unsigned long cpu;
300 cpu = get_cpu();
302 if (!cpu_isset(cpu, flush_cpumask))
303 goto out;
304 /*
305 * This was a BUG() but until someone can quote me the
306 * line from the intel manual that guarantees an IPI to
307 * multiple CPUs is retried _only_ on the erroring CPUs
308 * its staying as a return
309 *
310 * BUG();
311 */
313 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
314 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
315 if (flush_va == FLUSH_ALL)
316 local_flush_tlb();
317 else
318 __flush_tlb_one(flush_va);
319 } else
320 leave_mm(cpu);
321 }
322 smp_mb__before_clear_bit();
323 cpu_clear(cpu, flush_cpumask);
324 smp_mb__after_clear_bit();
325 out:
326 put_cpu_no_resched();
328 return IRQ_HANDLED;
329 }
331 static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
332 unsigned long va)
333 {
334 /*
335 * A couple of (to be removed) sanity checks:
336 *
337 * - current CPU must not be in mask
338 * - mask must exist :)
339 */
340 BUG_ON(cpus_empty(cpumask));
341 BUG_ON(cpu_isset(smp_processor_id(), cpumask));
342 BUG_ON(!mm);
344 /* If a CPU which we ran on has gone down, OK. */
345 cpus_and(cpumask, cpumask, cpu_online_map);
346 if (cpus_empty(cpumask))
347 return;
349 /*
350 * i'm not happy about this global shared spinlock in the
351 * MM hot path, but we'll see how contended it is.
352 * Temporarily this turns IRQs off, so that lockups are
353 * detected by the NMI watchdog.
354 */
355 spin_lock(&tlbstate_lock);
357 flush_mm = mm;
358 flush_va = va;
359 #if NR_CPUS <= BITS_PER_LONG
360 atomic_set_mask(cpumask, &flush_cpumask);
361 #else
362 {
363 int k;
364 unsigned long *flush_mask = (unsigned long *)&flush_cpumask;
365 unsigned long *cpu_mask = (unsigned long *)&cpumask;
366 for (k = 0; k < BITS_TO_LONGS(NR_CPUS); ++k)
367 atomic_set_mask(cpu_mask[k], &flush_mask[k]);
368 }
369 #endif
370 /*
371 * We have to send the IPI only to
372 * CPUs affected.
373 */
374 send_IPI_mask(cpumask, INVALIDATE_TLB_VECTOR);
376 while (!cpus_empty(flush_cpumask))
377 /* nothing. lockup detection does not belong here */
378 mb();
380 flush_mm = NULL;
381 flush_va = 0;
382 spin_unlock(&tlbstate_lock);
383 }
385 void flush_tlb_current_task(void)
386 {
387 struct mm_struct *mm = current->mm;
388 cpumask_t cpu_mask;
390 preempt_disable();
391 cpu_mask = mm->cpu_vm_mask;
392 cpu_clear(smp_processor_id(), cpu_mask);
394 local_flush_tlb();
395 if (!cpus_empty(cpu_mask))
396 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
397 preempt_enable();
398 }
400 void flush_tlb_mm (struct mm_struct * mm)
401 {
402 cpumask_t cpu_mask;
404 preempt_disable();
405 cpu_mask = mm->cpu_vm_mask;
406 cpu_clear(smp_processor_id(), cpu_mask);
408 if (current->active_mm == mm) {
409 if (current->mm)
410 local_flush_tlb();
411 else
412 leave_mm(smp_processor_id());
413 }
414 if (!cpus_empty(cpu_mask))
415 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
417 preempt_enable();
418 }
420 void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
421 {
422 struct mm_struct *mm = vma->vm_mm;
423 cpumask_t cpu_mask;
425 preempt_disable();
426 cpu_mask = mm->cpu_vm_mask;
427 cpu_clear(smp_processor_id(), cpu_mask);
429 if (current->active_mm == mm) {
430 if(current->mm)
431 __flush_tlb_one(va);
432 else
433 leave_mm(smp_processor_id());
434 }
436 if (!cpus_empty(cpu_mask))
437 flush_tlb_others(cpu_mask, mm, va);
439 preempt_enable();
440 }
442 static void do_flush_tlb_all(void* info)
443 {
444 unsigned long cpu = smp_processor_id();
446 __flush_tlb_all();
447 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
448 leave_mm(cpu);
449 }
451 void flush_tlb_all(void)
452 {
453 on_each_cpu(do_flush_tlb_all, NULL, 1, 1);
454 }
456 #else
458 irqreturn_t smp_invalidate_interrupt(int irq, void *dev_id,
459 struct pt_regs *regs)
460 { return 0; }
461 void flush_tlb_current_task(void)
462 { xen_tlb_flush_mask(&current->mm->cpu_vm_mask); }
463 void flush_tlb_mm(struct mm_struct * mm)
464 { xen_tlb_flush_mask(&mm->cpu_vm_mask); }
465 void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
466 { xen_invlpg_mask(&vma->vm_mm->cpu_vm_mask, va); }
467 void flush_tlb_all(void)
468 { xen_tlb_flush_all(); }
470 #endif /* XEN */
472 /*
473 * this function sends a 'reschedule' IPI to another CPU.
474 * it goes straight through and wastes no time serializing
475 * anything. Worst case is that we lose a reschedule ...
476 */
477 void smp_send_reschedule(int cpu)
478 {
479 WARN_ON(cpu_is_offline(cpu));
480 send_IPI_mask(cpumask_of_cpu(cpu), RESCHEDULE_VECTOR);
481 }
483 /*
484 * Structure and data for smp_call_function(). This is designed to minimise
485 * static memory requirements. It also looks cleaner.
486 */
487 static DEFINE_SPINLOCK(call_lock);
489 struct call_data_struct {
490 void (*func) (void *info);
491 void *info;
492 atomic_t started;
493 atomic_t finished;
494 int wait;
495 };
497 static struct call_data_struct * call_data;
499 /*
500 * this function sends a 'generic call function' IPI to all other CPUs
501 * in the system.
502 */
504 int smp_call_function (void (*func) (void *info), void *info, int nonatomic,
505 int wait)
506 /*
507 * [SUMMARY] Run a function on all other CPUs.
508 * <func> The function to run. This must be fast and non-blocking.
509 * <info> An arbitrary pointer to pass to the function.
510 * <nonatomic> currently unused.
511 * <wait> If true, wait (atomically) until function has completed on other CPUs.
512 * [RETURNS] 0 on success, else a negative status code. Does not return until
513 * remote CPUs are nearly ready to execute <<func>> or are or have executed.
514 *
515 * You must not call this function with disabled interrupts or from a
516 * hardware interrupt handler or from a bottom half handler.
517 */
518 {
519 struct call_data_struct data;
520 int cpus;
522 /* Holding any lock stops cpus from going down. */
523 spin_lock(&call_lock);
524 cpus = num_online_cpus()-1;
526 if (!cpus) {
527 spin_unlock(&call_lock);
528 return 0;
529 }
531 /* Can deadlock when called with interrupts disabled */
532 WARN_ON(irqs_disabled());
534 data.func = func;
535 data.info = info;
536 atomic_set(&data.started, 0);
537 data.wait = wait;
538 if (wait)
539 atomic_set(&data.finished, 0);
541 call_data = &data;
542 mb();
544 /* Send a message to all other CPUs and wait for them to respond */
545 send_IPI_allbutself(CALL_FUNCTION_VECTOR);
547 /* Wait for response */
548 while (atomic_read(&data.started) != cpus)
549 barrier();
551 if (wait)
552 while (atomic_read(&data.finished) != cpus)
553 barrier();
554 spin_unlock(&call_lock);
556 return 0;
557 }
559 static void stop_this_cpu (void * dummy)
560 {
561 /*
562 * Remove this CPU:
563 */
564 cpu_clear(smp_processor_id(), cpu_online_map);
565 local_irq_disable();
566 #if 1
567 xxprint("stop_this_cpu disable_local_APIC\n");
568 #else
569 disable_local_APIC();
570 #endif
571 if (cpu_data[smp_processor_id()].hlt_works_ok)
572 for(;;) __asm__("hlt");
573 for (;;);
574 }
576 /*
577 * this function calls the 'stop' function on all other CPUs in the system.
578 */
580 void smp_send_stop(void)
581 {
582 smp_call_function(stop_this_cpu, NULL, 1, 0);
584 local_irq_disable();
585 #if 1
586 xxprint("smp_send_stop disable_local_APIC\n");
587 #else
588 disable_local_APIC();
589 #endif
590 local_irq_enable();
591 }
593 /*
594 * Reschedule call back. Nothing to do,
595 * all the work is done automatically when
596 * we return from the interrupt.
597 */
598 irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id,
599 struct pt_regs *regs)
600 {
602 return IRQ_HANDLED;
603 }
605 #include <linux/kallsyms.h>
606 irqreturn_t smp_call_function_interrupt(int irq, void *dev_id,
607 struct pt_regs *regs)
608 {
609 void (*func) (void *info) = call_data->func;
610 void *info = call_data->info;
611 int wait = call_data->wait;
613 /*
614 * Notify initiating CPU that I've grabbed the data and am
615 * about to execute the function
616 */
617 mb();
618 atomic_inc(&call_data->started);
619 /*
620 * At this point the info structure may be out of scope unless wait==1
621 */
622 irq_enter();
623 (*func)(info);
624 irq_exit();
626 if (wait) {
627 mb();
628 atomic_inc(&call_data->finished);
629 }
631 return IRQ_HANDLED;
632 }