ia64/xen-unstable

view linux-2.6-xen-sparse/include/asm-i386/spinlock.h @ 11221:7c9d7fc3dce5

[HVM] Fix SMBIOS entry point copy destination.
Spotted by Xiaowei Yang <xiaowei.yang@intel.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@localhost.localdomain
date Sat Aug 19 12:06:36 2006 +0100 (2006-08-19)
parents ababeabf87c5
children
line source
1 #ifndef __ASM_SPINLOCK_H
2 #define __ASM_SPINLOCK_H
4 #include <asm/atomic.h>
5 #include <asm/rwlock.h>
6 #include <asm/page.h>
7 #include <linux/config.h>
8 #include <linux/compiler.h>
9 #include <asm/smp_alt.h>
11 /*
12 * Your basic SMP spinlocks, allowing only a single CPU anywhere
13 *
14 * Simple spin lock operations. There are two variants, one clears IRQ's
15 * on the local processor, one does not.
16 *
17 * We make no fairness assumptions. They have a cost.
18 *
19 * (the type definitions are in asm/spinlock_types.h)
20 */
22 #define __raw_spin_is_locked(x) \
23 (*(volatile signed char *)(&(x)->slock) <= 0)
25 #define __raw_spin_lock_string \
26 "\n1:\t" \
27 LOCK \
28 "decb %0\n\t" \
29 "jns 3f\n" \
30 "2:\t" \
31 "rep;nop\n\t" \
32 "cmpb $0,%0\n\t" \
33 "jle 2b\n\t" \
34 "jmp 1b\n" \
35 "3:\n\t"
37 #define __raw_spin_lock_string_flags \
38 "\n1:\t" \
39 LOCK \
40 "decb %0\n\t" \
41 "jns 4f\n\t" \
42 "2:\t" \
43 "testl $0x200, %1\n\t" \
44 "jz 3f\n\t" \
45 "sti\n\t" \
46 "3:\t" \
47 "rep;nop\n\t" \
48 "cmpb $0, %0\n\t" \
49 "jle 3b\n\t" \
50 "cli\n\t" \
51 "jmp 1b\n" \
52 "4:\n\t"
54 static inline void __raw_spin_lock(raw_spinlock_t *lock)
55 {
56 __asm__ __volatile__(
57 __raw_spin_lock_string
58 :"=m" (lock->slock) : : "memory");
59 }
61 static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
62 {
63 __asm__ __volatile__(
64 __raw_spin_lock_string_flags
65 :"=m" (lock->slock) : "r" (flags) : "memory");
66 }
68 static inline int __raw_spin_trylock(raw_spinlock_t *lock)
69 {
70 char oldval;
71 #ifdef CONFIG_SMP_ALTERNATIVES
72 __asm__ __volatile__(
73 "1:movb %1,%b0\n"
74 "movb $0,%1\n"
75 "2:"
76 ".section __smp_alternatives,\"a\"\n"
77 ".long 1b\n"
78 ".long 3f\n"
79 ".previous\n"
80 ".section __smp_replacements,\"a\"\n"
81 "3: .byte 2b - 1b\n"
82 ".byte 5f-4f\n"
83 ".byte 0\n"
84 ".byte 6f-5f\n"
85 ".byte -1\n"
86 "4: xchgb %b0,%1\n"
87 "5: movb %1,%b0\n"
88 "movb $0,%1\n"
89 "6:\n"
90 ".previous\n"
91 :"=q" (oldval), "=m" (lock->slock)
92 :"0" (0) : "memory");
93 #else
94 __asm__ __volatile__(
95 "xchgb %b0,%1"
96 :"=q" (oldval), "=m" (lock->slock)
97 :"0" (0) : "memory");
98 #endif
99 return oldval > 0;
100 }
102 /*
103 * __raw_spin_unlock based on writing $1 to the low byte.
104 * This method works. Despite all the confusion.
105 * (except on PPro SMP or if we are using OOSTORE, so we use xchgb there)
106 * (PPro errata 66, 92)
107 */
109 #if !defined(CONFIG_X86_OOSTORE) && !defined(CONFIG_X86_PPRO_FENCE)
111 #define __raw_spin_unlock_string \
112 "movb $1,%0" \
113 :"=m" (lock->slock) : : "memory"
116 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
117 {
118 __asm__ __volatile__(
119 __raw_spin_unlock_string
120 );
121 }
123 #else
125 #define __raw_spin_unlock_string \
126 "xchgb %b0, %1" \
127 :"=q" (oldval), "=m" (lock->slock) \
128 :"0" (oldval) : "memory"
130 static inline void __raw_spin_unlock(raw_spinlock_t *lock)
131 {
132 char oldval = 1;
134 __asm__ __volatile__(
135 __raw_spin_unlock_string
136 );
137 }
139 #endif
141 #define __raw_spin_unlock_wait(lock) \
142 do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
144 /*
145 * Read-write spinlocks, allowing multiple readers
146 * but only one writer.
147 *
148 * NOTE! it is quite common to have readers in interrupts
149 * but no interrupt writers. For those circumstances we
150 * can "mix" irq-safe locks - any writer needs to get a
151 * irq-safe write-lock, but readers can get non-irqsafe
152 * read-locks.
153 *
154 * On x86, we implement read-write locks as a 32-bit counter
155 * with the high bit (sign) being the "contended" bit.
156 *
157 * The inline assembly is non-obvious. Think about it.
158 *
159 * Changed to use the same technique as rw semaphores. See
160 * semaphore.h for details. -ben
161 *
162 * the helpers are in arch/i386/kernel/semaphore.c
163 */
165 /**
166 * read_can_lock - would read_trylock() succeed?
167 * @lock: the rwlock in question.
168 */
169 #define __raw_read_can_lock(x) ((int)(x)->lock > 0)
171 /**
172 * write_can_lock - would write_trylock() succeed?
173 * @lock: the rwlock in question.
174 */
175 #define __raw_write_can_lock(x) ((x)->lock == RW_LOCK_BIAS)
177 static inline void __raw_read_lock(raw_rwlock_t *rw)
178 {
179 __build_read_lock(rw, "__read_lock_failed");
180 }
182 static inline void __raw_write_lock(raw_rwlock_t *rw)
183 {
184 __build_write_lock(rw, "__write_lock_failed");
185 }
187 static inline int __raw_read_trylock(raw_rwlock_t *lock)
188 {
189 atomic_t *count = (atomic_t *)lock;
190 atomic_dec(count);
191 if (atomic_read(count) >= 0)
192 return 1;
193 atomic_inc(count);
194 return 0;
195 }
197 static inline int __raw_write_trylock(raw_rwlock_t *lock)
198 {
199 atomic_t *count = (atomic_t *)lock;
200 if (atomic_sub_and_test(RW_LOCK_BIAS, count))
201 return 1;
202 atomic_add(RW_LOCK_BIAS, count);
203 return 0;
204 }
206 static inline void __raw_read_unlock(raw_rwlock_t *rw)
207 {
208 asm volatile(LOCK "incl %0" :"=m" (rw->lock) : : "memory");
209 }
211 static inline void __raw_write_unlock(raw_rwlock_t *rw)
212 {
213 asm volatile(LOCK "addl $" RW_LOCK_BIAS_STR ", %0"
214 : "=m" (rw->lock) : : "memory");
215 }
217 #endif /* __ASM_SPINLOCK_H */