ia64/xen-unstable

view tools/ioemu/hw/pass-through.h @ 18003:79978fcf8797

ioemu: pass-through: XC_PAGE_SIZE should be used

Signed-off-by: KUWAMURA Shin'ya <kuwa@jp.fujitsu.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Jul 09 10:39:42 2008 +0100 (2008-07-09)
parents 9cf72db44ee9
children 8c8505e8e4e3
line source
1 /*
2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 */
18 #ifndef __PASSTHROUGH_H__
19 #define __PASSTHROUGH_H__
21 #include "vl.h"
22 #include "pci/header.h"
23 #include "pci/pci.h"
24 #include "audio/sys-queue.h"
26 /* Log acesss */
27 #define PT_LOGGING_ENABLED
29 #ifdef PT_LOGGING_ENABLED
30 #define PT_LOG(_f, _a...) fprintf(logfile, "%s: " _f, __func__, ##_a)
31 #else
32 #define PT_LOG(_f, _a...)
33 #endif
35 /* Some compilation flags */
36 // #define PT_DEBUG_PCI_CONFIG_ACCESS
38 #define PT_MACHINE_IRQ_AUTO (0xFFFFFFFF)
39 #define PT_VIRT_DEVFN_AUTO (-1)
41 /* Misc PCI constants that should be moved to a separate library :) */
42 #define PCI_CONFIG_SIZE (256)
43 #define PCI_EXP_DEVCAP_FLR (1 << 28)
44 #define PCI_EXP_DEVCTL_FLR (1 << 15)
45 #define PCI_BAR_ENTRIES (6)
47 /* because the current version of libpci (2.2.0) doesn't define these ID,
48 * so we define Capability ID here.
49 */
50 /* SHPC Capability List Item reg group */
51 #define PCI_CAP_ID_HOTPLUG 0x0C
52 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
53 #define PCI_CAP_ID_SSVID 0x0D
54 /* interrupt masking & reporting supported */
55 #define PCI_MSI_FLAGS_MASK_BIT 0x0100
57 #define PT_INVALID_REG 0xFFFFFFFF /* invalid register value */
58 #define PT_BAR_ALLF 0xFFFFFFFF /* BAR ALLF value */
59 #define PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */
60 #define PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */
61 #define PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
62 #define PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
63 enum {
64 PT_BAR_FLAG_MEM = 0, /* Memory type BAR */
65 PT_BAR_FLAG_IO, /* I/O type BAR */
66 PT_BAR_FLAG_UPPER, /* upper 64bit BAR */
67 PT_BAR_FLAG_UNUSED, /* unused BAR */
68 };
69 enum {
70 GRP_TYPE_HARDWIRED = 0, /* 0 Hardwired reg group */
71 GRP_TYPE_EMU, /* emul reg group */
72 };
74 #define PT_GET_EMUL_SIZE(flag, r_size) do { \
75 if (flag == PT_BAR_FLAG_MEM) {\
76 r_size = (((r_size) + XC_PAGE_SIZE - 1) & ~(XC_PAGE_SIZE - 1)); \
77 }\
78 } while(0)
81 struct pt_region {
82 /* Virtual phys base & size */
83 uint32_t e_physbase;
84 uint32_t e_size;
85 /* Index of region in qemu */
86 uint32_t memory_index;
87 /* BAR flag */
88 uint32_t bar_flag;
89 /* Translation of the emulated address */
90 union {
91 uint64_t maddr;
92 uint64_t pio_base;
93 uint64_t u;
94 } access;
95 };
97 struct pt_msi_info {
98 uint32_t flags;
99 int pirq; /* guest pirq corresponding */
100 uint32_t addr_lo; /* guest message address */
101 uint32_t addr_hi; /* guest message upper address */
102 uint16_t data; /* guest message data */
103 };
105 struct msix_entry_info {
106 int pirq; /* -1 means unmapped */
107 int flags; /* flags indicting whether MSI ADDR or DATA is updated */
108 uint32_t io_mem[4];
109 };
111 struct pt_msix_info {
112 int enabled;
113 int total_entries;
114 int bar_index;
115 uint32_t table_off;
116 uint64_t mmio_base_addr;
117 int mmio_index;
118 int fd;
119 void *phys_iomem_base;
120 struct msix_entry_info msix_entry[0];
121 };
123 /*
124 This structure holds the context of the mapping functions
125 and data that is relevant for qemu device management.
126 */
127 struct pt_dev {
128 PCIDevice dev;
129 struct pci_dev *pci_dev; /* libpci struct */
130 struct pt_region bases[PCI_NUM_REGIONS]; /* Access regions */
131 QEMU_LIST_HEAD (reg_grp_tbl_listhead, pt_reg_grp_tbl) reg_grp_tbl_head;
132 /* emul reg group list */
133 struct pt_msi_info *msi; /* MSI virtualization */
134 struct pt_msix_info *msix; /* MSI-X virtualization */
135 };
137 /* Used for formatting PCI BDF into cf8 format */
138 struct pci_config_cf8 {
139 union {
140 unsigned int value;
141 struct {
142 unsigned int reserved1:2;
143 unsigned int reg:6;
144 unsigned int func:3;
145 unsigned int dev:5;
146 unsigned int bus:8;
147 unsigned int reserved2:7;
148 unsigned int enable:1;
149 };
150 };
151 };
153 int pt_init(PCIBus * e_bus, char * direct_pci);
155 /* emul reg group management table */
156 struct pt_reg_grp_tbl {
157 /* emul reg group list */
158 QEMU_LIST_ENTRY (pt_reg_grp_tbl) entries;
159 /* emul reg group info table */
160 struct pt_reg_grp_info_tbl *reg_grp;
161 /* emul reg group base offset */
162 uint32_t base_offset;
163 /* emul reg group size */
164 uint8_t size;
165 /* emul reg management table list */
166 QEMU_LIST_HEAD (reg_tbl_listhead, pt_reg_tbl) reg_tbl_head;
167 };
169 /* emul reg group size initialize method */
170 typedef uint8_t (*pt_reg_size_init) (struct pt_dev *ptdev,
171 struct pt_reg_grp_info_tbl *grp_reg,
172 uint32_t base_offset);
173 /* emul reg group infomation table */
174 struct pt_reg_grp_info_tbl {
175 /* emul reg group ID */
176 uint8_t grp_id;
177 /* emul reg group type */
178 uint8_t grp_type;
179 /* emul reg group size */
180 uint8_t grp_size;
181 /* emul reg get size method */
182 pt_reg_size_init size_init;
183 /* emul reg info table */
184 struct pt_reg_info_tbl *emu_reg_tbl;
185 };
187 /* emul reg management table */
188 struct pt_reg_tbl {
189 /* emul reg table list */
190 QEMU_LIST_ENTRY (pt_reg_tbl) entries;
191 /* emul reg info table */
192 struct pt_reg_info_tbl *reg;
193 /* emul reg value */
194 uint32_t data;
195 };
197 /* emul reg initialize method */
198 typedef uint32_t (*conf_reg_init) (struct pt_dev *ptdev,
199 struct pt_reg_info_tbl *reg,
200 uint32_t real_offset);
201 /* emul reg long write method */
202 typedef int (*conf_dword_write) (struct pt_dev *ptdev,
203 struct pt_reg_tbl *cfg_entry,
204 uint32_t *value,
205 uint32_t dev_value,
206 uint32_t valid_mask);
207 /* emul reg word write method */
208 typedef int (*conf_word_write) (struct pt_dev *ptdev,
209 struct pt_reg_tbl *cfg_entry,
210 uint16_t *value,
211 uint16_t dev_value,
212 uint16_t valid_mask);
213 /* emul reg byte write method */
214 typedef int (*conf_byte_write) (struct pt_dev *ptdev,
215 struct pt_reg_tbl *cfg_entry,
216 uint8_t *value,
217 uint8_t dev_value,
218 uint8_t valid_mask);
219 /* emul reg long read methods */
220 typedef int (*conf_dword_read) (struct pt_dev *ptdev,
221 struct pt_reg_tbl *cfg_entry,
222 uint32_t *value,
223 uint32_t valid_mask);
224 /* emul reg word read method */
225 typedef int (*conf_word_read) (struct pt_dev *ptdev,
226 struct pt_reg_tbl *cfg_entry,
227 uint16_t *value,
228 uint16_t valid_mask);
229 /* emul reg byte read method */
230 typedef int (*conf_byte_read) (struct pt_dev *ptdev,
231 struct pt_reg_tbl *cfg_entry,
232 uint8_t *value,
233 uint8_t valid_mask);
235 /* emul reg infomation table */
236 struct pt_reg_info_tbl {
237 /* reg relative offset */
238 uint32_t offset;
239 /* reg size */
240 uint32_t size;
241 /* reg initial value */
242 uint32_t init_val;
243 /* reg read only field mask (ON:RO/ROS, OFF:other) */
244 uint32_t ro_mask;
245 /* reg emulate field mask (ON:emu, OFF:passthrough) */
246 uint32_t emu_mask;
247 /* emul reg initialize method */
248 conf_reg_init init;
249 union {
250 struct {
251 /* emul reg long write method */
252 conf_dword_write write;
253 /* emul reg long read method */
254 conf_dword_read read;
255 } dw;
256 struct {
257 /* emul reg word write method */
258 conf_word_write write;
259 /* emul reg word read method */
260 conf_word_read read;
261 } w;
262 struct {
263 /* emul reg byte write method */
264 conf_byte_write write;
265 /* emul reg byte read method */
266 conf_byte_read read;
267 } b;
268 } u;
269 };
271 #endif /* __PASSTHROUGH_H__ */