ia64/xen-unstable

view xen/include/asm-x86/io_apic.h @ 19800:78962f85c562

IOMMU: Add two generic functions to vendor neutral interface

Add 2 generic functions into the vendor neutral iommu interface, The
reason is that from changeset 19732, there is only one global flag
"iommu_enabled" that controls iommu enablement for both vtd and amd
systems, so we need different code paths for vtd and amd iommu systems
if this flag has been turned on. Also, the early checking of
"iommu_enabled" in iommu_setup() is removed to prevent iommu
functionalities from been disabled on amd systems.

Signed-off-by: Wei Wang <wei.wang2@amd.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Jun 19 08:41:50 2009 +0100 (2009-06-19)
parents 6705898f768d
children
line source
1 #ifndef __ASM_IO_APIC_H
2 #define __ASM_IO_APIC_H
4 #include <xen/config.h>
5 #include <asm/types.h>
6 #include <asm/mpspec.h>
7 #include <asm/apicdef.h>
8 #include <asm/fixmap.h>
9 #include <xen/iommu.h>
11 /*
12 * Intel IO-APIC support for SMP and UP systems.
13 *
14 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
15 */
17 #ifdef CONFIG_X86_IO_APIC
19 #define IO_APIC_BASE(idx) \
20 ((volatile int *)(__fix_to_virt(FIX_IO_APIC_BASE_0 + idx) \
21 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK)))
23 #define IO_APIC_ID(idx) (mp_ioapics[idx].mpc_apicid)
25 /*
26 * The structure of the IO-APIC:
27 */
28 union IO_APIC_reg_00 {
29 u32 raw;
30 struct {
31 u32 __reserved_2 : 14,
32 LTS : 1,
33 delivery_type : 1,
34 __reserved_1 : 8,
35 ID : 8;
36 } __attribute__ ((packed)) bits;
37 };
39 union IO_APIC_reg_01 {
40 u32 raw;
41 struct {
42 u32 version : 8,
43 __reserved_2 : 7,
44 PRQ : 1,
45 entries : 8,
46 __reserved_1 : 8;
47 } __attribute__ ((packed)) bits;
48 };
50 union IO_APIC_reg_02 {
51 u32 raw;
52 struct {
53 u32 __reserved_2 : 24,
54 arbitration : 4,
55 __reserved_1 : 4;
56 } __attribute__ ((packed)) bits;
57 };
59 union IO_APIC_reg_03 {
60 u32 raw;
61 struct {
62 u32 boot_DT : 1,
63 __reserved_1 : 31;
64 } __attribute__ ((packed)) bits;
65 };
67 /*
68 * # of IO-APICs and # of IRQ routing registers
69 */
70 extern int nr_ioapics;
71 extern int nr_ioapic_registers[MAX_IO_APICS];
73 enum ioapic_irq_destination_types {
74 dest_Fixed = 0,
75 dest_LowestPrio = 1,
76 dest_SMI = 2,
77 dest__reserved_1 = 3,
78 dest_NMI = 4,
79 dest_INIT = 5,
80 dest__reserved_2 = 6,
81 dest_ExtINT = 7
82 };
84 struct IO_APIC_route_entry {
85 __u32 vector : 8,
86 delivery_mode : 3, /* 000: FIXED
87 * 001: lowest prio
88 * 111: ExtINT
89 */
90 dest_mode : 1, /* 0: physical, 1: logical */
91 delivery_status : 1,
92 polarity : 1,
93 irr : 1,
94 trigger : 1, /* 0: edge, 1: level */
95 mask : 1, /* 0: enabled, 1: disabled */
96 __reserved_2 : 15;
98 union { struct { __u32
99 __reserved_1 : 24,
100 physical_dest : 4,
101 __reserved_2 : 4;
102 } physical;
104 struct { __u32
105 __reserved_1 : 24,
106 logical_dest : 8;
107 } logical;
108 } dest;
110 } __attribute__ ((packed));
112 /*
113 * MP-BIOS irq configuration table structures:
114 */
116 /* I/O APIC entries */
117 extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
119 /* # of MP IRQ source entries */
120 extern int mp_irq_entries;
122 /* MP IRQ source entries */
123 extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
125 /* non-0 if default (table-less) MP configuration */
126 extern int mpc_default_type;
128 /* Only need to remap ioapic RTE (reg: 10~3Fh) */
129 #define ioapic_reg_remapped(reg) (iommu_enabled && ((reg) >= 0x10))
131 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
132 {
133 if (ioapic_reg_remapped(reg))
134 return iommu_read_apic_from_ire(apic, reg);
135 *IO_APIC_BASE(apic) = reg;
136 return *(IO_APIC_BASE(apic)+4);
137 }
139 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
140 {
141 if (ioapic_reg_remapped(reg))
142 return iommu_update_ire_from_apic(apic, reg, value);
143 *IO_APIC_BASE(apic) = reg;
144 *(IO_APIC_BASE(apic)+4) = value;
145 }
147 /*
148 * Re-write a value: to be used for read-modify-write
149 * cycles where the read already set up the index register.
150 *
151 * Older SiS APIC requires we rewrite the index regiser
152 */
153 #ifdef __i386__
154 extern int sis_apic_bug;
155 #else
156 #define sis_apic_bug 0
157 #endif
158 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
159 {
160 if (ioapic_reg_remapped(reg))
161 return iommu_update_ire_from_apic(apic, reg, value);
162 if (sis_apic_bug)
163 *IO_APIC_BASE(apic) = reg;
164 *(IO_APIC_BASE(apic)+4) = value;
165 }
167 /* 1 if "noapic" boot option passed */
168 extern int skip_ioapic_setup;
170 #ifdef CONFIG_ACPI_BOOT
171 extern int io_apic_get_unique_id (int ioapic, int apic_id);
172 extern int io_apic_get_version (int ioapic);
173 extern int io_apic_get_redir_entries (int ioapic);
174 extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low);
175 extern int timer_uses_ioapic_pin_0;
176 #endif /*CONFIG_ACPI_BOOT*/
178 extern void init_ioapic_mappings(void);
180 extern int (*ioapic_renumber_irq)(int ioapic, int irq);
181 extern void ioapic_suspend(void);
182 extern void ioapic_resume(void);
184 #else /* !CONFIG_X86_IO_APIC */
185 static inline void init_ioapic_mappings(void) {}
186 static inline void ioapic_suspend(void) {}
187 static inline void ioapic_resume(void) {}
188 #endif
190 extern int assign_irq_vector(int irq);
191 extern int free_irq_vector(int vector);
193 #endif