ia64/xen-unstable

view xen/arch/x86/hvm/hvm.c @ 19764:775afcdc2759

x86, hvm: fix a domain_lock leak
Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Jun 16 13:33:12 2009 +0100 (2009-06-16)
parents 43833a6d50a5
children f2a3b7188906
line source
1 /*
2 * hvm.c: Common hardware virtual machine abstractions.
3 *
4 * Copyright (c) 2004, Intel Corporation.
5 * Copyright (c) 2005, International Business Machines Corporation.
6 * Copyright (c) 2008, Citrix Systems, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19 * Place - Suite 330, Boston, MA 02111-1307 USA.
20 */
22 #include <xen/config.h>
23 #include <xen/ctype.h>
24 #include <xen/init.h>
25 #include <xen/lib.h>
26 #include <xen/trace.h>
27 #include <xen/sched.h>
28 #include <xen/irq.h>
29 #include <xen/softirq.h>
30 #include <xen/domain.h>
31 #include <xen/domain_page.h>
32 #include <xen/hypercall.h>
33 #include <xen/guest_access.h>
34 #include <xen/event.h>
35 #include <xen/paging.h>
36 #include <asm/shadow.h>
37 #include <asm/hap.h>
38 #include <asm/current.h>
39 #include <asm/e820.h>
40 #include <asm/io.h>
41 #include <asm/regs.h>
42 #include <asm/cpufeature.h>
43 #include <asm/processor.h>
44 #include <asm/types.h>
45 #include <asm/msr.h>
46 #include <asm/mc146818rtc.h>
47 #include <asm/spinlock.h>
48 #include <asm/hvm/hvm.h>
49 #include <asm/hvm/vpt.h>
50 #include <asm/hvm/support.h>
51 #include <asm/hvm/cacheattr.h>
52 #include <asm/hvm/trace.h>
53 #include <public/sched.h>
54 #include <public/hvm/ioreq.h>
55 #include <public/version.h>
56 #include <public/memory.h>
58 int hvm_enabled __read_mostly;
60 unsigned int opt_hvm_debug_level __read_mostly;
61 integer_param("hvm_debug", opt_hvm_debug_level);
63 int opt_softtsc;
64 boolean_param("softtsc", opt_softtsc);
66 struct hvm_function_table hvm_funcs __read_mostly;
68 /* I/O permission bitmap is globally shared by all HVM guests. */
69 unsigned long __attribute__ ((__section__ (".bss.page_aligned")))
70 hvm_io_bitmap[3*PAGE_SIZE/BYTES_PER_LONG];
72 void hvm_enable(struct hvm_function_table *fns)
73 {
74 BUG_ON(hvm_enabled);
75 printk("HVM: %s enabled\n", fns->name);
77 /*
78 * Allow direct access to the PC debug ports 0x80 and 0xed (they are
79 * often used for I/O delays, but the vmexits simply slow things down).
80 */
81 memset(hvm_io_bitmap, ~0, sizeof(hvm_io_bitmap));
82 __clear_bit(0x80, hvm_io_bitmap);
83 __clear_bit(0xed, hvm_io_bitmap);
85 hvm_funcs = *fns;
86 hvm_enabled = 1;
88 if ( hvm_funcs.hap_supported )
89 printk("HVM: Hardware Assisted Paging detected.\n");
90 }
92 /*
93 * Need to re-inject a given event? We avoid re-injecting software exceptions
94 * and interrupts because the faulting/trapping instruction can simply be
95 * re-executed (neither VMX nor SVM update RIP when they VMEXIT during
96 * INT3/INTO/INTn).
97 */
98 int hvm_event_needs_reinjection(uint8_t type, uint8_t vector)
99 {
100 switch ( type )
101 {
102 case X86_EVENTTYPE_EXT_INTR:
103 case X86_EVENTTYPE_NMI:
104 return 1;
105 case X86_EVENTTYPE_HW_EXCEPTION:
106 /*
107 * SVM uses type 3 ("HW Exception") for #OF and #BP. We explicitly
108 * check for these vectors, as they are really SW Exceptions. SVM has
109 * not updated RIP to point after the trapping instruction (INT3/INTO).
110 */
111 return (vector != 3) && (vector != 4);
112 default:
113 /* Software exceptions/interrupts can be re-executed (e.g., INT n). */
114 break;
115 }
116 return 0;
117 }
119 /*
120 * Combine two hardware exceptions: @vec2 was raised during delivery of @vec1.
121 * This means we can assume that @vec2 is contributory or a page fault.
122 */
123 uint8_t hvm_combine_hw_exceptions(uint8_t vec1, uint8_t vec2)
124 {
125 /* Exception during double-fault delivery always causes a triple fault. */
126 if ( vec1 == TRAP_double_fault )
127 {
128 hvm_triple_fault();
129 return TRAP_double_fault; /* dummy return */
130 }
132 /* Exception during page-fault delivery always causes a double fault. */
133 if ( vec1 == TRAP_page_fault )
134 return TRAP_double_fault;
136 /* Discard the first exception if it's benign or if we now have a #PF. */
137 if ( !((1u << vec1) & 0x7c01u) || (vec2 == TRAP_page_fault) )
138 return vec2;
140 /* Cannot combine the exceptions: double fault. */
141 return TRAP_double_fault;
142 }
144 void hvm_set_guest_tsc(struct vcpu *v, u64 guest_tsc)
145 {
146 u64 host_tsc;
148 rdtscll(host_tsc);
150 v->arch.hvm_vcpu.cache_tsc_offset = guest_tsc - host_tsc;
151 hvm_funcs.set_tsc_offset(v, v->arch.hvm_vcpu.cache_tsc_offset);
152 }
154 u64 hvm_get_guest_tsc(struct vcpu *v)
155 {
156 u64 host_tsc;
158 if ( opt_softtsc )
159 host_tsc = hvm_get_guest_time(v);
160 else
161 rdtscll(host_tsc);
163 return host_tsc + v->arch.hvm_vcpu.cache_tsc_offset;
164 }
166 void hvm_migrate_timers(struct vcpu *v)
167 {
168 rtc_migrate_timers(v);
169 pt_migrate(v);
170 }
172 void hvm_do_resume(struct vcpu *v)
173 {
174 ioreq_t *p;
176 pt_restore_timer(v);
178 /* NB. Optimised for common case (p->state == STATE_IOREQ_NONE). */
179 p = &get_ioreq(v)->vp_ioreq;
180 while ( p->state != STATE_IOREQ_NONE )
181 {
182 switch ( p->state )
183 {
184 case STATE_IORESP_READY: /* IORESP_READY -> NONE */
185 hvm_io_assist();
186 break;
187 case STATE_IOREQ_READY: /* IOREQ_{READY,INPROCESS} -> IORESP_READY */
188 case STATE_IOREQ_INPROCESS:
189 wait_on_xen_event_channel(v->arch.hvm_vcpu.xen_port,
190 (p->state != STATE_IOREQ_READY) &&
191 (p->state != STATE_IOREQ_INPROCESS));
192 break;
193 default:
194 gdprintk(XENLOG_ERR, "Weird HVM iorequest state %d.\n", p->state);
195 domain_crash(v->domain);
196 return; /* bail */
197 }
198 }
199 }
201 static void hvm_init_ioreq_page(
202 struct domain *d, struct hvm_ioreq_page *iorp)
203 {
204 memset(iorp, 0, sizeof(*iorp));
205 spin_lock_init(&iorp->lock);
206 domain_pause(d);
207 }
209 static void hvm_destroy_ioreq_page(
210 struct domain *d, struct hvm_ioreq_page *iorp)
211 {
212 spin_lock(&iorp->lock);
214 ASSERT(d->is_dying);
216 if ( iorp->va != NULL )
217 {
218 unmap_domain_page_global(iorp->va);
219 put_page_and_type(iorp->page);
220 iorp->va = NULL;
221 }
223 spin_unlock(&iorp->lock);
224 }
226 static int hvm_set_ioreq_page(
227 struct domain *d, struct hvm_ioreq_page *iorp, unsigned long gmfn)
228 {
229 struct page_info *page;
230 p2m_type_t p2mt;
231 unsigned long mfn;
232 void *va;
234 mfn = mfn_x(gfn_to_mfn(d, gmfn, &p2mt));
235 if ( !p2m_is_ram(p2mt) )
236 return -EINVAL;
237 ASSERT(mfn_valid(mfn));
239 page = mfn_to_page(mfn);
240 if ( !get_page_and_type(page, d, PGT_writable_page) )
241 return -EINVAL;
243 va = map_domain_page_global(mfn);
244 if ( va == NULL )
245 {
246 put_page_and_type(page);
247 return -ENOMEM;
248 }
250 spin_lock(&iorp->lock);
252 if ( (iorp->va != NULL) || d->is_dying )
253 {
254 spin_unlock(&iorp->lock);
255 unmap_domain_page_global(va);
256 put_page_and_type(mfn_to_page(mfn));
257 return -EINVAL;
258 }
260 iorp->va = va;
261 iorp->page = page;
263 spin_unlock(&iorp->lock);
265 domain_unpause(d);
267 return 0;
268 }
270 static int hvm_print_line(
271 int dir, uint32_t port, uint32_t bytes, uint32_t *val)
272 {
273 struct vcpu *curr = current;
274 struct hvm_domain *hd = &curr->domain->arch.hvm_domain;
275 char c = *val;
277 BUG_ON(bytes != 1);
279 /* Accept only printable characters, newline, and horizontal tab. */
280 if ( !isprint(c) && (c != '\n') && (c != '\t') )
281 return X86EMUL_OKAY;
283 spin_lock(&hd->pbuf_lock);
284 hd->pbuf[hd->pbuf_idx++] = c;
285 if ( (hd->pbuf_idx == (sizeof(hd->pbuf) - 2)) || (c == '\n') )
286 {
287 if ( c != '\n' )
288 hd->pbuf[hd->pbuf_idx++] = '\n';
289 hd->pbuf[hd->pbuf_idx] = '\0';
290 printk(XENLOG_G_DEBUG "HVM%u: %s", curr->domain->domain_id, hd->pbuf);
291 hd->pbuf_idx = 0;
292 }
293 spin_unlock(&hd->pbuf_lock);
295 return X86EMUL_OKAY;
296 }
298 int hvm_domain_initialise(struct domain *d)
299 {
300 int rc;
302 if ( !hvm_enabled )
303 {
304 gdprintk(XENLOG_WARNING, "Attempt to create a HVM guest "
305 "on a non-VT/AMDV platform.\n");
306 return -EINVAL;
307 }
309 spin_lock_init(&d->arch.hvm_domain.pbuf_lock);
310 spin_lock_init(&d->arch.hvm_domain.irq_lock);
311 spin_lock_init(&d->arch.hvm_domain.uc_lock);
313 INIT_LIST_HEAD(&d->arch.hvm_domain.msixtbl_list);
314 spin_lock_init(&d->arch.hvm_domain.msixtbl_list_lock);
316 hvm_init_guest_time(d);
318 d->arch.hvm_domain.params[HVM_PARAM_HPET_ENABLED] = 1;
320 hvm_init_cacheattr_region_list(d);
322 rc = paging_enable(d, PG_refcounts|PG_translate|PG_external);
323 if ( rc != 0 )
324 goto fail1;
326 vpic_init(d);
328 rc = vioapic_init(d);
329 if ( rc != 0 )
330 goto fail1;
332 stdvga_init(d);
334 rtc_init(d);
336 hvm_init_ioreq_page(d, &d->arch.hvm_domain.ioreq);
337 hvm_init_ioreq_page(d, &d->arch.hvm_domain.buf_ioreq);
339 register_portio_handler(d, 0xe9, 1, hvm_print_line);
341 rc = hvm_funcs.domain_initialise(d);
342 if ( rc != 0 )
343 goto fail2;
345 return 0;
347 fail2:
348 rtc_deinit(d);
349 stdvga_deinit(d);
350 vioapic_deinit(d);
351 fail1:
352 hvm_destroy_cacheattr_region_list(d);
353 return rc;
354 }
356 extern void msixtbl_pt_cleanup(struct domain *d);
358 void hvm_domain_relinquish_resources(struct domain *d)
359 {
360 hvm_destroy_ioreq_page(d, &d->arch.hvm_domain.ioreq);
361 hvm_destroy_ioreq_page(d, &d->arch.hvm_domain.buf_ioreq);
363 msixtbl_pt_cleanup(d);
365 /* Stop all asynchronous timer actions. */
366 rtc_deinit(d);
367 if ( d->vcpu[0] != NULL )
368 {
369 pit_deinit(d);
370 pmtimer_deinit(d);
371 hpet_deinit(d);
372 }
373 }
375 void hvm_domain_destroy(struct domain *d)
376 {
377 hvm_funcs.domain_destroy(d);
378 rtc_deinit(d);
379 stdvga_deinit(d);
380 vioapic_deinit(d);
381 hvm_destroy_cacheattr_region_list(d);
382 }
384 static int hvm_save_cpu_ctxt(struct domain *d, hvm_domain_context_t *h)
385 {
386 struct vcpu *v;
387 struct hvm_hw_cpu ctxt;
388 struct segment_register seg;
389 struct vcpu_guest_context *vc;
391 for_each_vcpu ( d, v )
392 {
393 /* We don't need to save state for a vcpu that is down; the restore
394 * code will leave it down if there is nothing saved. */
395 if ( test_bit(_VPF_down, &v->pause_flags) )
396 continue;
398 /* Architecture-specific vmcs/vmcb bits */
399 hvm_funcs.save_cpu_ctxt(v, &ctxt);
401 hvm_get_segment_register(v, x86_seg_idtr, &seg);
402 ctxt.idtr_limit = seg.limit;
403 ctxt.idtr_base = seg.base;
405 hvm_get_segment_register(v, x86_seg_gdtr, &seg);
406 ctxt.gdtr_limit = seg.limit;
407 ctxt.gdtr_base = seg.base;
409 hvm_get_segment_register(v, x86_seg_cs, &seg);
410 ctxt.cs_sel = seg.sel;
411 ctxt.cs_limit = seg.limit;
412 ctxt.cs_base = seg.base;
413 ctxt.cs_arbytes = seg.attr.bytes;
415 hvm_get_segment_register(v, x86_seg_ds, &seg);
416 ctxt.ds_sel = seg.sel;
417 ctxt.ds_limit = seg.limit;
418 ctxt.ds_base = seg.base;
419 ctxt.ds_arbytes = seg.attr.bytes;
421 hvm_get_segment_register(v, x86_seg_es, &seg);
422 ctxt.es_sel = seg.sel;
423 ctxt.es_limit = seg.limit;
424 ctxt.es_base = seg.base;
425 ctxt.es_arbytes = seg.attr.bytes;
427 hvm_get_segment_register(v, x86_seg_ss, &seg);
428 ctxt.ss_sel = seg.sel;
429 ctxt.ss_limit = seg.limit;
430 ctxt.ss_base = seg.base;
431 ctxt.ss_arbytes = seg.attr.bytes;
433 hvm_get_segment_register(v, x86_seg_fs, &seg);
434 ctxt.fs_sel = seg.sel;
435 ctxt.fs_limit = seg.limit;
436 ctxt.fs_base = seg.base;
437 ctxt.fs_arbytes = seg.attr.bytes;
439 hvm_get_segment_register(v, x86_seg_gs, &seg);
440 ctxt.gs_sel = seg.sel;
441 ctxt.gs_limit = seg.limit;
442 ctxt.gs_base = seg.base;
443 ctxt.gs_arbytes = seg.attr.bytes;
445 hvm_get_segment_register(v, x86_seg_tr, &seg);
446 ctxt.tr_sel = seg.sel;
447 ctxt.tr_limit = seg.limit;
448 ctxt.tr_base = seg.base;
449 ctxt.tr_arbytes = seg.attr.bytes;
451 hvm_get_segment_register(v, x86_seg_ldtr, &seg);
452 ctxt.ldtr_sel = seg.sel;
453 ctxt.ldtr_limit = seg.limit;
454 ctxt.ldtr_base = seg.base;
455 ctxt.ldtr_arbytes = seg.attr.bytes;
457 vc = &v->arch.guest_context;
459 if ( v->fpu_initialised )
460 memcpy(ctxt.fpu_regs, &vc->fpu_ctxt, sizeof(ctxt.fpu_regs));
461 else
462 memset(ctxt.fpu_regs, 0, sizeof(ctxt.fpu_regs));
464 ctxt.rax = vc->user_regs.eax;
465 ctxt.rbx = vc->user_regs.ebx;
466 ctxt.rcx = vc->user_regs.ecx;
467 ctxt.rdx = vc->user_regs.edx;
468 ctxt.rbp = vc->user_regs.ebp;
469 ctxt.rsi = vc->user_regs.esi;
470 ctxt.rdi = vc->user_regs.edi;
471 ctxt.rsp = vc->user_regs.esp;
472 ctxt.rip = vc->user_regs.eip;
473 ctxt.rflags = vc->user_regs.eflags;
474 #ifdef __x86_64__
475 ctxt.r8 = vc->user_regs.r8;
476 ctxt.r9 = vc->user_regs.r9;
477 ctxt.r10 = vc->user_regs.r10;
478 ctxt.r11 = vc->user_regs.r11;
479 ctxt.r12 = vc->user_regs.r12;
480 ctxt.r13 = vc->user_regs.r13;
481 ctxt.r14 = vc->user_regs.r14;
482 ctxt.r15 = vc->user_regs.r15;
483 #endif
484 ctxt.dr0 = vc->debugreg[0];
485 ctxt.dr1 = vc->debugreg[1];
486 ctxt.dr2 = vc->debugreg[2];
487 ctxt.dr3 = vc->debugreg[3];
488 ctxt.dr6 = vc->debugreg[6];
489 ctxt.dr7 = vc->debugreg[7];
491 if ( hvm_save_entry(CPU, v->vcpu_id, h, &ctxt) != 0 )
492 return 1;
493 }
494 return 0;
495 }
497 static int hvm_load_cpu_ctxt(struct domain *d, hvm_domain_context_t *h)
498 {
499 int vcpuid, rc;
500 struct vcpu *v;
501 struct hvm_hw_cpu ctxt;
502 struct segment_register seg;
503 struct vcpu_guest_context *vc;
505 /* Which vcpu is this? */
506 vcpuid = hvm_load_instance(h);
507 if ( vcpuid >= MAX_VIRT_CPUS || (v = d->vcpu[vcpuid]) == NULL )
508 {
509 gdprintk(XENLOG_ERR, "HVM restore: domain has no vcpu %u\n", vcpuid);
510 return -EINVAL;
511 }
512 vc = &v->arch.guest_context;
514 /* Need to init this vcpu before loading its contents */
515 rc = 0;
516 domain_lock(d);
517 if ( !v->is_initialised )
518 rc = boot_vcpu(d, vcpuid, vc);
519 domain_unlock(d);
520 if ( rc != 0 )
521 return rc;
523 if ( hvm_load_entry(CPU, h, &ctxt) != 0 )
524 return -EINVAL;
526 /* Sanity check some control registers. */
527 if ( (ctxt.cr0 & HVM_CR0_GUEST_RESERVED_BITS) ||
528 !(ctxt.cr0 & X86_CR0_ET) ||
529 ((ctxt.cr0 & (X86_CR0_PE|X86_CR0_PG)) == X86_CR0_PG) )
530 {
531 gdprintk(XENLOG_ERR, "HVM restore: bad CR0 0x%"PRIx64"\n",
532 ctxt.cr0);
533 return -EINVAL;
534 }
536 if ( ctxt.cr4 & HVM_CR4_GUEST_RESERVED_BITS )
537 {
538 gdprintk(XENLOG_ERR, "HVM restore: bad CR4 0x%"PRIx64"\n",
539 ctxt.cr4);
540 return -EINVAL;
541 }
543 if ( (ctxt.msr_efer & ~(EFER_FFXSE | EFER_LME | EFER_LMA |
544 EFER_NX | EFER_SCE)) ||
545 ((sizeof(long) != 8) && (ctxt.msr_efer & EFER_LME)) ||
546 (!cpu_has_nx && (ctxt.msr_efer & EFER_NX)) ||
547 (!cpu_has_syscall && (ctxt.msr_efer & EFER_SCE)) ||
548 (!cpu_has_ffxsr && (ctxt.msr_efer & EFER_FFXSE)) ||
549 ((ctxt.msr_efer & (EFER_LME|EFER_LMA)) == EFER_LMA) )
550 {
551 gdprintk(XENLOG_ERR, "HVM restore: bad EFER 0x%"PRIx64"\n",
552 ctxt.msr_efer);
553 return -EINVAL;
554 }
556 /* Older Xen versions used to save the segment arbytes directly
557 * from the VMCS on Intel hosts. Detect this and rearrange them
558 * into the struct segment_register format. */
559 #define UNFOLD_ARBYTES(_r) \
560 if ( (_r & 0xf000) && !(_r & 0x0f00) ) \
561 _r = ((_r & 0xff) | ((_r >> 4) & 0xf00))
562 UNFOLD_ARBYTES(ctxt.cs_arbytes);
563 UNFOLD_ARBYTES(ctxt.ds_arbytes);
564 UNFOLD_ARBYTES(ctxt.es_arbytes);
565 UNFOLD_ARBYTES(ctxt.fs_arbytes);
566 UNFOLD_ARBYTES(ctxt.gs_arbytes);
567 UNFOLD_ARBYTES(ctxt.ss_arbytes);
568 UNFOLD_ARBYTES(ctxt.tr_arbytes);
569 UNFOLD_ARBYTES(ctxt.ldtr_arbytes);
570 #undef UNFOLD_ARBYTES
572 /* Architecture-specific vmcs/vmcb bits */
573 if ( hvm_funcs.load_cpu_ctxt(v, &ctxt) < 0 )
574 return -EINVAL;
576 seg.limit = ctxt.idtr_limit;
577 seg.base = ctxt.idtr_base;
578 hvm_set_segment_register(v, x86_seg_idtr, &seg);
580 seg.limit = ctxt.gdtr_limit;
581 seg.base = ctxt.gdtr_base;
582 hvm_set_segment_register(v, x86_seg_gdtr, &seg);
584 seg.sel = ctxt.cs_sel;
585 seg.limit = ctxt.cs_limit;
586 seg.base = ctxt.cs_base;
587 seg.attr.bytes = ctxt.cs_arbytes;
588 hvm_set_segment_register(v, x86_seg_cs, &seg);
590 seg.sel = ctxt.ds_sel;
591 seg.limit = ctxt.ds_limit;
592 seg.base = ctxt.ds_base;
593 seg.attr.bytes = ctxt.ds_arbytes;
594 hvm_set_segment_register(v, x86_seg_ds, &seg);
596 seg.sel = ctxt.es_sel;
597 seg.limit = ctxt.es_limit;
598 seg.base = ctxt.es_base;
599 seg.attr.bytes = ctxt.es_arbytes;
600 hvm_set_segment_register(v, x86_seg_es, &seg);
602 seg.sel = ctxt.ss_sel;
603 seg.limit = ctxt.ss_limit;
604 seg.base = ctxt.ss_base;
605 seg.attr.bytes = ctxt.ss_arbytes;
606 hvm_set_segment_register(v, x86_seg_ss, &seg);
608 seg.sel = ctxt.fs_sel;
609 seg.limit = ctxt.fs_limit;
610 seg.base = ctxt.fs_base;
611 seg.attr.bytes = ctxt.fs_arbytes;
612 hvm_set_segment_register(v, x86_seg_fs, &seg);
614 seg.sel = ctxt.gs_sel;
615 seg.limit = ctxt.gs_limit;
616 seg.base = ctxt.gs_base;
617 seg.attr.bytes = ctxt.gs_arbytes;
618 hvm_set_segment_register(v, x86_seg_gs, &seg);
620 seg.sel = ctxt.tr_sel;
621 seg.limit = ctxt.tr_limit;
622 seg.base = ctxt.tr_base;
623 seg.attr.bytes = ctxt.tr_arbytes;
624 hvm_set_segment_register(v, x86_seg_tr, &seg);
626 seg.sel = ctxt.ldtr_sel;
627 seg.limit = ctxt.ldtr_limit;
628 seg.base = ctxt.ldtr_base;
629 seg.attr.bytes = ctxt.ldtr_arbytes;
630 hvm_set_segment_register(v, x86_seg_ldtr, &seg);
632 memcpy(&vc->fpu_ctxt, ctxt.fpu_regs, sizeof(ctxt.fpu_regs));
634 vc->user_regs.eax = ctxt.rax;
635 vc->user_regs.ebx = ctxt.rbx;
636 vc->user_regs.ecx = ctxt.rcx;
637 vc->user_regs.edx = ctxt.rdx;
638 vc->user_regs.ebp = ctxt.rbp;
639 vc->user_regs.esi = ctxt.rsi;
640 vc->user_regs.edi = ctxt.rdi;
641 vc->user_regs.esp = ctxt.rsp;
642 vc->user_regs.eip = ctxt.rip;
643 vc->user_regs.eflags = ctxt.rflags | 2;
644 #ifdef __x86_64__
645 vc->user_regs.r8 = ctxt.r8;
646 vc->user_regs.r9 = ctxt.r9;
647 vc->user_regs.r10 = ctxt.r10;
648 vc->user_regs.r11 = ctxt.r11;
649 vc->user_regs.r12 = ctxt.r12;
650 vc->user_regs.r13 = ctxt.r13;
651 vc->user_regs.r14 = ctxt.r14;
652 vc->user_regs.r15 = ctxt.r15;
653 #endif
654 vc->debugreg[0] = ctxt.dr0;
655 vc->debugreg[1] = ctxt.dr1;
656 vc->debugreg[2] = ctxt.dr2;
657 vc->debugreg[3] = ctxt.dr3;
658 vc->debugreg[6] = ctxt.dr6;
659 vc->debugreg[7] = ctxt.dr7;
661 vc->flags = VGCF_online;
662 v->fpu_initialised = 1;
664 /* Auxiliary processors should be woken immediately. */
665 if ( test_and_clear_bit(_VPF_down, &v->pause_flags) )
666 vcpu_wake(v);
668 return 0;
669 }
671 HVM_REGISTER_SAVE_RESTORE(CPU, hvm_save_cpu_ctxt, hvm_load_cpu_ctxt,
672 1, HVMSR_PER_VCPU);
674 int hvm_vcpu_initialise(struct vcpu *v)
675 {
676 int rc;
678 if ( (rc = vlapic_init(v)) != 0 )
679 goto fail1;
681 if ( (rc = hvm_funcs.vcpu_initialise(v)) != 0 )
682 goto fail2;
684 /* Create ioreq event channel. */
685 rc = alloc_unbound_xen_event_channel(v, 0);
686 if ( rc < 0 )
687 goto fail3;
689 /* Register ioreq event channel. */
690 v->arch.hvm_vcpu.xen_port = rc;
691 spin_lock(&v->domain->arch.hvm_domain.ioreq.lock);
692 if ( v->domain->arch.hvm_domain.ioreq.va != NULL )
693 get_ioreq(v)->vp_eport = v->arch.hvm_vcpu.xen_port;
694 spin_unlock(&v->domain->arch.hvm_domain.ioreq.lock);
696 spin_lock_init(&v->arch.hvm_vcpu.tm_lock);
697 INIT_LIST_HEAD(&v->arch.hvm_vcpu.tm_list);
699 rc = hvm_vcpu_cacheattr_init(v);
700 if ( rc != 0 )
701 goto fail3;
703 tasklet_init(&v->arch.hvm_vcpu.assert_evtchn_irq_tasklet,
704 (void(*)(unsigned long))hvm_assert_evtchn_irq,
705 (unsigned long)v);
707 v->arch.guest_context.user_regs.eflags = 2;
709 if ( v->vcpu_id == 0 )
710 {
711 /* NB. All these really belong in hvm_domain_initialise(). */
712 pit_init(v, cpu_khz);
713 pmtimer_init(v);
714 hpet_init(v);
716 /* Init guest TSC to start from zero. */
717 hvm_set_guest_tsc(v, 0);
719 /* Can start up without SIPI-SIPI or setvcpucontext domctl. */
720 v->is_initialised = 1;
721 clear_bit(_VPF_down, &v->pause_flags);
722 }
724 return 0;
726 fail3:
727 hvm_funcs.vcpu_destroy(v);
728 fail2:
729 vlapic_destroy(v);
730 fail1:
731 return rc;
732 }
734 void hvm_vcpu_destroy(struct vcpu *v)
735 {
736 tasklet_kill(&v->arch.hvm_vcpu.assert_evtchn_irq_tasklet);
737 hvm_vcpu_cacheattr_destroy(v);
738 vlapic_destroy(v);
739 hvm_funcs.vcpu_destroy(v);
741 /* Event channel is already freed by evtchn_destroy(). */
742 /*free_xen_event_channel(v, v->arch.hvm_vcpu.xen_port);*/
743 }
745 void hvm_vcpu_down(struct vcpu *v)
746 {
747 struct domain *d = v->domain;
748 int online_count = 0;
750 /* Doesn't halt us immediately, but we'll never return to guest context. */
751 set_bit(_VPF_down, &v->pause_flags);
752 vcpu_sleep_nosync(v);
754 /* Any other VCPUs online? ... */
755 domain_lock(d);
756 for_each_vcpu ( d, v )
757 if ( !test_bit(_VPF_down, &v->pause_flags) )
758 online_count++;
759 domain_unlock(d);
761 /* ... Shut down the domain if not. */
762 if ( online_count == 0 )
763 {
764 gdprintk(XENLOG_INFO, "All CPUs offline -- powering off.\n");
765 domain_shutdown(d, SHUTDOWN_poweroff);
766 }
767 }
769 void hvm_send_assist_req(struct vcpu *v)
770 {
771 ioreq_t *p;
773 if ( unlikely(!vcpu_start_shutdown_deferral(v)) )
774 return; /* implicitly bins the i/o operation */
776 p = &get_ioreq(v)->vp_ioreq;
777 if ( unlikely(p->state != STATE_IOREQ_NONE) )
778 {
779 /* This indicates a bug in the device model. Crash the domain. */
780 gdprintk(XENLOG_ERR, "Device model set bad IO state %d.\n", p->state);
781 domain_crash(v->domain);
782 return;
783 }
785 prepare_wait_on_xen_event_channel(v->arch.hvm_vcpu.xen_port);
787 /*
788 * Following happens /after/ blocking and setting up ioreq contents.
789 * prepare_wait_on_xen_event_channel() is an implicit barrier.
790 */
791 p->state = STATE_IOREQ_READY;
792 notify_via_xen_event_channel(v->arch.hvm_vcpu.xen_port);
793 }
795 void hvm_hlt(unsigned long rflags)
796 {
797 struct vcpu *curr = current;
799 if ( hvm_event_pending(curr) )
800 return;
802 /*
803 * If we halt with interrupts disabled, that's a pretty sure sign that we
804 * want to shut down. In a real processor, NMIs are the only way to break
805 * out of this.
806 */
807 if ( unlikely(!(rflags & X86_EFLAGS_IF)) )
808 return hvm_vcpu_down(curr);
810 do_sched_op_compat(SCHEDOP_block, 0);
812 HVMTRACE_1D(HLT, /* pending = */ vcpu_runnable(curr));
813 }
815 void hvm_triple_fault(void)
816 {
817 struct vcpu *v = current;
818 gdprintk(XENLOG_INFO, "Triple fault on VCPU%d - "
819 "invoking HVM system reset.\n", v->vcpu_id);
820 domain_shutdown(v->domain, SHUTDOWN_reboot);
821 }
823 int hvm_set_efer(uint64_t value)
824 {
825 struct vcpu *v = current;
827 value &= ~EFER_LMA;
829 if ( (value & ~(EFER_FFXSE | EFER_LME | EFER_NX | EFER_SCE)) ||
830 ((sizeof(long) != 8) && (value & EFER_LME)) ||
831 (!cpu_has_nx && (value & EFER_NX)) ||
832 (!cpu_has_syscall && (value & EFER_SCE)) ||
833 (!cpu_has_ffxsr && (value & EFER_FFXSE)) )
834 {
835 gdprintk(XENLOG_WARNING, "Trying to set reserved bit in "
836 "EFER: %"PRIx64"\n", value);
837 hvm_inject_exception(TRAP_gp_fault, 0, 0);
838 return X86EMUL_EXCEPTION;
839 }
841 if ( ((value ^ v->arch.hvm_vcpu.guest_efer) & EFER_LME) &&
842 hvm_paging_enabled(v) )
843 {
844 gdprintk(XENLOG_WARNING,
845 "Trying to change EFER.LME with paging enabled\n");
846 hvm_inject_exception(TRAP_gp_fault, 0, 0);
847 return X86EMUL_EXCEPTION;
848 }
850 value |= v->arch.hvm_vcpu.guest_efer & EFER_LMA;
851 v->arch.hvm_vcpu.guest_efer = value;
852 hvm_update_guest_efer(v);
854 return X86EMUL_OKAY;
855 }
857 extern void shadow_blow_tables_per_domain(struct domain *d);
858 extern bool_t mtrr_pat_not_equal(struct vcpu *vd, struct vcpu *vs);
860 /* Exit UC mode only if all VCPUs agree on MTRR/PAT and are not in no_fill. */
861 static bool_t domain_exit_uc_mode(struct vcpu *v)
862 {
863 struct domain *d = v->domain;
864 struct vcpu *vs;
866 for_each_vcpu ( d, vs )
867 {
868 if ( (vs == v) || !vs->is_initialised )
869 continue;
870 if ( (vs->arch.hvm_vcpu.cache_mode == NO_FILL_CACHE_MODE) ||
871 mtrr_pat_not_equal(vs, v) )
872 return 0;
873 }
875 return 1;
876 }
878 static void local_flush_cache(void *info)
879 {
880 wbinvd();
881 }
883 static void hvm_set_uc_mode(struct vcpu *v, bool_t is_in_uc_mode)
884 {
885 v->domain->arch.hvm_domain.is_in_uc_mode = is_in_uc_mode;
886 shadow_blow_tables_per_domain(v->domain);
887 if ( hvm_funcs.set_uc_mode )
888 return hvm_funcs.set_uc_mode(v);
889 }
891 int hvm_set_cr0(unsigned long value)
892 {
893 struct vcpu *v = current;
894 p2m_type_t p2mt;
895 unsigned long gfn, mfn, old_value = v->arch.hvm_vcpu.guest_cr[0];
897 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR0 value = %lx", value);
899 if ( (u32)value != value )
900 {
901 HVM_DBG_LOG(DBG_LEVEL_1,
902 "Guest attempts to set upper 32 bits in CR0: %lx",
903 value);
904 goto gpf;
905 }
907 value &= ~HVM_CR0_GUEST_RESERVED_BITS;
909 /* ET is reserved and should be always be 1. */
910 value |= X86_CR0_ET;
912 if ( (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PG )
913 goto gpf;
915 if ( (value & X86_CR0_PG) && !(old_value & X86_CR0_PG) )
916 {
917 if ( v->arch.hvm_vcpu.guest_efer & EFER_LME )
918 {
919 if ( !(v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_PAE) )
920 {
921 HVM_DBG_LOG(DBG_LEVEL_1, "Enable paging before PAE enable");
922 goto gpf;
923 }
924 HVM_DBG_LOG(DBG_LEVEL_1, "Enabling long mode");
925 v->arch.hvm_vcpu.guest_efer |= EFER_LMA;
926 hvm_update_guest_efer(v);
927 }
929 if ( !paging_mode_hap(v->domain) )
930 {
931 /* The guest CR3 must be pointing to the guest physical. */
932 gfn = v->arch.hvm_vcpu.guest_cr[3]>>PAGE_SHIFT;
933 mfn = mfn_x(gfn_to_mfn_current(gfn, &p2mt));
934 if ( !p2m_is_ram(p2mt) || !mfn_valid(mfn) ||
935 !get_page(mfn_to_page(mfn), v->domain))
936 {
937 gdprintk(XENLOG_ERR, "Invalid CR3 value = %lx (mfn=%lx)\n",
938 v->arch.hvm_vcpu.guest_cr[3], mfn);
939 domain_crash(v->domain);
940 return X86EMUL_UNHANDLEABLE;
941 }
943 /* Now arch.guest_table points to machine physical. */
944 v->arch.guest_table = pagetable_from_pfn(mfn);
946 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
947 v->arch.hvm_vcpu.guest_cr[3], mfn);
948 }
949 }
950 else if ( !(value & X86_CR0_PG) && (old_value & X86_CR0_PG) )
951 {
952 /* When CR0.PG is cleared, LMA is cleared immediately. */
953 if ( hvm_long_mode_enabled(v) )
954 {
955 v->arch.hvm_vcpu.guest_efer &= ~EFER_LMA;
956 hvm_update_guest_efer(v);
957 }
959 if ( !paging_mode_hap(v->domain) )
960 {
961 put_page(pagetable_get_page(v->arch.guest_table));
962 v->arch.guest_table = pagetable_null();
963 }
964 }
966 if ( has_arch_pdevs(v->domain) )
967 {
968 if ( (value & X86_CR0_CD) && !(value & X86_CR0_NW) )
969 {
970 /* Entering no fill cache mode. */
971 spin_lock(&v->domain->arch.hvm_domain.uc_lock);
972 v->arch.hvm_vcpu.cache_mode = NO_FILL_CACHE_MODE;
974 if ( !v->domain->arch.hvm_domain.is_in_uc_mode )
975 {
976 /* Flush physical caches. */
977 on_each_cpu(local_flush_cache, NULL, 1);
978 hvm_set_uc_mode(v, 1);
979 }
980 spin_unlock(&v->domain->arch.hvm_domain.uc_lock);
981 }
982 else if ( !(value & (X86_CR0_CD | X86_CR0_NW)) &&
983 (v->arch.hvm_vcpu.cache_mode == NO_FILL_CACHE_MODE) )
984 {
985 /* Exit from no fill cache mode. */
986 spin_lock(&v->domain->arch.hvm_domain.uc_lock);
987 v->arch.hvm_vcpu.cache_mode = NORMAL_CACHE_MODE;
989 if ( domain_exit_uc_mode(v) )
990 hvm_set_uc_mode(v, 0);
992 spin_unlock(&v->domain->arch.hvm_domain.uc_lock);
993 }
994 }
996 v->arch.hvm_vcpu.guest_cr[0] = value;
997 hvm_update_guest_cr(v, 0);
999 if ( (value ^ old_value) & X86_CR0_PG )
1000 paging_update_paging_modes(v);
1002 return X86EMUL_OKAY;
1004 gpf:
1005 hvm_inject_exception(TRAP_gp_fault, 0, 0);
1006 return X86EMUL_EXCEPTION;
1009 int hvm_set_cr3(unsigned long value)
1011 unsigned long mfn;
1012 p2m_type_t p2mt;
1013 struct vcpu *v = current;
1015 if ( hvm_paging_enabled(v) && !paging_mode_hap(v->domain) &&
1016 (value != v->arch.hvm_vcpu.guest_cr[3]) )
1018 /* Shadow-mode CR3 change. Check PDBR and update refcounts. */
1019 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 value = %lx", value);
1020 mfn = mfn_x(gfn_to_mfn_current(value >> PAGE_SHIFT, &p2mt));
1021 if ( !p2m_is_ram(p2mt) || !mfn_valid(mfn) ||
1022 !get_page(mfn_to_page(mfn), v->domain) )
1023 goto bad_cr3;
1025 put_page(pagetable_get_page(v->arch.guest_table));
1026 v->arch.guest_table = pagetable_from_pfn(mfn);
1028 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx", value);
1031 v->arch.hvm_vcpu.guest_cr[3] = value;
1032 paging_update_cr3(v);
1033 return X86EMUL_OKAY;
1035 bad_cr3:
1036 gdprintk(XENLOG_ERR, "Invalid CR3\n");
1037 domain_crash(v->domain);
1038 return X86EMUL_UNHANDLEABLE;
1041 int hvm_set_cr4(unsigned long value)
1043 struct vcpu *v = current;
1044 unsigned long old_cr;
1046 if ( value & HVM_CR4_GUEST_RESERVED_BITS )
1048 HVM_DBG_LOG(DBG_LEVEL_1,
1049 "Guest attempts to set reserved bit in CR4: %lx",
1050 value);
1051 goto gpf;
1054 if ( !(value & X86_CR4_PAE) && hvm_long_mode_enabled(v) )
1056 HVM_DBG_LOG(DBG_LEVEL_1, "Guest cleared CR4.PAE while "
1057 "EFER.LMA is set");
1058 goto gpf;
1061 old_cr = v->arch.hvm_vcpu.guest_cr[4];
1062 v->arch.hvm_vcpu.guest_cr[4] = value;
1063 hvm_update_guest_cr(v, 4);
1065 /* Modifying CR4.{PSE,PAE,PGE} invalidates all TLB entries, inc. Global. */
1066 if ( (old_cr ^ value) & (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE) )
1067 paging_update_paging_modes(v);
1069 return X86EMUL_OKAY;
1071 gpf:
1072 hvm_inject_exception(TRAP_gp_fault, 0, 0);
1073 return X86EMUL_EXCEPTION;
1076 int hvm_virtual_to_linear_addr(
1077 enum x86_segment seg,
1078 struct segment_register *reg,
1079 unsigned long offset,
1080 unsigned int bytes,
1081 enum hvm_access_type access_type,
1082 unsigned int addr_size,
1083 unsigned long *linear_addr)
1085 unsigned long addr = offset;
1086 uint32_t last_byte;
1088 if ( !(current->arch.hvm_vcpu.guest_cr[0] & X86_CR0_PE) )
1090 /*
1091 * REAL MODE: Don't bother with segment access checks.
1092 * Certain of them are not done in native real mode anyway.
1093 */
1094 addr = (uint32_t)(addr + reg->base);
1096 else if ( addr_size != 64 )
1098 /*
1099 * COMPATIBILITY MODE: Apply segment checks and add base.
1100 */
1102 switch ( access_type )
1104 case hvm_access_read:
1105 if ( (reg->attr.fields.type & 0xa) == 0x8 )
1106 goto gpf; /* execute-only code segment */
1107 break;
1108 case hvm_access_write:
1109 if ( (reg->attr.fields.type & 0xa) != 0x2 )
1110 goto gpf; /* not a writable data segment */
1111 break;
1112 default:
1113 break;
1116 last_byte = offset + bytes - 1;
1118 /* Is this a grows-down data segment? Special limit check if so. */
1119 if ( (reg->attr.fields.type & 0xc) == 0x4 )
1121 /* Is upper limit 0xFFFF or 0xFFFFFFFF? */
1122 if ( !reg->attr.fields.db )
1123 last_byte = (uint16_t)last_byte;
1125 /* Check first byte and last byte against respective bounds. */
1126 if ( (offset <= reg->limit) || (last_byte < offset) )
1127 goto gpf;
1129 else if ( (last_byte > reg->limit) || (last_byte < offset) )
1130 goto gpf; /* last byte is beyond limit or wraps 0xFFFFFFFF */
1132 /*
1133 * Hardware truncates to 32 bits in compatibility mode.
1134 * It does not truncate to 16 bits in 16-bit address-size mode.
1135 */
1136 addr = (uint32_t)(addr + reg->base);
1138 else
1140 /*
1141 * LONG MODE: FS and GS add segment base. Addresses must be canonical.
1142 */
1144 if ( (seg == x86_seg_fs) || (seg == x86_seg_gs) )
1145 addr += reg->base;
1147 if ( !is_canonical_address(addr) )
1148 goto gpf;
1151 *linear_addr = addr;
1152 return 1;
1154 gpf:
1155 return 0;
1158 static void *hvm_map_entry(unsigned long va)
1160 unsigned long gfn, mfn;
1161 p2m_type_t p2mt;
1162 uint32_t pfec;
1164 if ( ((va & ~PAGE_MASK) + 8) > PAGE_SIZE )
1166 gdprintk(XENLOG_ERR, "Descriptor table entry "
1167 "straddles page boundary\n");
1168 domain_crash(current->domain);
1169 return NULL;
1172 /* We're mapping on behalf of the segment-load logic, which might
1173 * write the accessed flags in the descriptors (in 32-bit mode), but
1174 * we still treat it as a kernel-mode read (i.e. no access checks). */
1175 pfec = PFEC_page_present;
1176 gfn = paging_gva_to_gfn(current, va, &pfec);
1177 mfn = mfn_x(gfn_to_mfn_current(gfn, &p2mt));
1178 if ( !p2m_is_ram(p2mt) )
1180 gdprintk(XENLOG_ERR, "Failed to look up descriptor table entry\n");
1181 domain_crash(current->domain);
1182 return NULL;
1185 ASSERT(mfn_valid(mfn));
1187 paging_mark_dirty(current->domain, mfn);
1189 return (char *)map_domain_page(mfn) + (va & ~PAGE_MASK);
1192 static void hvm_unmap_entry(void *p)
1194 if ( p )
1195 unmap_domain_page(p);
1198 static int hvm_load_segment_selector(
1199 enum x86_segment seg, uint16_t sel)
1201 struct segment_register desctab, cs, segr;
1202 struct desc_struct *pdesc, desc;
1203 u8 dpl, rpl, cpl;
1204 int fault_type = TRAP_invalid_tss;
1205 struct cpu_user_regs *regs = guest_cpu_user_regs();
1206 struct vcpu *v = current;
1208 if ( regs->eflags & EF_VM )
1210 segr.sel = sel;
1211 segr.base = (uint32_t)sel << 4;
1212 segr.limit = 0xffffu;
1213 segr.attr.bytes = 0xf3;
1214 hvm_set_segment_register(v, seg, &segr);
1215 return 0;
1218 /* NULL selector? */
1219 if ( (sel & 0xfffc) == 0 )
1221 if ( (seg == x86_seg_cs) || (seg == x86_seg_ss) )
1222 goto fail;
1223 memset(&segr, 0, sizeof(segr));
1224 hvm_set_segment_register(v, seg, &segr);
1225 return 0;
1228 /* LDT descriptor must be in the GDT. */
1229 if ( (seg == x86_seg_ldtr) && (sel & 4) )
1230 goto fail;
1232 hvm_get_segment_register(v, x86_seg_cs, &cs);
1233 hvm_get_segment_register(
1234 v, (sel & 4) ? x86_seg_ldtr : x86_seg_gdtr, &desctab);
1236 /* Check against descriptor table limit. */
1237 if ( ((sel & 0xfff8) + 7) > desctab.limit )
1238 goto fail;
1240 pdesc = hvm_map_entry(desctab.base + (sel & 0xfff8));
1241 if ( pdesc == NULL )
1242 goto hvm_map_fail;
1244 do {
1245 desc = *pdesc;
1247 /* Segment present in memory? */
1248 if ( !(desc.b & (1u<<15)) )
1250 fault_type = TRAP_no_segment;
1251 goto unmap_and_fail;
1254 /* LDT descriptor is a system segment. All others are code/data. */
1255 if ( (desc.b & (1u<<12)) == ((seg == x86_seg_ldtr) << 12) )
1256 goto unmap_and_fail;
1258 dpl = (desc.b >> 13) & 3;
1259 rpl = sel & 3;
1260 cpl = cs.sel & 3;
1262 switch ( seg )
1264 case x86_seg_cs:
1265 /* Code segment? */
1266 if ( !(desc.b & (1u<<11)) )
1267 goto unmap_and_fail;
1268 /* Non-conforming segment: check DPL against RPL. */
1269 if ( ((desc.b & (6u<<9)) != 6) && (dpl != rpl) )
1270 goto unmap_and_fail;
1271 break;
1272 case x86_seg_ss:
1273 /* Writable data segment? */
1274 if ( (desc.b & (5u<<9)) != (1u<<9) )
1275 goto unmap_and_fail;
1276 if ( (dpl != cpl) || (dpl != rpl) )
1277 goto unmap_and_fail;
1278 break;
1279 case x86_seg_ldtr:
1280 /* LDT system segment? */
1281 if ( (desc.b & (15u<<8)) != (2u<<8) )
1282 goto unmap_and_fail;
1283 goto skip_accessed_flag;
1284 default:
1285 /* Readable code or data segment? */
1286 if ( (desc.b & (5u<<9)) == (4u<<9) )
1287 goto unmap_and_fail;
1288 /* Non-conforming segment: check DPL against RPL and CPL. */
1289 if ( ((desc.b & (6u<<9)) != 6) && ((dpl < cpl) || (dpl < rpl)) )
1290 goto unmap_and_fail;
1291 break;
1293 } while ( !(desc.b & 0x100) && /* Ensure Accessed flag is set */
1294 (cmpxchg(&pdesc->b, desc.b, desc.b | 0x100) != desc.b) );
1296 /* Force the Accessed flag in our local copy. */
1297 desc.b |= 0x100;
1299 skip_accessed_flag:
1300 hvm_unmap_entry(pdesc);
1302 segr.base = (((desc.b << 0) & 0xff000000u) |
1303 ((desc.b << 16) & 0x00ff0000u) |
1304 ((desc.a >> 16) & 0x0000ffffu));
1305 segr.attr.bytes = (((desc.b >> 8) & 0x00ffu) |
1306 ((desc.b >> 12) & 0x0f00u));
1307 segr.limit = (desc.b & 0x000f0000u) | (desc.a & 0x0000ffffu);
1308 if ( segr.attr.fields.g )
1309 segr.limit = (segr.limit << 12) | 0xfffu;
1310 segr.sel = sel;
1311 hvm_set_segment_register(v, seg, &segr);
1313 return 0;
1315 unmap_and_fail:
1316 hvm_unmap_entry(pdesc);
1317 fail:
1318 hvm_inject_exception(fault_type, sel & 0xfffc, 0);
1319 hvm_map_fail:
1320 return 1;
1323 void hvm_task_switch(
1324 uint16_t tss_sel, enum hvm_task_switch_reason taskswitch_reason,
1325 int32_t errcode)
1327 struct vcpu *v = current;
1328 struct cpu_user_regs *regs = guest_cpu_user_regs();
1329 struct segment_register gdt, tr, prev_tr, segr;
1330 struct desc_struct *optss_desc = NULL, *nptss_desc = NULL, tss_desc;
1331 unsigned long eflags;
1332 int exn_raised, rc;
1333 struct {
1334 u16 back_link,__blh;
1335 u32 esp0;
1336 u16 ss0, _0;
1337 u32 esp1;
1338 u16 ss1, _1;
1339 u32 esp2;
1340 u16 ss2, _2;
1341 u32 cr3, eip, eflags, eax, ecx, edx, ebx, esp, ebp, esi, edi;
1342 u16 es, _3, cs, _4, ss, _5, ds, _6, fs, _7, gs, _8, ldt, _9;
1343 u16 trace, iomap;
1344 } tss = { 0 };
1346 hvm_get_segment_register(v, x86_seg_gdtr, &gdt);
1347 hvm_get_segment_register(v, x86_seg_tr, &prev_tr);
1349 if ( ((tss_sel & 0xfff8) + 7) > gdt.limit )
1351 hvm_inject_exception((taskswitch_reason == TSW_iret) ?
1352 TRAP_invalid_tss : TRAP_gp_fault,
1353 tss_sel & 0xfff8, 0);
1354 goto out;
1357 optss_desc = hvm_map_entry(gdt.base + (prev_tr.sel & 0xfff8));
1358 if ( optss_desc == NULL )
1359 goto out;
1361 nptss_desc = hvm_map_entry(gdt.base + (tss_sel & 0xfff8));
1362 if ( nptss_desc == NULL )
1363 goto out;
1365 tss_desc = *nptss_desc;
1366 tr.sel = tss_sel;
1367 tr.base = (((tss_desc.b << 0) & 0xff000000u) |
1368 ((tss_desc.b << 16) & 0x00ff0000u) |
1369 ((tss_desc.a >> 16) & 0x0000ffffu));
1370 tr.attr.bytes = (((tss_desc.b >> 8) & 0x00ffu) |
1371 ((tss_desc.b >> 12) & 0x0f00u));
1372 tr.limit = (tss_desc.b & 0x000f0000u) | (tss_desc.a & 0x0000ffffu);
1373 if ( tr.attr.fields.g )
1374 tr.limit = (tr.limit << 12) | 0xfffu;
1376 if ( !tr.attr.fields.p )
1378 hvm_inject_exception(TRAP_no_segment, tss_sel & 0xfff8, 0);
1379 goto out;
1382 if ( tr.attr.fields.type != ((taskswitch_reason == TSW_iret) ? 0xb : 0x9) )
1384 hvm_inject_exception(
1385 (taskswitch_reason == TSW_iret) ? TRAP_invalid_tss : TRAP_gp_fault,
1386 tss_sel & 0xfff8, 0);
1387 goto out;
1390 if ( tr.limit < (sizeof(tss)-1) )
1392 hvm_inject_exception(TRAP_invalid_tss, tss_sel & 0xfff8, 0);
1393 goto out;
1396 rc = hvm_copy_from_guest_virt(
1397 &tss, prev_tr.base, sizeof(tss), PFEC_page_present);
1398 if ( rc == HVMCOPY_bad_gva_to_gfn )
1399 goto out;
1401 eflags = regs->eflags;
1402 if ( taskswitch_reason == TSW_iret )
1403 eflags &= ~X86_EFLAGS_NT;
1405 tss.cr3 = v->arch.hvm_vcpu.guest_cr[3];
1406 tss.eip = regs->eip;
1407 tss.eflags = eflags;
1408 tss.eax = regs->eax;
1409 tss.ecx = regs->ecx;
1410 tss.edx = regs->edx;
1411 tss.ebx = regs->ebx;
1412 tss.esp = regs->esp;
1413 tss.ebp = regs->ebp;
1414 tss.esi = regs->esi;
1415 tss.edi = regs->edi;
1417 hvm_get_segment_register(v, x86_seg_es, &segr);
1418 tss.es = segr.sel;
1419 hvm_get_segment_register(v, x86_seg_cs, &segr);
1420 tss.cs = segr.sel;
1421 hvm_get_segment_register(v, x86_seg_ss, &segr);
1422 tss.ss = segr.sel;
1423 hvm_get_segment_register(v, x86_seg_ds, &segr);
1424 tss.ds = segr.sel;
1425 hvm_get_segment_register(v, x86_seg_fs, &segr);
1426 tss.fs = segr.sel;
1427 hvm_get_segment_register(v, x86_seg_gs, &segr);
1428 tss.gs = segr.sel;
1429 hvm_get_segment_register(v, x86_seg_ldtr, &segr);
1430 tss.ldt = segr.sel;
1432 rc = hvm_copy_to_guest_virt(
1433 prev_tr.base, &tss, sizeof(tss), PFEC_page_present);
1434 if ( rc == HVMCOPY_bad_gva_to_gfn )
1435 goto out;
1437 rc = hvm_copy_from_guest_virt(
1438 &tss, tr.base, sizeof(tss), PFEC_page_present);
1439 if ( rc == HVMCOPY_bad_gva_to_gfn )
1440 goto out;
1442 if ( hvm_set_cr3(tss.cr3) )
1443 goto out;
1445 regs->eip = tss.eip;
1446 regs->eflags = tss.eflags | 2;
1447 regs->eax = tss.eax;
1448 regs->ecx = tss.ecx;
1449 regs->edx = tss.edx;
1450 regs->ebx = tss.ebx;
1451 regs->esp = tss.esp;
1452 regs->ebp = tss.ebp;
1453 regs->esi = tss.esi;
1454 regs->edi = tss.edi;
1456 if ( (taskswitch_reason == TSW_call_or_int) )
1458 regs->eflags |= X86_EFLAGS_NT;
1459 tss.back_link = prev_tr.sel;
1462 exn_raised = 0;
1463 if ( hvm_load_segment_selector(x86_seg_ldtr, tss.ldt) ||
1464 hvm_load_segment_selector(x86_seg_es, tss.es) ||
1465 hvm_load_segment_selector(x86_seg_cs, tss.cs) ||
1466 hvm_load_segment_selector(x86_seg_ss, tss.ss) ||
1467 hvm_load_segment_selector(x86_seg_ds, tss.ds) ||
1468 hvm_load_segment_selector(x86_seg_fs, tss.fs) ||
1469 hvm_load_segment_selector(x86_seg_gs, tss.gs) )
1470 exn_raised = 1;
1472 rc = hvm_copy_to_guest_virt(
1473 tr.base, &tss, sizeof(tss), PFEC_page_present);
1474 if ( rc == HVMCOPY_bad_gva_to_gfn )
1475 exn_raised = 1;
1477 if ( (tss.trace & 1) && !exn_raised )
1478 hvm_inject_exception(TRAP_debug, tss_sel & 0xfff8, 0);
1480 tr.attr.fields.type = 0xb; /* busy 32-bit tss */
1481 hvm_set_segment_register(v, x86_seg_tr, &tr);
1483 v->arch.hvm_vcpu.guest_cr[0] |= X86_CR0_TS;
1484 hvm_update_guest_cr(v, 0);
1486 if ( (taskswitch_reason == TSW_iret) ||
1487 (taskswitch_reason == TSW_jmp) )
1488 clear_bit(41, optss_desc); /* clear B flag of old task */
1490 if ( taskswitch_reason != TSW_iret )
1491 set_bit(41, nptss_desc); /* set B flag of new task */
1493 if ( errcode >= 0 )
1495 struct segment_register reg;
1496 unsigned long linear_addr;
1497 regs->esp -= 4;
1498 hvm_get_segment_register(current, x86_seg_ss, &reg);
1499 /* Todo: do not ignore access faults here. */
1500 if ( hvm_virtual_to_linear_addr(x86_seg_ss, &reg, regs->esp,
1501 4, hvm_access_write, 32,
1502 &linear_addr) )
1503 hvm_copy_to_guest_virt_nofault(linear_addr, &errcode, 4, 0);
1506 out:
1507 hvm_unmap_entry(optss_desc);
1508 hvm_unmap_entry(nptss_desc);
1511 #define HVMCOPY_from_guest (0u<<0)
1512 #define HVMCOPY_to_guest (1u<<0)
1513 #define HVMCOPY_no_fault (0u<<1)
1514 #define HVMCOPY_fault (1u<<1)
1515 #define HVMCOPY_phys (0u<<2)
1516 #define HVMCOPY_virt (1u<<2)
1517 static enum hvm_copy_result __hvm_copy(
1518 void *buf, paddr_t addr, int size, unsigned int flags, uint32_t pfec)
1520 struct vcpu *curr = current;
1521 unsigned long gfn, mfn;
1522 p2m_type_t p2mt;
1523 char *p;
1524 int count, todo = size;
1526 while ( todo > 0 )
1528 count = min_t(int, PAGE_SIZE - (addr & ~PAGE_MASK), todo);
1530 if ( flags & HVMCOPY_virt )
1532 gfn = paging_gva_to_gfn(curr, addr, &pfec);
1533 if ( gfn == INVALID_GFN )
1535 if ( flags & HVMCOPY_fault )
1536 hvm_inject_exception(TRAP_page_fault, pfec, addr);
1537 return HVMCOPY_bad_gva_to_gfn;
1540 else
1542 gfn = addr >> PAGE_SHIFT;
1545 mfn = mfn_x(gfn_to_mfn_current(gfn, &p2mt));
1547 if ( !p2m_is_ram(p2mt) )
1548 return HVMCOPY_bad_gfn_to_mfn;
1549 ASSERT(mfn_valid(mfn));
1551 p = (char *)map_domain_page(mfn) + (addr & ~PAGE_MASK);
1553 if ( flags & HVMCOPY_to_guest )
1555 if ( p2mt == p2m_ram_ro )
1557 static unsigned long lastpage;
1558 if ( xchg(&lastpage, gfn) != gfn )
1559 gdprintk(XENLOG_DEBUG, "guest attempted write to read-only"
1560 " memory page. gfn=%#lx, mfn=%#lx\n",
1561 gfn, mfn);
1563 else
1565 memcpy(p, buf, count);
1566 paging_mark_dirty(curr->domain, mfn);
1569 else
1571 memcpy(buf, p, count);
1574 unmap_domain_page(p);
1576 addr += count;
1577 buf += count;
1578 todo -= count;
1581 return HVMCOPY_okay;
1584 enum hvm_copy_result hvm_copy_to_guest_phys(
1585 paddr_t paddr, void *buf, int size)
1587 return __hvm_copy(buf, paddr, size,
1588 HVMCOPY_to_guest | HVMCOPY_fault | HVMCOPY_phys,
1589 0);
1592 enum hvm_copy_result hvm_copy_from_guest_phys(
1593 void *buf, paddr_t paddr, int size)
1595 return __hvm_copy(buf, paddr, size,
1596 HVMCOPY_from_guest | HVMCOPY_fault | HVMCOPY_phys,
1597 0);
1600 enum hvm_copy_result hvm_copy_to_guest_virt(
1601 unsigned long vaddr, void *buf, int size, uint32_t pfec)
1603 return __hvm_copy(buf, vaddr, size,
1604 HVMCOPY_to_guest | HVMCOPY_fault | HVMCOPY_virt,
1605 PFEC_page_present | PFEC_write_access | pfec);
1608 enum hvm_copy_result hvm_copy_from_guest_virt(
1609 void *buf, unsigned long vaddr, int size, uint32_t pfec)
1611 return __hvm_copy(buf, vaddr, size,
1612 HVMCOPY_from_guest | HVMCOPY_fault | HVMCOPY_virt,
1613 PFEC_page_present | pfec);
1616 enum hvm_copy_result hvm_fetch_from_guest_virt(
1617 void *buf, unsigned long vaddr, int size, uint32_t pfec)
1619 if ( hvm_nx_enabled(current) )
1620 pfec |= PFEC_insn_fetch;
1621 return __hvm_copy(buf, vaddr, size,
1622 HVMCOPY_from_guest | HVMCOPY_fault | HVMCOPY_virt,
1623 PFEC_page_present | pfec);
1626 enum hvm_copy_result hvm_copy_to_guest_virt_nofault(
1627 unsigned long vaddr, void *buf, int size, uint32_t pfec)
1629 return __hvm_copy(buf, vaddr, size,
1630 HVMCOPY_to_guest | HVMCOPY_no_fault | HVMCOPY_virt,
1631 PFEC_page_present | PFEC_write_access | pfec);
1634 enum hvm_copy_result hvm_copy_from_guest_virt_nofault(
1635 void *buf, unsigned long vaddr, int size, uint32_t pfec)
1637 return __hvm_copy(buf, vaddr, size,
1638 HVMCOPY_from_guest | HVMCOPY_no_fault | HVMCOPY_virt,
1639 PFEC_page_present | pfec);
1642 enum hvm_copy_result hvm_fetch_from_guest_virt_nofault(
1643 void *buf, unsigned long vaddr, int size, uint32_t pfec)
1645 if ( hvm_nx_enabled(current) )
1646 pfec |= PFEC_insn_fetch;
1647 return __hvm_copy(buf, vaddr, size,
1648 HVMCOPY_from_guest | HVMCOPY_no_fault | HVMCOPY_virt,
1649 PFEC_page_present | pfec);
1652 #ifdef __x86_64__
1653 DEFINE_PER_CPU(bool_t, hvm_64bit_hcall);
1654 #endif
1656 unsigned long copy_to_user_hvm(void *to, const void *from, unsigned int len)
1658 int rc;
1660 #ifdef __x86_64__
1661 if ( !this_cpu(hvm_64bit_hcall) && is_compat_arg_xlat_range(to, len) )
1663 memcpy(to, from, len);
1664 return 0;
1666 #endif
1668 rc = hvm_copy_to_guest_virt_nofault((unsigned long)to, (void *)from,
1669 len, 0);
1670 return rc ? len : 0; /* fake a copy_to_user() return code */
1673 unsigned long copy_from_user_hvm(void *to, const void *from, unsigned len)
1675 int rc;
1677 #ifdef __x86_64__
1678 if ( !this_cpu(hvm_64bit_hcall) && is_compat_arg_xlat_range(from, len) )
1680 memcpy(to, from, len);
1681 return 0;
1683 #endif
1685 rc = hvm_copy_from_guest_virt_nofault(to, (unsigned long)from, len, 0);
1686 return rc ? len : 0; /* fake a copy_from_user() return code */
1689 #define bitmaskof(idx) (1U << ((idx) & 31))
1690 void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx,
1691 unsigned int *ecx, unsigned int *edx)
1693 struct vcpu *v = current;
1695 if ( cpuid_viridian_leaves(input, eax, ebx, ecx, edx) )
1696 return;
1698 if ( cpuid_hypervisor_leaves(input, eax, ebx, ecx, edx) )
1699 return;
1701 domain_cpuid(v->domain, input, *ecx, eax, ebx, ecx, edx);
1703 switch ( input )
1705 case 0x1:
1706 /* Fix up VLAPIC details. */
1707 *ebx &= 0x00FFFFFFu;
1708 *ebx |= (v->vcpu_id * 2) << 24;
1709 if ( vlapic_hw_disabled(vcpu_vlapic(v)) )
1710 __clear_bit(X86_FEATURE_APIC & 31, edx);
1711 break;
1712 case 0xb:
1713 /* Fix the x2APIC identifier. */
1714 *edx = v->vcpu_id * 2;
1715 break;
1719 void hvm_rdtsc_intercept(struct cpu_user_regs *regs)
1721 uint64_t tsc;
1722 struct vcpu *v = current;
1724 tsc = hvm_get_guest_tsc(v);
1725 regs->eax = (uint32_t)tsc;
1726 regs->edx = (uint32_t)(tsc >> 32);
1729 int hvm_msr_read_intercept(struct cpu_user_regs *regs)
1731 uint32_t ecx = regs->ecx;
1732 uint64_t msr_content = 0;
1733 struct vcpu *v = current;
1734 uint64_t *var_range_base, *fixed_range_base;
1735 int index, mtrr;
1736 uint32_t cpuid[4];
1738 var_range_base = (uint64_t *)v->arch.hvm_vcpu.mtrr.var_ranges;
1739 fixed_range_base = (uint64_t *)v->arch.hvm_vcpu.mtrr.fixed_ranges;
1741 hvm_cpuid(1, &cpuid[0], &cpuid[1], &cpuid[2], &cpuid[3]);
1742 mtrr = !!(cpuid[3] & bitmaskof(X86_FEATURE_MTRR));
1744 switch ( ecx )
1746 case MSR_IA32_TSC:
1747 msr_content = hvm_get_guest_tsc(v);
1748 break;
1750 case MSR_IA32_APICBASE:
1751 msr_content = vcpu_vlapic(v)->hw.apic_base_msr;
1752 break;
1754 case MSR_IA32_MCG_CAP:
1755 case MSR_IA32_MCG_STATUS:
1756 case MSR_IA32_MC0_STATUS:
1757 case MSR_IA32_MC1_STATUS:
1758 case MSR_IA32_MC2_STATUS:
1759 case MSR_IA32_MC3_STATUS:
1760 case MSR_IA32_MC4_STATUS:
1761 case MSR_IA32_MC5_STATUS:
1762 /* No point in letting the guest see real MCEs */
1763 msr_content = 0;
1764 break;
1766 case MSR_IA32_CR_PAT:
1767 msr_content = v->arch.hvm_vcpu.pat_cr;
1768 break;
1770 case MSR_MTRRcap:
1771 if ( !mtrr )
1772 goto gp_fault;
1773 msr_content = v->arch.hvm_vcpu.mtrr.mtrr_cap;
1774 break;
1775 case MSR_MTRRdefType:
1776 if ( !mtrr )
1777 goto gp_fault;
1778 msr_content = v->arch.hvm_vcpu.mtrr.def_type
1779 | (v->arch.hvm_vcpu.mtrr.enabled << 10);
1780 break;
1781 case MSR_MTRRfix64K_00000:
1782 if ( !mtrr )
1783 goto gp_fault;
1784 msr_content = fixed_range_base[0];
1785 break;
1786 case MSR_MTRRfix16K_80000:
1787 case MSR_MTRRfix16K_A0000:
1788 if ( !mtrr )
1789 goto gp_fault;
1790 index = regs->ecx - MSR_MTRRfix16K_80000;
1791 msr_content = fixed_range_base[index + 1];
1792 break;
1793 case MSR_MTRRfix4K_C0000...MSR_MTRRfix4K_F8000:
1794 if ( !mtrr )
1795 goto gp_fault;
1796 index = regs->ecx - MSR_MTRRfix4K_C0000;
1797 msr_content = fixed_range_base[index + 3];
1798 break;
1799 case MSR_IA32_MTRR_PHYSBASE0...MSR_IA32_MTRR_PHYSMASK7:
1800 if ( !mtrr )
1801 goto gp_fault;
1802 index = regs->ecx - MSR_IA32_MTRR_PHYSBASE0;
1803 msr_content = var_range_base[index];
1804 break;
1806 case MSR_K8_ENABLE_C1E:
1807 /* There's no point in letting the guest see C-States.
1808 * Further, this AMD-only register may be accessed if this HVM guest
1809 * has been migrated to an Intel host. This fixes a guest crash
1810 * in this case.
1811 */
1812 msr_content = 0;
1813 break;
1815 default:
1816 return hvm_funcs.msr_read_intercept(regs);
1819 regs->eax = (uint32_t)msr_content;
1820 regs->edx = (uint32_t)(msr_content >> 32);
1821 return X86EMUL_OKAY;
1823 gp_fault:
1824 hvm_inject_exception(TRAP_gp_fault, 0, 0);
1825 return X86EMUL_EXCEPTION;
1828 int hvm_msr_write_intercept(struct cpu_user_regs *regs)
1830 extern bool_t mtrr_var_range_msr_set(
1831 struct mtrr_state *v, u32 msr, u64 msr_content);
1832 extern bool_t mtrr_fix_range_msr_set(
1833 struct mtrr_state *v, int row, u64 msr_content);
1834 extern bool_t mtrr_def_type_msr_set(struct mtrr_state *v, u64 msr_content);
1835 extern bool_t pat_msr_set(u64 *pat, u64 msr);
1837 uint32_t ecx = regs->ecx;
1838 uint64_t msr_content = (uint32_t)regs->eax | ((uint64_t)regs->edx << 32);
1839 struct vcpu *v = current;
1840 int index, mtrr;
1841 uint32_t cpuid[4];
1843 hvm_cpuid(1, &cpuid[0], &cpuid[1], &cpuid[2], &cpuid[3]);
1844 mtrr = !!(cpuid[3] & bitmaskof(X86_FEATURE_MTRR));
1846 switch ( ecx )
1848 case MSR_IA32_TSC:
1849 hvm_set_guest_tsc(v, msr_content);
1850 pt_reset(v);
1851 break;
1853 case MSR_IA32_APICBASE:
1854 vlapic_msr_set(vcpu_vlapic(v), msr_content);
1855 break;
1857 case MSR_IA32_CR_PAT:
1858 if ( !pat_msr_set(&v->arch.hvm_vcpu.pat_cr, msr_content) )
1859 goto gp_fault;
1860 break;
1862 case MSR_MTRRcap:
1863 if ( !mtrr )
1864 goto gp_fault;
1865 goto gp_fault;
1866 case MSR_MTRRdefType:
1867 if ( !mtrr )
1868 goto gp_fault;
1869 if ( !mtrr_def_type_msr_set(&v->arch.hvm_vcpu.mtrr, msr_content) )
1870 goto gp_fault;
1871 break;
1872 case MSR_MTRRfix64K_00000:
1873 if ( !mtrr )
1874 goto gp_fault;
1875 if ( !mtrr_fix_range_msr_set(&v->arch.hvm_vcpu.mtrr, 0, msr_content) )
1876 goto gp_fault;
1877 break;
1878 case MSR_MTRRfix16K_80000:
1879 case MSR_MTRRfix16K_A0000:
1880 if ( !mtrr )
1881 goto gp_fault;
1882 index = regs->ecx - MSR_MTRRfix16K_80000 + 1;
1883 if ( !mtrr_fix_range_msr_set(&v->arch.hvm_vcpu.mtrr,
1884 index, msr_content) )
1885 goto gp_fault;
1886 break;
1887 case MSR_MTRRfix4K_C0000...MSR_MTRRfix4K_F8000:
1888 if ( !mtrr )
1889 goto gp_fault;
1890 index = regs->ecx - MSR_MTRRfix4K_C0000 + 3;
1891 if ( !mtrr_fix_range_msr_set(&v->arch.hvm_vcpu.mtrr,
1892 index, msr_content) )
1893 goto gp_fault;
1894 break;
1895 case MSR_IA32_MTRR_PHYSBASE0...MSR_IA32_MTRR_PHYSMASK7:
1896 if ( !mtrr )
1897 goto gp_fault;
1898 if ( !mtrr_var_range_msr_set(&v->arch.hvm_vcpu.mtrr,
1899 regs->ecx, msr_content) )
1900 goto gp_fault;
1901 break;
1903 default:
1904 return hvm_funcs.msr_write_intercept(regs);
1907 return X86EMUL_OKAY;
1909 gp_fault:
1910 hvm_inject_exception(TRAP_gp_fault, 0, 0);
1911 return X86EMUL_EXCEPTION;
1914 enum hvm_intblk hvm_interrupt_blocked(struct vcpu *v, struct hvm_intack intack)
1916 unsigned long intr_shadow;
1918 ASSERT(v == current);
1920 if ( (intack.source != hvm_intsrc_nmi) &&
1921 !(guest_cpu_user_regs()->eflags & X86_EFLAGS_IF) )
1922 return hvm_intblk_rflags_ie;
1924 intr_shadow = hvm_funcs.get_interrupt_shadow(v);
1926 if ( intr_shadow & (HVM_INTR_SHADOW_STI|HVM_INTR_SHADOW_MOV_SS) )
1927 return hvm_intblk_shadow;
1929 if ( intack.source == hvm_intsrc_nmi )
1930 return ((intr_shadow & HVM_INTR_SHADOW_NMI) ?
1931 hvm_intblk_nmi_iret : hvm_intblk_none);
1933 if ( intack.source == hvm_intsrc_lapic )
1935 uint32_t tpr = vlapic_get_reg(vcpu_vlapic(v), APIC_TASKPRI) & 0xF0;
1936 if ( (tpr >> 4) >= (intack.vector >> 4) )
1937 return hvm_intblk_tpr;
1940 return hvm_intblk_none;
1943 static long hvm_grant_table_op(
1944 unsigned int cmd, XEN_GUEST_HANDLE(void) uop, unsigned int count)
1946 if ( (cmd != GNTTABOP_query_size) && (cmd != GNTTABOP_setup_table) )
1947 return -ENOSYS; /* all other commands need auditing */
1948 return do_grant_table_op(cmd, uop, count);
1951 static long hvm_memory_op(int cmd, XEN_GUEST_HANDLE(void) arg)
1953 long rc = do_memory_op(cmd, arg);
1954 if ( (cmd & MEMOP_CMD_MASK) == XENMEM_decrease_reservation )
1955 current->domain->arch.hvm_domain.qemu_mapcache_invalidate = 1;
1956 return rc;
1959 static long hvm_vcpu_op(
1960 int cmd, int vcpuid, XEN_GUEST_HANDLE(void) arg)
1962 long rc;
1964 switch ( cmd )
1966 case VCPUOP_register_runstate_memory_area:
1967 case VCPUOP_get_runstate_info:
1968 rc = do_vcpu_op(cmd, vcpuid, arg);
1969 break;
1970 default:
1971 rc = -ENOSYS;
1972 break;
1975 return rc;
1978 typedef unsigned long hvm_hypercall_t(
1979 unsigned long, unsigned long, unsigned long, unsigned long, unsigned long);
1981 #define HYPERCALL(x) \
1982 [ __HYPERVISOR_ ## x ] = (hvm_hypercall_t *) do_ ## x
1984 #if defined(__i386__)
1986 static hvm_hypercall_t *hvm_hypercall32_table[NR_hypercalls] = {
1987 [ __HYPERVISOR_memory_op ] = (hvm_hypercall_t *)hvm_memory_op,
1988 [ __HYPERVISOR_grant_table_op ] = (hvm_hypercall_t *)hvm_grant_table_op,
1989 [ __HYPERVISOR_vcpu_op ] = (hvm_hypercall_t *)hvm_vcpu_op,
1990 HYPERCALL(xen_version),
1991 HYPERCALL(event_channel_op),
1992 HYPERCALL(sched_op),
1993 HYPERCALL(hvm_op)
1994 };
1996 #else /* defined(__x86_64__) */
1998 static long hvm_memory_op_compat32(int cmd, XEN_GUEST_HANDLE(void) arg)
2000 long rc = compat_memory_op(cmd, arg);
2001 if ( (cmd & MEMOP_CMD_MASK) == XENMEM_decrease_reservation )
2002 current->domain->arch.hvm_domain.qemu_mapcache_invalidate = 1;
2003 return rc;
2006 static long hvm_vcpu_op_compat32(
2007 int cmd, int vcpuid, XEN_GUEST_HANDLE(void) arg)
2009 long rc;
2011 switch ( cmd )
2013 case VCPUOP_register_runstate_memory_area:
2014 case VCPUOP_get_runstate_info:
2015 rc = compat_vcpu_op(cmd, vcpuid, arg);
2016 break;
2017 default:
2018 rc = -ENOSYS;
2019 break;
2022 return rc;
2025 static hvm_hypercall_t *hvm_hypercall64_table[NR_hypercalls] = {
2026 [ __HYPERVISOR_memory_op ] = (hvm_hypercall_t *)hvm_memory_op,
2027 [ __HYPERVISOR_grant_table_op ] = (hvm_hypercall_t *)hvm_grant_table_op,
2028 [ __HYPERVISOR_vcpu_op ] = (hvm_hypercall_t *)hvm_vcpu_op,
2029 HYPERCALL(xen_version),
2030 HYPERCALL(event_channel_op),
2031 HYPERCALL(sched_op),
2032 HYPERCALL(hvm_op)
2033 };
2035 static hvm_hypercall_t *hvm_hypercall32_table[NR_hypercalls] = {
2036 [ __HYPERVISOR_memory_op ] = (hvm_hypercall_t *)hvm_memory_op_compat32,
2037 [ __HYPERVISOR_grant_table_op ] = (hvm_hypercall_t *)hvm_grant_table_op,
2038 [ __HYPERVISOR_vcpu_op ] = (hvm_hypercall_t *)hvm_vcpu_op_compat32,
2039 HYPERCALL(xen_version),
2040 HYPERCALL(event_channel_op),
2041 HYPERCALL(sched_op),
2042 HYPERCALL(hvm_op)
2043 };
2045 #endif /* defined(__x86_64__) */
2047 int hvm_do_hypercall(struct cpu_user_regs *regs)
2049 struct vcpu *curr = current;
2050 struct segment_register sreg;
2051 int mode = hvm_guest_x86_mode(curr);
2052 uint32_t eax = regs->eax;
2054 switch ( mode )
2056 #ifdef __x86_64__
2057 case 8:
2058 #endif
2059 case 4:
2060 case 2:
2061 hvm_get_segment_register(curr, x86_seg_ss, &sreg);
2062 if ( unlikely(sreg.attr.fields.dpl == 3) )
2064 default:
2065 regs->eax = -EPERM;
2066 return HVM_HCALL_completed;
2068 case 0:
2069 break;
2072 if ( (eax & 0x80000000) && is_viridian_domain(curr->domain) )
2073 return viridian_hypercall(regs);
2075 if ( (eax >= NR_hypercalls) || !hvm_hypercall32_table[eax] )
2077 regs->eax = -ENOSYS;
2078 return HVM_HCALL_completed;
2081 this_cpu(hc_preempted) = 0;
2083 #ifdef __x86_64__
2084 if ( mode == 8 )
2086 HVM_DBG_LOG(DBG_LEVEL_HCALL, "hcall%u(%lx, %lx, %lx, %lx, %lx)", eax,
2087 regs->rdi, regs->rsi, regs->rdx, regs->r10, regs->r8);
2089 this_cpu(hvm_64bit_hcall) = 1;
2090 regs->rax = hvm_hypercall64_table[eax](regs->rdi,
2091 regs->rsi,
2092 regs->rdx,
2093 regs->r10,
2094 regs->r8);
2095 this_cpu(hvm_64bit_hcall) = 0;
2097 else
2098 #endif
2100 HVM_DBG_LOG(DBG_LEVEL_HCALL, "hcall%u(%x, %x, %x, %x, %x)", eax,
2101 (uint32_t)regs->ebx, (uint32_t)regs->ecx,
2102 (uint32_t)regs->edx, (uint32_t)regs->esi,
2103 (uint32_t)regs->edi);
2105 regs->eax = hvm_hypercall32_table[eax]((uint32_t)regs->ebx,
2106 (uint32_t)regs->ecx,
2107 (uint32_t)regs->edx,
2108 (uint32_t)regs->esi,
2109 (uint32_t)regs->edi);
2112 HVM_DBG_LOG(DBG_LEVEL_HCALL, "hcall%u -> %lx",
2113 eax, (unsigned long)regs->eax);
2115 if ( this_cpu(hc_preempted) )
2116 return HVM_HCALL_preempted;
2118 if ( unlikely(curr->domain->arch.hvm_domain.qemu_mapcache_invalidate) &&
2119 test_and_clear_bool(curr->domain->arch.hvm_domain.
2120 qemu_mapcache_invalidate) )
2121 return HVM_HCALL_invalidate;
2123 return HVM_HCALL_completed;
2126 static void hvm_latch_shinfo_size(struct domain *d)
2128 /*
2129 * Called from operations which are among the very first executed by
2130 * PV drivers on initialisation or after save/restore. These are sensible
2131 * points at which to sample the execution mode of the guest and latch
2132 * 32- or 64-bit format for shared state.
2133 */
2134 if ( current->domain == d )
2135 d->arch.has_32bit_shinfo = (hvm_guest_x86_mode(current) != 8);
2138 /* Initialise a hypercall transfer page for a VMX domain using
2139 paravirtualised drivers. */
2140 void hvm_hypercall_page_initialise(struct domain *d,
2141 void *hypercall_page)
2143 hvm_latch_shinfo_size(d);
2144 hvm_funcs.init_hypercall_page(d, hypercall_page);
2147 static int hvmop_set_pci_intx_level(
2148 XEN_GUEST_HANDLE(xen_hvm_set_pci_intx_level_t) uop)
2150 struct xen_hvm_set_pci_intx_level op;
2151 struct domain *d;
2152 int rc;
2154 if ( copy_from_guest(&op, uop, 1) )
2155 return -EFAULT;
2157 if ( (op.domain > 0) || (op.bus > 0) || (op.device > 31) || (op.intx > 3) )
2158 return -EINVAL;
2160 d = rcu_lock_domain_by_id(op.domid);
2161 if ( d == NULL )
2162 return -ESRCH;
2164 rc = -EPERM;
2165 if ( !IS_PRIV_FOR(current->domain, d) )
2166 goto out;
2168 rc = -EINVAL;
2169 if ( !is_hvm_domain(d) )
2170 goto out;
2172 rc = xsm_hvm_set_pci_intx_level(d);
2173 if ( rc )
2174 goto out;
2176 rc = 0;
2177 switch ( op.level )
2179 case 0:
2180 hvm_pci_intx_deassert(d, op.device, op.intx);
2181 break;
2182 case 1:
2183 hvm_pci_intx_assert(d, op.device, op.intx);
2184 break;
2185 default:
2186 rc = -EINVAL;
2187 break;
2190 out:
2191 rcu_unlock_domain(d);
2192 return rc;
2195 void hvm_vcpu_reset_state(struct vcpu *v, uint16_t cs, uint16_t ip)
2197 struct domain *d = v->domain;
2198 struct vcpu_guest_context *ctxt;
2199 struct segment_register reg;
2201 BUG_ON(vcpu_runnable(v));
2203 domain_lock(d);
2205 if ( v->is_initialised )
2206 goto out;
2208 if ( !paging_mode_hap(d) )
2210 if ( v->arch.hvm_vcpu.guest_cr[0] & X86_CR0_PG )
2211 put_page(pagetable_get_page(v->arch.guest_table));
2212 v->arch.guest_table = pagetable_null();
2215 ctxt = &v->arch.guest_context;
2216 memset(ctxt, 0, sizeof(*ctxt));
2217 ctxt->flags = VGCF_online;
2218 ctxt->user_regs.eflags = 2;
2219 ctxt->user_regs.edx = 0x00000f00;
2220 ctxt->user_regs.eip = ip;
2222 v->arch.hvm_vcpu.guest_cr[0] = X86_CR0_ET;
2223 hvm_update_guest_cr(v, 0);
2225 v->arch.hvm_vcpu.guest_cr[2] = 0;
2226 hvm_update_guest_cr(v, 2);
2228 v->arch.hvm_vcpu.guest_cr[3] = 0;
2229 hvm_update_guest_cr(v, 3);
2231 v->arch.hvm_vcpu.guest_cr[4] = 0;
2232 hvm_update_guest_cr(v, 4);
2234 v->arch.hvm_vcpu.guest_efer = 0;
2235 hvm_update_guest_efer(v);
2237 reg.sel = cs;
2238 reg.base = (uint32_t)reg.sel << 4;
2239 reg.limit = 0xffff;
2240 reg.attr.bytes = 0x09b;
2241 hvm_set_segment_register(v, x86_seg_cs, &reg);
2243 reg.sel = reg.base = 0;
2244 reg.limit = 0xffff;
2245 reg.attr.bytes = 0x093;
2246 hvm_set_segment_register(v, x86_seg_ds, &reg);
2247 hvm_set_segment_register(v, x86_seg_es, &reg);
2248 hvm_set_segment_register(v, x86_seg_fs, &reg);
2249 hvm_set_segment_register(v, x86_seg_gs, &reg);
2250 hvm_set_segment_register(v, x86_seg_ss, &reg);
2252 reg.attr.bytes = 0x82; /* LDT */
2253 hvm_set_segment_register(v, x86_seg_ldtr, &reg);
2255 reg.attr.bytes = 0x8b; /* 32-bit TSS (busy) */
2256 hvm_set_segment_register(v, x86_seg_tr, &reg);
2258 reg.attr.bytes = 0;
2259 hvm_set_segment_register(v, x86_seg_gdtr, &reg);
2260 hvm_set_segment_register(v, x86_seg_idtr, &reg);
2262 /* Sync AP's TSC with BSP's. */
2263 v->arch.hvm_vcpu.cache_tsc_offset =
2264 v->domain->vcpu[0]->arch.hvm_vcpu.cache_tsc_offset;
2265 hvm_funcs.set_tsc_offset(v, v->arch.hvm_vcpu.cache_tsc_offset);
2267 paging_update_paging_modes(v);
2269 v->arch.flags |= TF_kernel_mode;
2270 v->is_initialised = 1;
2271 clear_bit(_VPF_down, &v->pause_flags);
2273 out:
2274 domain_unlock(d);
2277 static void hvm_s3_suspend(struct domain *d)
2279 struct vcpu *v;
2281 domain_pause(d);
2282 domain_lock(d);
2284 if ( d->is_dying || (d->vcpu[0] == NULL) ||
2285 test_and_set_bool(d->arch.hvm_domain.is_s3_suspended) )
2287 domain_unlock(d);
2288 domain_unpause(d);
2289 return;
2292 for_each_vcpu ( d, v )
2294 vlapic_reset(vcpu_vlapic(v));
2295 vcpu_reset(v);
2298 vpic_reset(d);
2299 vioapic_reset(d);
2300 pit_reset(d);
2301 rtc_reset(d);
2302 pmtimer_reset(d);
2303 hpet_reset(d);
2305 hvm_vcpu_reset_state(d->vcpu[0], 0xf000, 0xfff0);
2307 domain_unlock(d);
2310 static void hvm_s3_resume(struct domain *d)
2312 if ( test_and_clear_bool(d->arch.hvm_domain.is_s3_suspended) )
2313 domain_unpause(d);
2316 static int hvmop_set_isa_irq_level(
2317 XEN_GUEST_HANDLE(xen_hvm_set_isa_irq_level_t) uop)
2319 struct xen_hvm_set_isa_irq_level op;
2320 struct domain *d;
2321 int rc;
2323 if ( copy_from_guest(&op, uop, 1) )
2324 return -EFAULT;
2326 if ( op.isa_irq > 15 )
2327 return -EINVAL;
2329 d = rcu_lock_domain_by_id(op.domid);
2330 if ( d == NULL )
2331 return -ESRCH;
2333 rc = -EPERM;
2334 if ( !IS_PRIV_FOR(current->domain, d) )
2335 goto out;
2337 rc = -EINVAL;
2338 if ( !is_hvm_domain(d) )
2339 goto out;
2341 rc = xsm_hvm_set_isa_irq_level(d);
2342 if ( rc )
2343 goto out;
2345 rc = 0;
2346 switch ( op.level )
2348 case 0:
2349 hvm_isa_irq_deassert(d, op.isa_irq);
2350 break;
2351 case 1:
2352 hvm_isa_irq_assert(d, op.isa_irq);
2353 break;
2354 default:
2355 rc = -EINVAL;
2356 break;
2359 out:
2360 rcu_unlock_domain(d);
2361 return rc;
2364 static int hvmop_set_pci_link_route(
2365 XEN_GUEST_HANDLE(xen_hvm_set_pci_link_route_t) uop)
2367 struct xen_hvm_set_pci_link_route op;
2368 struct domain *d;
2369 int rc;
2371 if ( copy_from_guest(&op, uop, 1) )
2372 return -EFAULT;
2374 if ( (op.link > 3) || (op.isa_irq > 15) )
2375 return -EINVAL;
2377 d = rcu_lock_domain_by_id(op.domid);
2378 if ( d == NULL )
2379 return -ESRCH;
2381 rc = -EPERM;
2382 if ( !IS_PRIV_FOR(current->domain, d) )
2383 goto out;
2385 rc = -EINVAL;
2386 if ( !is_hvm_domain(d) )
2387 goto out;
2389 rc = xsm_hvm_set_pci_link_route(d);
2390 if ( rc )
2391 goto out;
2393 rc = 0;
2394 hvm_set_pci_link_route(d, op.link, op.isa_irq);
2396 out:
2397 rcu_unlock_domain(d);
2398 return rc;
2401 static int hvmop_flush_tlb_all(void)
2403 struct domain *d = current->domain;
2404 struct vcpu *v;
2406 if ( !is_hvm_domain(d) )
2407 return -EINVAL;
2409 /* Avoid deadlock if more than one vcpu tries this at the same time. */
2410 if ( !spin_trylock(&d->hypercall_deadlock_mutex) )
2411 return -EAGAIN;
2413 /* Pause all other vcpus. */
2414 for_each_vcpu ( d, v )
2415 if ( v != current )
2416 vcpu_pause_nosync(v);
2418 /* Now that all VCPUs are signalled to deschedule, we wait... */
2419 for_each_vcpu ( d, v )
2420 if ( v != current )
2421 while ( !vcpu_runnable(v) && v->is_running )
2422 cpu_relax();
2424 /* All other vcpus are paused, safe to unlock now. */
2425 spin_unlock(&d->hypercall_deadlock_mutex);
2427 /* Flush paging-mode soft state (e.g., va->gfn cache; PAE PDPE cache). */
2428 for_each_vcpu ( d, v )
2429 paging_update_cr3(v);
2431 /* Flush all dirty TLBs. */
2432 flush_tlb_mask(&d->domain_dirty_cpumask);
2434 /* Done. */
2435 for_each_vcpu ( d, v )
2436 if ( v != current )
2437 vcpu_unpause(v);
2439 return 0;
2442 long do_hvm_op(unsigned long op, XEN_GUEST_HANDLE(void) arg)
2445 struct domain *curr_d = current->domain;
2446 long rc = 0;
2448 switch ( op )
2450 case HVMOP_set_param:
2451 case HVMOP_get_param:
2453 struct xen_hvm_param a;
2454 struct hvm_ioreq_page *iorp;
2455 struct domain *d;
2456 struct vcpu *v;
2458 if ( copy_from_guest(&a, arg, 1) )
2459 return -EFAULT;
2461 if ( a.index >= HVM_NR_PARAMS )
2462 return -EINVAL;
2464 rc = rcu_lock_target_domain_by_id(a.domid, &d);
2465 if ( rc != 0 )
2466 return rc;
2468 rc = -EINVAL;
2469 if ( !is_hvm_domain(d) )
2470 goto param_fail;
2472 rc = xsm_hvm_param(d, op);
2473 if ( rc )
2474 goto param_fail;
2476 if ( op == HVMOP_set_param )
2478 rc = 0;
2480 switch ( a.index )
2482 case HVM_PARAM_IOREQ_PFN:
2483 iorp = &d->arch.hvm_domain.ioreq;
2484 if ( (rc = hvm_set_ioreq_page(d, iorp, a.value)) != 0 )
2485 break;
2486 spin_lock(&iorp->lock);
2487 if ( iorp->va != NULL )
2488 /* Initialise evtchn port info if VCPUs already created. */
2489 for_each_vcpu ( d, v )
2490 get_ioreq(v)->vp_eport = v->arch.hvm_vcpu.xen_port;
2491 spin_unlock(&iorp->lock);
2492 break;
2493 case HVM_PARAM_BUFIOREQ_PFN:
2494 iorp = &d->arch.hvm_domain.buf_ioreq;
2495 rc = hvm_set_ioreq_page(d, iorp, a.value);
2496 break;
2497 case HVM_PARAM_CALLBACK_IRQ:
2498 hvm_set_callback_via(d, a.value);
2499 hvm_latch_shinfo_size(d);
2500 break;
2501 case HVM_PARAM_TIMER_MODE:
2502 if ( a.value > HVMPTM_one_missed_tick_pending )
2503 rc = -EINVAL;
2504 break;
2505 case HVM_PARAM_VIRIDIAN:
2506 if ( a.value > 1 )
2507 rc = -EINVAL;
2508 break;
2509 case HVM_PARAM_IDENT_PT:
2510 /* Not reflexive, as we must domain_pause(). */
2511 rc = -EPERM;
2512 if ( curr_d == d )
2513 break;
2515 rc = -EINVAL;
2516 if ( d->arch.hvm_domain.params[a.index] != 0 )
2517 break;
2519 rc = 0;
2520 if ( !paging_mode_hap(d) )
2521 break;
2523 /*
2524 * Update GUEST_CR3 in each VMCS to point at identity map.
2525 * All foreign updates to guest state must synchronise on
2526 * the domctl_lock.
2527 */
2528 rc = -EAGAIN;
2529 if ( !domctl_lock_acquire() )
2530 break;
2532 rc = 0;
2533 domain_pause(d);
2534 d->arch.hvm_domain.params[a.index] = a.value;
2535 for_each_vcpu ( d, v )
2536 paging_update_cr3(v);
2537 domain_unpause(d);
2539 domctl_lock_release();
2540 break;
2541 case HVM_PARAM_DM_DOMAIN:
2542 /* Not reflexive, as we must domain_pause(). */
2543 rc = -EPERM;
2544 if ( curr_d == d )
2545 break;
2547 if ( a.value == DOMID_SELF )
2548 a.value = curr_d->domain_id;
2550 rc = 0;
2551 domain_pause(d); /* safe to change per-vcpu xen_port */
2552 iorp = &d->arch.hvm_domain.ioreq;
2553 for_each_vcpu ( d, v )
2555 int old_port, new_port;
2556 new_port = alloc_unbound_xen_event_channel(v, a.value);
2557 if ( new_port < 0 )
2559 rc = new_port;
2560 break;
2562 /* xchg() ensures that only we free_xen_event_channel() */
2563 old_port = xchg(&v->arch.hvm_vcpu.xen_port, new_port);
2564 free_xen_event_channel(v, old_port);
2565 spin_lock(&iorp->lock);
2566 if ( iorp->va != NULL )
2567 get_ioreq(v)->vp_eport = v->arch.hvm_vcpu.xen_port;
2568 spin_unlock(&iorp->lock);
2570 domain_unpause(d);
2571 break;
2572 case HVM_PARAM_ACPI_S_STATE:
2573 /* Not reflexive, as we must domain_pause(). */
2574 rc = -EPERM;
2575 if ( curr_d == d )
2576 break;
2578 rc = 0;
2579 if ( a.value == 3 )
2580 hvm_s3_suspend(d);
2581 else if ( a.value == 0 )
2582 hvm_s3_resume(d);
2583 else
2584 rc = -EINVAL;
2586 break;
2589 if ( rc == 0 )
2590 d->arch.hvm_domain.params[a.index] = a.value;
2592 else
2594 switch ( a.index )
2596 case HVM_PARAM_ACPI_S_STATE:
2597 a.value = d->arch.hvm_domain.is_s3_suspended ? 3 : 0;
2598 break;
2599 default:
2600 a.value = d->arch.hvm_domain.params[a.index];
2601 break;
2603 rc = copy_to_guest(arg, &a, 1) ? -EFAULT : 0;
2606 HVM_DBG_LOG(DBG_LEVEL_HCALL, "%s param %u = %"PRIx64,
2607 op == HVMOP_set_param ? "set" : "get",
2608 a.index, a.value);
2610 param_fail:
2611 rcu_unlock_domain(d);
2612 break;
2615 case HVMOP_set_pci_intx_level:
2616 rc = hvmop_set_pci_intx_level(
2617 guest_handle_cast(arg, xen_hvm_set_pci_intx_level_t));
2618 break;
2620 case HVMOP_set_isa_irq_level:
2621 rc = hvmop_set_isa_irq_level(
2622 guest_handle_cast(arg, xen_hvm_set_isa_irq_level_t));
2623 break;
2625 case HVMOP_set_pci_link_route:
2626 rc = hvmop_set_pci_link_route(
2627 guest_handle_cast(arg, xen_hvm_set_pci_link_route_t));
2628 break;
2630 case HVMOP_flush_tlbs:
2631 rc = guest_handle_is_null(arg) ? hvmop_flush_tlb_all() : -ENOSYS;
2632 break;
2634 case HVMOP_track_dirty_vram:
2636 struct xen_hvm_track_dirty_vram a;
2637 struct domain *d;
2639 if ( copy_from_guest(&a, arg, 1) )
2640 return -EFAULT;
2642 rc = rcu_lock_target_domain_by_id(a.domid, &d);
2643 if ( rc != 0 )
2644 return rc;
2646 rc = -EINVAL;
2647 if ( !is_hvm_domain(d) )
2648 goto param_fail2;
2650 rc = xsm_hvm_param(d, op);
2651 if ( rc )
2652 goto param_fail2;
2654 rc = -ESRCH;
2655 if ( d->is_dying )
2656 goto param_fail2;
2658 rc = -EINVAL;
2659 if ( d->vcpu[0] == NULL )
2660 goto param_fail2;
2662 if ( shadow_mode_enabled(d) )
2663 rc = shadow_track_dirty_vram(d, a.first_pfn, a.nr, a.dirty_bitmap);
2664 else
2665 rc = hap_track_dirty_vram(d, a.first_pfn, a.nr, a.dirty_bitmap);
2667 param_fail2:
2668 rcu_unlock_domain(d);
2669 break;
2672 case HVMOP_modified_memory:
2674 struct xen_hvm_modified_memory a;
2675 struct domain *d;
2676 unsigned long pfn;
2678 if ( copy_from_guest(&a, arg, 1) )
2679 return -EFAULT;
2681 rc = rcu_lock_target_domain_by_id(a.domid, &d);
2682 if ( rc != 0 )
2683 return rc;
2685 rc = -EINVAL;
2686 if ( !is_hvm_domain(d) )
2687 goto param_fail3;
2689 rc = xsm_hvm_param(d, op);
2690 if ( rc )
2691 goto param_fail3;
2693 rc = -EINVAL;
2694 if ( (a.first_pfn > domain_get_maximum_gpfn(d)) ||
2695 ((a.first_pfn + a.nr - 1) < a.first_pfn) ||
2696 ((a.first_pfn + a.nr - 1) > domain_get_maximum_gpfn(d)) )
2697 goto param_fail3;
2699 rc = 0;
2700 if ( !paging_mode_log_dirty(d) )
2701 goto param_fail3;
2703 for ( pfn = a.first_pfn; pfn < a.first_pfn + a.nr; pfn++ )
2705 p2m_type_t t;
2706 mfn_t mfn = gfn_to_mfn(d, pfn, &t);
2707 if ( mfn_x(mfn) != INVALID_MFN )
2709 paging_mark_dirty(d, mfn_x(mfn));
2710 /* These are most probably not page tables any more */
2711 /* don't take a long time and don't die either */
2712 sh_remove_shadows(d->vcpu[0], mfn, 1, 0);
2716 param_fail3:
2717 rcu_unlock_domain(d);
2718 break;
2721 case HVMOP_set_mem_type:
2723 struct xen_hvm_set_mem_type a;
2724 struct domain *d;
2725 unsigned long pfn;
2727 /* Interface types to internal p2m types */
2728 p2m_type_t memtype[] = {
2729 p2m_ram_rw, /* HVMMEM_ram_rw */
2730 p2m_ram_ro, /* HVMMEM_ram_ro */
2731 p2m_mmio_dm /* HVMMEM_mmio_dm */
2732 };
2734 if ( copy_from_guest(&a, arg, 1) )
2735 return -EFAULT;
2737 rc = rcu_lock_target_domain_by_id(a.domid, &d);
2738 if ( rc != 0 )
2739 return rc;
2741 rc = -EINVAL;
2742 if ( !is_hvm_domain(d) )
2743 goto param_fail4;
2745 rc = -EINVAL;
2746 if ( (a.first_pfn > domain_get_maximum_gpfn(d)) ||
2747 ((a.first_pfn + a.nr - 1) < a.first_pfn) ||
2748 ((a.first_pfn + a.nr - 1) > domain_get_maximum_gpfn(d)) )
2749 goto param_fail4;
2751 if ( a.hvmmem_type >= ARRAY_SIZE(memtype) )
2752 goto param_fail4;
2754 rc = 0;
2756 for ( pfn = a.first_pfn; pfn < a.first_pfn + a.nr; pfn++ )
2758 p2m_type_t t;
2759 mfn_t mfn;
2760 mfn = gfn_to_mfn(d, pfn, &t);
2761 p2m_change_type(d, pfn, t, memtype[a.hvmmem_type]);
2764 param_fail4:
2765 rcu_unlock_domain(d);
2766 break;
2769 default:
2771 gdprintk(XENLOG_WARNING, "Bad HVM op %ld.\n", op);
2772 rc = -ENOSYS;
2773 break;
2777 if ( rc == -EAGAIN )
2778 rc = hypercall_create_continuation(
2779 __HYPERVISOR_hvm_op, "lh", op, arg);
2781 return rc;
2784 int hvm_debug_op(struct vcpu *v, int32_t op)
2786 int rc;
2788 switch ( op )
2790 case XEN_DOMCTL_DEBUG_OP_SINGLE_STEP_ON:
2791 case XEN_DOMCTL_DEBUG_OP_SINGLE_STEP_OFF:
2792 rc = -ENOSYS;
2793 if ( !cpu_has_monitor_trap_flag )
2794 break;
2795 rc = 0;
2796 vcpu_pause(v);
2797 v->arch.hvm_vcpu.single_step =
2798 (op == XEN_DOMCTL_DEBUG_OP_SINGLE_STEP_ON);
2799 vcpu_unpause(v); /* guest will latch new state */
2800 break;
2801 default:
2802 rc = -ENOSYS;
2803 break;
2806 return rc;
2810 /*
2811 * Local variables:
2812 * mode: C
2813 * c-set-style: "BSD"
2814 * c-basic-offset: 4
2815 * tab-width: 4
2816 * indent-tabs-mode: nil
2817 * End:
2818 */