ia64/xen-unstable

view xen/arch/ia64/linux-xen/setup.c @ 14709:770c465344d3

[IA64] Auto setup serial console on PRIMEQUEST

Signed-off-by: Akio Takebe <takebe_akio@jp.fujitsu.com>
author Alex Williamson <alex.williamson@hp.com>
date Thu Apr 05 09:13:16 2007 -0600 (2007-04-05)
parents eb6c19ed6e67
children 9ec7dadc98ba
line source
1 /*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 *
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
24 */
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
29 #include <linux/acpi.h>
30 #include <linux/bootmem.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
33 #include <linux/kernel.h>
34 #include <linux/shutdown.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/string.h>
38 #include <linux/threads.h>
39 #include <linux/tty.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
44 #ifndef XEN
45 #include <linux/platform.h>
46 #include <linux/pm.h>
47 #endif
49 #include <asm/ia32.h>
50 #include <asm/machvec.h>
51 #include <asm/mca.h>
52 #include <asm/meminit.h>
53 #include <asm/page.h>
54 #include <asm/patch.h>
55 #include <asm/pgtable.h>
56 #include <asm/processor.h>
57 #include <asm/sal.h>
58 #include <asm/sections.h>
59 #include <asm/serial.h>
60 #include <asm/setup.h>
61 #include <asm/smp.h>
62 #include <asm/system.h>
63 #include <asm/unistd.h>
64 #ifdef XEN
65 #include <asm/vmx.h>
66 #include <asm/io.h>
67 #endif
69 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
70 # error "struct cpuinfo_ia64 too big!"
71 #endif
73 #ifdef CONFIG_SMP
74 unsigned long __per_cpu_offset[NR_CPUS];
75 EXPORT_SYMBOL(__per_cpu_offset);
76 #endif
78 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
79 #ifdef XEN
80 DEFINE_PER_CPU(cpu_kr_ia64_t, cpu_kr);
81 #endif
82 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
83 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
84 unsigned long ia64_cycles_per_usec;
85 struct ia64_boot_param *ia64_boot_param;
86 struct screen_info screen_info;
87 unsigned long vga_console_iobase;
88 unsigned long vga_console_membase;
90 unsigned long ia64_max_cacheline_size;
91 unsigned long ia64_iobase; /* virtual address for I/O accesses */
92 EXPORT_SYMBOL(ia64_iobase);
93 struct io_space io_space[MAX_IO_SPACES];
94 EXPORT_SYMBOL(io_space);
95 unsigned int num_io_spaces;
97 #ifdef XEN
98 extern void early_cmdline_parse(char **);
99 #endif
101 /*
102 * "flush_icache_range()" needs to know what processor dependent stride size to use
103 * when it makes i-cache(s) coherent with d-caches.
104 */
105 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
106 unsigned long ia64_i_cache_stride_shift = ~0;
108 #ifdef XEN
109 #define D_CACHE_STRIDE_SHIFT 5 /* Safest. */
110 unsigned long ia64_d_cache_stride_shift = ~0;
111 #endif
113 /*
114 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
115 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
116 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
117 * address of the second buffer must be aligned to (merge_mask+1) in order to be
118 * mergeable). By default, we assume there is no I/O MMU which can merge physically
119 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
120 * page-size of 2^64.
121 */
122 unsigned long ia64_max_iommu_merge_mask = ~0UL;
123 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
125 /*
126 * We use a special marker for the end of memory and it uses the extra (+1) slot
127 */
128 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
129 int num_rsvd_regions;
132 /*
133 * Filter incoming memory segments based on the primitive map created from the boot
134 * parameters. Segments contained in the map are removed from the memory ranges. A
135 * caller-specified function is called with the memory ranges that remain after filtering.
136 * This routine does not assume the incoming segments are sorted.
137 */
138 int
139 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
140 {
141 unsigned long range_start, range_end, prev_start;
142 void (*func)(unsigned long, unsigned long, int);
143 int i;
145 #if IGNORE_PFN0
146 if (start == PAGE_OFFSET) {
147 printk(KERN_WARNING "warning: skipping physical page 0\n");
148 start += PAGE_SIZE;
149 if (start >= end) return 0;
150 }
151 #endif
152 /*
153 * lowest possible address(walker uses virtual)
154 */
155 prev_start = PAGE_OFFSET;
156 func = arg;
158 for (i = 0; i < num_rsvd_regions; ++i) {
159 range_start = max(start, prev_start);
160 range_end = min(end, rsvd_region[i].start);
162 if (range_start < range_end)
163 #ifdef XEN
164 {
165 /* init_boot_pages requires "ps, pe" */
166 printk("Init boot pages: 0x%lx -> 0x%lx.\n",
167 __pa(range_start), __pa(range_end));
168 (*func)(__pa(range_start), __pa(range_end), 0);
169 }
170 #else
171 call_pernode_memory(__pa(range_start), range_end - range_start, func);
172 #endif
174 /* nothing more available in this segment */
175 if (range_end == end) return 0;
177 prev_start = rsvd_region[i].end;
178 }
179 /* end of memory marker allows full processing inside loop body */
180 return 0;
181 }
183 static void
184 sort_regions (struct rsvd_region *rsvd_region, int max)
185 {
186 int j;
188 /* simple bubble sorting */
189 while (max--) {
190 for (j = 0; j < max; ++j) {
191 if (rsvd_region[j].start > rsvd_region[j+1].start) {
192 struct rsvd_region tmp;
193 tmp = rsvd_region[j];
194 rsvd_region[j] = rsvd_region[j + 1];
195 rsvd_region[j + 1] = tmp;
196 }
197 }
198 }
199 }
201 /**
202 * reserve_memory - setup reserved memory areas
203 *
204 * Setup the reserved memory areas set aside for the boot parameters,
205 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
206 * see include/asm-ia64/meminit.h if you need to define more.
207 */
208 void
209 reserve_memory (void)
210 {
211 int n = 0;
213 /*
214 * none of the entries in this table overlap
215 */
216 rsvd_region[n].start = (unsigned long) ia64_boot_param;
217 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
218 n++;
220 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
221 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
222 n++;
224 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
225 rsvd_region[n].end = (rsvd_region[n].start
226 + strlen(__va(ia64_boot_param->command_line)) + 1);
227 n++;
229 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
230 #ifdef XEN
231 /* Reserve xen image/bitmap/xen-heap */
232 rsvd_region[n].end = rsvd_region[n].start + xenheap_size;
233 #else
234 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
235 #endif
236 n++;
238 #ifdef XEN
239 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->domain_start);
240 rsvd_region[n].end = (rsvd_region[n].start + ia64_boot_param->domain_size);
241 n++;
242 #endif
244 #if defined(XEN)||defined(CONFIG_BLK_DEV_INITRD)
245 if (ia64_boot_param->initrd_start) {
246 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
247 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
248 n++;
249 }
250 #endif
252 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
253 n++;
255 /* end of memory marker */
256 rsvd_region[n].start = ~0UL;
257 rsvd_region[n].end = ~0UL;
258 n++;
260 num_rsvd_regions = n;
262 sort_regions(rsvd_region, num_rsvd_regions);
263 }
265 /**
266 * find_initrd - get initrd parameters from the boot parameter structure
267 *
268 * Grab the initrd start and end from the boot parameter struct given us by
269 * the boot loader.
270 */
271 void
272 find_initrd (void)
273 {
274 #ifdef CONFIG_BLK_DEV_INITRD
275 if (ia64_boot_param->initrd_start) {
276 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
277 initrd_end = initrd_start+ia64_boot_param->initrd_size;
279 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
280 initrd_start, ia64_boot_param->initrd_size);
281 }
282 #endif
283 }
285 static void __init
286 io_port_init (void)
287 {
288 extern unsigned long ia64_iobase;
289 unsigned long phys_iobase;
291 /*
292 * Set `iobase' to the appropriate address in region 6 (uncached access range).
293 *
294 * The EFI memory map is the "preferred" location to get the I/O port space base,
295 * rather the relying on AR.KR0. This should become more clear in future SAL
296 * specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is
297 * found in the memory map.
298 */
299 phys_iobase = efi_get_iobase();
300 if (phys_iobase)
301 /* set AR.KR0 since this is all we use it for anyway */
302 ia64_set_kr(IA64_KR_IO_BASE, phys_iobase);
303 else {
304 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
305 printk(KERN_INFO "No I/O port range found in EFI memory map, falling back "
306 "to AR.KR0\n");
307 printk(KERN_INFO "I/O port base = 0x%lx\n", phys_iobase);
308 }
309 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
311 /* setup legacy IO port space */
312 io_space[0].mmio_base = ia64_iobase;
313 io_space[0].sparse = 1;
314 num_io_spaces = 1;
315 }
317 #ifdef XEN
318 static int __init
319 acpi_oem_console_setup(void)
320 {
321 extern struct ns16550_defaults ns16550_com1;
322 efi_system_table_t *systab;
323 efi_config_table_t *tables;
324 struct acpi20_table_rsdp *rsdp = NULL;
325 struct acpi_table_xsdt *xsdt;
326 struct acpi_table_header *hdr;
327 int i;
329 /* Don't duplicate setup if an HCDP table is present */
330 if (efi.hcdp)
331 return -ENODEV;
333 /* Manually walk firmware provided tables to get to the XSDT. */
334 systab = __va(ia64_boot_param->efi_systab);
336 if (!systab || systab->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE)
337 return -ENODEV;
339 tables = __va(systab->tables);
341 for (i = 0 ; i < (int)systab->nr_tables && !rsdp ; i++) {
342 if (efi_guidcmp(tables[i].guid, ACPI_20_TABLE_GUID) == 0)
343 rsdp =
344 (struct acpi20_table_rsdp *)__va(tables[i].table);
345 }
347 if (!rsdp || strncmp(rsdp->signature, RSDP_SIG, sizeof(RSDP_SIG) - 1))
348 return -ENODEV;
350 xsdt = (struct acpi_table_xsdt *)__va(rsdp->xsdt_address);
351 hdr = &xsdt->header;
353 if (strncmp(hdr->signature, XSDT_SIG, sizeof(XSDT_SIG) - 1))
354 return -ENODEV;
356 /* Looking for Fujitsu PRIMEQUEST systems */
357 if (!strncmp(hdr->oem_id, "FUJITSPQ", 8) &&
358 (!strncmp(hdr->oem_table_id, "PQ", 2))){
359 ns16550_com1.baud = BAUD_AUTO;
360 ns16550_com1.io_base = 0x3f8;
361 ns16550_com1.irq = 48;
362 return 0;
363 }
365 /*
366 * Looking for Intel Tiger systems
367 * Tiger 2: SR870BH2
368 * Tiger 4: SR870BN4
369 */
370 if (strncmp(hdr->oem_id, "INTEL", 5) ||
371 (!strncmp(hdr->oem_table_id, "SR870BH2", 8) &&
372 !strncmp(hdr->oem_table_id, "SR870BN4", 8)))
373 return -ENODEV;
375 ns16550_com1.baud = BAUD_AUTO;
376 ns16550_com1.io_base = 0x2f8;
377 ns16550_com1.irq = 3;
379 return 0;
380 }
381 #endif
383 /**
384 * early_console_setup - setup debugging console
385 *
386 * Consoles started here require little enough setup that we can start using
387 * them very early in the boot process, either right after the machine
388 * vector initialization, or even before if the drivers can detect their hw.
389 *
390 * Returns non-zero if a console couldn't be setup.
391 */
392 static inline int __init
393 early_console_setup (char *cmdline)
394 {
395 int earlycons = 0;
397 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
398 {
399 extern int sn_serial_console_early_setup(void);
400 if (!sn_serial_console_early_setup())
401 earlycons++;
402 }
403 #endif
404 #ifdef CONFIG_EFI_PCDP
405 if (!efi_setup_pcdp_console(cmdline))
406 earlycons++;
407 #endif
408 #ifdef CONFIG_SERIAL_8250_CONSOLE
409 if (!early_serial_console_init(cmdline))
410 earlycons++;
411 #endif
413 #ifdef XEN
414 if (!acpi_oem_console_setup())
415 earlycons++;
416 #endif
417 return (earlycons) ? 0 : -1;
418 }
420 static inline void
421 mark_bsp_online (void)
422 {
423 #ifdef CONFIG_SMP
424 /* If we register an early console, allow CPU 0 to printk */
425 cpu_set(smp_processor_id(), cpu_online_map);
426 #endif
427 }
429 #ifdef CONFIG_SMP
430 static void
431 check_for_logical_procs (void)
432 {
433 pal_logical_to_physical_t info;
434 s64 status;
436 status = ia64_pal_logical_to_phys(0, &info);
437 if (status == -1) {
438 printk(KERN_INFO "No logical to physical processor mapping "
439 "available\n");
440 return;
441 }
442 if (status) {
443 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
444 status);
445 return;
446 }
447 /*
448 * Total number of siblings that BSP has. Though not all of them
449 * may have booted successfully. The correct number of siblings
450 * booted is in info.overview_num_log.
451 */
452 smp_num_siblings = info.overview_tpc;
453 smp_num_cpucores = info.overview_cpp;
454 }
455 #endif
457 void __init
458 #ifdef XEN
459 early_setup_arch (char **cmdline_p)
460 #else
461 setup_arch (char **cmdline_p)
462 #endif
463 {
464 unw_init();
466 #ifndef XEN
467 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
468 #endif
470 *cmdline_p = __va(ia64_boot_param->command_line);
471 #ifndef XEN
472 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
473 #else
474 early_cmdline_parse(cmdline_p);
475 cmdline_parse(*cmdline_p);
476 #endif
478 efi_init();
479 io_port_init();
481 #ifdef CONFIG_IA64_GENERIC
482 {
483 const char *mvec_name = strstr (*cmdline_p, "machvec=");
484 char str[64];
486 if (mvec_name) {
487 const char *end;
488 size_t len;
490 mvec_name += 8;
491 end = strchr (mvec_name, ' ');
492 if (end)
493 len = end - mvec_name;
494 else
495 len = strlen (mvec_name);
496 len = min(len, sizeof (str) - 1);
497 strlcpy (str, mvec_name, len);
498 mvec_name = str;
499 } else
500 mvec_name = acpi_get_sysname();
501 machvec_init(mvec_name);
502 }
503 #endif
505 if (early_console_setup(*cmdline_p) == 0)
506 mark_bsp_online();
508 #ifdef XEN
509 }
511 void __init
512 late_setup_arch (char **cmdline_p)
513 {
514 #endif
515 #ifdef CONFIG_ACPI_BOOT
516 /* Initialize the ACPI boot-time table parser */
517 acpi_table_init();
518 # ifdef CONFIG_ACPI_NUMA
519 acpi_numa_init();
520 # endif
521 #else
522 # ifdef CONFIG_SMP
523 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
524 # endif
525 #endif /* CONFIG_APCI_BOOT */
527 #ifndef XEN
528 find_memory();
529 #endif
531 /* process SAL system table: */
532 ia64_sal_init(efi.sal_systab);
534 #ifdef CONFIG_SMP
535 #ifdef XEN
536 init_smp_config ();
537 #endif
539 cpu_physical_id(0) = hard_smp_processor_id();
541 cpu_set(0, cpu_sibling_map[0]);
542 cpu_set(0, cpu_core_map[0]);
544 check_for_logical_procs();
545 if (smp_num_cpucores > 1)
546 printk(KERN_INFO
547 "cpu package is Multi-Core capable: number of cores=%d\n",
548 smp_num_cpucores);
549 if (smp_num_siblings > 1)
550 printk(KERN_INFO
551 "cpu package is Multi-Threading capable: number of siblings=%d\n",
552 smp_num_siblings);
553 #endif
555 #ifdef XEN
556 identify_vmx_feature();
557 #endif
559 cpu_init(); /* initialize the bootstrap CPU */
561 #ifdef CONFIG_ACPI_BOOT
562 acpi_boot_init();
563 #endif
565 #ifdef CONFIG_VT
566 if (!conswitchp) {
567 # if defined(CONFIG_DUMMY_CONSOLE)
568 conswitchp = &dummy_con;
569 # endif
570 # if defined(CONFIG_VGA_CONSOLE)
571 /*
572 * Non-legacy systems may route legacy VGA MMIO range to system
573 * memory. vga_con probes the MMIO hole, so memory looks like
574 * a VGA device to it. The EFI memory map can tell us if it's
575 * memory so we can avoid this problem.
576 */
577 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
578 conswitchp = &vga_con;
579 # endif
580 }
581 #endif
583 /* enable IA-64 Machine Check Abort Handling unless disabled */
584 if (!strstr(saved_command_line, "nomca"))
585 ia64_mca_init();
587 platform_setup(cmdline_p);
588 paging_init();
589 }
591 #ifndef XEN
592 /*
593 * Display cpu info for all cpu's.
594 */
595 static int
596 show_cpuinfo (struct seq_file *m, void *v)
597 {
598 #ifdef CONFIG_SMP
599 # define lpj c->loops_per_jiffy
600 # define cpunum c->cpu
601 #else
602 # define lpj loops_per_jiffy
603 # define cpunum 0
604 #endif
605 static struct {
606 unsigned long mask;
607 const char *feature_name;
608 } feature_bits[] = {
609 { 1UL << 0, "branchlong" },
610 { 1UL << 1, "spontaneous deferral"},
611 { 1UL << 2, "16-byte atomic ops" }
612 };
613 char family[32], features[128], *cp, sep;
614 struct cpuinfo_ia64 *c = v;
615 unsigned long mask;
616 int i;
618 mask = c->features;
620 switch (c->family) {
621 case 0x07: memcpy(family, "Itanium", 8); break;
622 case 0x1f: memcpy(family, "Itanium 2", 10); break;
623 default: snprintf(family, sizeof(family), "%u", c->family); break;
624 }
626 /* build the feature string: */
627 memcpy(features, " standard", 10);
628 cp = features;
629 sep = 0;
630 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
631 if (mask & feature_bits[i].mask) {
632 if (sep)
633 *cp++ = sep;
634 sep = ',';
635 *cp++ = ' ';
636 strlcpy(cp, feature_bits[i].feature_name, sizeof(features));
637 cp += strlen(feature_bits[i].feature_name);
638 mask &= ~feature_bits[i].mask;
639 }
640 }
641 if (mask) {
642 /* print unknown features as a hex value: */
643 if (sep)
644 *cp++ = sep;
645 snprintf(cp, sizeof(features) - (cp - features), " 0x%lx", mask);
646 }
648 seq_printf(m,
649 "processor : %d\n"
650 "vendor : %s\n"
651 "arch : IA-64\n"
652 "family : %s\n"
653 "model : %u\n"
654 "revision : %u\n"
655 "archrev : %u\n"
656 "features :%s\n" /* don't change this---it _is_ right! */
657 "cpu number : %lu\n"
658 "cpu regs : %u\n"
659 "cpu MHz : %lu.%06lu\n"
660 "itc MHz : %lu.%06lu\n"
661 "BogoMIPS : %lu.%02lu\n",
662 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
663 features, c->ppn, c->number,
664 c->proc_freq / 1000000, c->proc_freq % 1000000,
665 c->itc_freq / 1000000, c->itc_freq % 1000000,
666 lpj*HZ/500000, (lpj*HZ/5000) % 100);
667 #ifdef CONFIG_SMP
668 seq_printf(m, "siblings : %u\n", c->num_log);
669 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
670 seq_printf(m,
671 "physical id: %u\n"
672 "core id : %u\n"
673 "thread id : %u\n",
674 c->socket_id, c->core_id, c->thread_id);
675 #endif
676 seq_printf(m,"\n");
678 return 0;
679 }
681 static void *
682 c_start (struct seq_file *m, loff_t *pos)
683 {
684 #ifdef CONFIG_SMP
685 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
686 ++*pos;
687 #endif
688 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
689 }
691 static void *
692 c_next (struct seq_file *m, void *v, loff_t *pos)
693 {
694 ++*pos;
695 return c_start(m, pos);
696 }
698 static void
699 c_stop (struct seq_file *m, void *v)
700 {
701 }
703 struct seq_operations cpuinfo_op = {
704 .start = c_start,
705 .next = c_next,
706 .stop = c_stop,
707 .show = show_cpuinfo
708 };
709 #endif /* XEN */
711 void
712 identify_cpu (struct cpuinfo_ia64 *c)
713 {
714 union {
715 unsigned long bits[5];
716 struct {
717 /* id 0 & 1: */
718 char vendor[16];
720 /* id 2 */
721 u64 ppn; /* processor serial number */
723 /* id 3: */
724 unsigned number : 8;
725 unsigned revision : 8;
726 unsigned model : 8;
727 unsigned family : 8;
728 unsigned archrev : 8;
729 unsigned reserved : 24;
731 /* id 4: */
732 u64 features;
733 } field;
734 } cpuid;
735 pal_vm_info_1_u_t vm1;
736 pal_vm_info_2_u_t vm2;
737 pal_status_t status;
738 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
739 int i;
741 for (i = 0; i < 5; ++i)
742 cpuid.bits[i] = ia64_get_cpuid(i);
744 memcpy(c->vendor, cpuid.field.vendor, 16);
745 #ifdef CONFIG_SMP
746 c->cpu = smp_processor_id();
748 /* below default values will be overwritten by identify_siblings()
749 * for Multi-Threading/Multi-Core capable cpu's
750 */
751 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
752 c->socket_id = -1;
754 identify_siblings(c);
755 #endif
756 c->ppn = cpuid.field.ppn;
757 c->number = cpuid.field.number;
758 c->revision = cpuid.field.revision;
759 c->model = cpuid.field.model;
760 c->family = cpuid.field.family;
761 c->archrev = cpuid.field.archrev;
762 c->features = cpuid.field.features;
764 status = ia64_pal_vm_summary(&vm1, &vm2);
765 if (status == PAL_STATUS_SUCCESS) {
766 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
767 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
768 }
769 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
770 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
772 #ifdef XEN
773 /* If vmx feature is on, do necessary initialization for vmx */
774 if (vmx_enabled)
775 vmx_init_env();
776 #endif
777 }
779 void
780 setup_per_cpu_areas (void)
781 {
782 /* start_kernel() requires this... */
783 }
785 /*
786 * Calculate the max. cache line size.
787 *
788 * In addition, the minimum of the i-cache stride sizes is calculated for
789 * "flush_icache_range()".
790 */
791 static void
792 get_max_cacheline_size (void)
793 {
794 unsigned long line_size, max = 1;
795 u64 l, levels, unique_caches;
796 pal_cache_config_info_t cci;
797 s64 status;
799 status = ia64_pal_cache_summary(&levels, &unique_caches);
800 if (status != 0) {
801 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
802 __FUNCTION__, status);
803 max = SMP_CACHE_BYTES;
804 /* Safest setup for "flush_icache_range()" */
805 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
806 #ifdef XEN
807 ia64_d_cache_stride_shift = D_CACHE_STRIDE_SHIFT;
808 #endif
809 goto out;
810 }
812 for (l = 0; l < levels; ++l) {
813 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
814 &cci);
815 if (status != 0) {
816 printk(KERN_ERR
817 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
818 __FUNCTION__, l, status);
819 max = SMP_CACHE_BYTES;
820 /* The safest setup for "flush_icache_range()" */
821 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
822 cci.pcci_unified = 1;
823 }
824 #ifdef XEN
825 if (cci.pcci_stride < ia64_d_cache_stride_shift)
826 ia64_d_cache_stride_shift = cci.pcci_stride;
827 #endif
828 line_size = 1 << cci.pcci_line_size;
829 if (line_size > max)
830 max = line_size;
831 if (!cci.pcci_unified) {
832 status = ia64_pal_cache_config_info(l,
833 /* cache_type (instruction)= */ 1,
834 &cci);
835 if (status != 0) {
836 printk(KERN_ERR
837 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
838 __FUNCTION__, l, status);
839 /* The safest setup for "flush_icache_range()" */
840 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
841 }
842 }
843 if (cci.pcci_stride < ia64_i_cache_stride_shift)
844 ia64_i_cache_stride_shift = cci.pcci_stride;
845 }
846 out:
847 if (max > ia64_max_cacheline_size)
848 ia64_max_cacheline_size = max;
849 #ifdef XEN
850 if (ia64_d_cache_stride_shift > ia64_i_cache_stride_shift)
851 ia64_d_cache_stride_shift = ia64_i_cache_stride_shift;
852 #endif
854 }
856 /*
857 * cpu_init() initializes state that is per-CPU. This function acts
858 * as a 'CPU state barrier', nothing should get across.
859 */
860 void
861 cpu_init (void)
862 {
863 extern void __devinit ia64_mmu_init (void *);
864 unsigned long num_phys_stacked;
865 #ifndef XEN
866 pal_vm_info_2_u_t vmi;
867 unsigned int max_ctx;
868 #endif
869 struct cpuinfo_ia64 *cpu_info;
870 void *cpu_data;
872 cpu_data = per_cpu_init();
874 #ifdef XEN
875 printk("cpu_init: current=%p\n", current);
876 #endif
878 /*
879 * We set ar.k3 so that assembly code in MCA handler can compute
880 * physical addresses of per cpu variables with a simple:
881 * phys = ar.k3 + &per_cpu_var
882 */
883 ia64_set_kr(IA64_KR_PER_CPU_DATA,
884 ia64_tpa(cpu_data) - (long) __per_cpu_start);
886 get_max_cacheline_size();
888 /*
889 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
890 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
891 * depends on the data returned by identify_cpu(). We break the dependency by
892 * accessing cpu_data() through the canonical per-CPU address.
893 */
894 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
895 identify_cpu(cpu_info);
897 #ifdef CONFIG_MCKINLEY
898 {
899 # define FEATURE_SET 16
900 struct ia64_pal_retval iprv;
902 if (cpu_info->family == 0x1f) {
903 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
904 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
905 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
906 (iprv.v1 | 0x80), FEATURE_SET, 0);
907 }
908 }
909 #endif
911 /* Clear the stack memory reserved for pt_regs: */
912 memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
914 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
916 /*
917 * Initialize the page-table base register to a global
918 * directory with all zeroes. This ensure that we can handle
919 * TLB-misses to user address-space even before we created the
920 * first user address-space. This may happen, e.g., due to
921 * aggressive use of lfetch.fault.
922 */
923 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
925 /*
926 * Initialize default control register to defer speculative faults except
927 * for those arising from TLB misses, which are not deferred. The
928 * kernel MUST NOT depend on a particular setting of these bits (in other words,
929 * the kernel must have recovery code for all speculative accesses). Turn on
930 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
931 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
932 * be fine).
933 */
934 #ifdef XEN
935 ia64_setreg(_IA64_REG_CR_DCR, IA64_DEFAULT_DCR_BITS);
936 #else
937 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
938 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
939 #endif
940 #ifndef XEN
941 atomic_inc(&init_mm.mm_count);
942 current->active_mm = &init_mm;
943 #endif
944 #ifndef XEN
945 if (current->mm)
946 BUG();
947 #endif
950 #ifdef XEN
951 ia64_fph_enable();
952 __ia64_init_fpu();
953 #endif
955 ia64_mmu_init(ia64_imva(cpu_data));
956 ia64_mca_cpu_init(ia64_imva(cpu_data));
958 #ifdef CONFIG_IA32_SUPPORT
959 ia32_cpu_init();
960 #endif
962 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
963 ia64_set_itc(0);
965 /* disable all local interrupt sources: */
966 ia64_set_itv(1 << 16);
967 ia64_set_lrr0(1 << 16);
968 ia64_set_lrr1(1 << 16);
969 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
970 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
972 /* clear TPR & XTP to enable all interrupt classes: */
973 ia64_setreg(_IA64_REG_CR_TPR, 0);
974 #ifdef CONFIG_SMP
975 normal_xtp();
976 #endif
978 #ifndef XEN
979 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
980 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
981 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
982 else {
983 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
984 max_ctx = (1U << 15) - 1; /* use architected minimum */
985 }
986 while (max_ctx < ia64_ctx.max_ctx) {
987 unsigned int old = ia64_ctx.max_ctx;
988 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
989 break;
990 }
991 #endif
993 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
994 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
995 "stacked regs\n");
996 num_phys_stacked = 96;
997 }
998 /* size of physical stacked register partition plus 8 bytes: */
999 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
1000 platform_cpu_init();
1001 #ifndef XEN
1002 pm_idle = default_idle;
1003 #endif
1005 #ifdef XEN
1006 /* surrender usage of kernel registers to domain, use percpu area instead */
1007 __get_cpu_var(cpu_kr)._kr[IA64_KR_IO_BASE] = ia64_get_kr(IA64_KR_IO_BASE);
1008 __get_cpu_var(cpu_kr)._kr[IA64_KR_PER_CPU_DATA] = ia64_get_kr(IA64_KR_PER_CPU_DATA);
1009 __get_cpu_var(cpu_kr)._kr[IA64_KR_CURRENT_STACK] = ia64_get_kr(IA64_KR_CURRENT_STACK);
1010 __get_cpu_var(cpu_kr)._kr[IA64_KR_FPU_OWNER] = ia64_get_kr(IA64_KR_FPU_OWNER);
1011 __get_cpu_var(cpu_kr)._kr[IA64_KR_CURRENT] = ia64_get_kr(IA64_KR_CURRENT);
1012 __get_cpu_var(cpu_kr)._kr[IA64_KR_PT_BASE] = ia64_get_kr(IA64_KR_PT_BASE);
1013 #endif
1016 #ifndef XEN
1017 void
1018 check_bugs (void)
1020 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
1021 (unsigned long) __end___mckinley_e9_bundles);
1023 #endif