ia64/xen-unstable

view linux-2.6-xen-sparse/arch/xen/i386/kernel/smpboot.c @ 7329:74d56b7ff46c

Merged
author djm@kirby.fc.hp.com
date Tue Oct 11 16:57:44 2005 -0600 (2005-10-11)
parents 4e0c94871be2 f1e8d5f64105
children def91f2dbc89
line source
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 *
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
9 *
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
13 *
14 * This code is released under the GNU General Public License version 2 or
15 * later.
16 *
17 * Fixes
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
28 * from Jose Renau
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/config.h>
38 #include <linux/init.h>
39 #include <linux/kernel.h>
41 #include <linux/mm.h>
42 #include <linux/sched.h>
43 #include <linux/kernel_stat.h>
44 #include <linux/smp_lock.h>
45 #include <linux/irq.h>
46 #include <linux/bootmem.h>
47 #include <linux/notifier.h>
48 #include <linux/cpu.h>
49 #include <linux/percpu.h>
51 #include <linux/delay.h>
52 #include <linux/mc146818rtc.h>
53 #include <asm/tlbflush.h>
54 #include <asm/desc.h>
55 #include <asm/arch_hooks.h>
57 #include <asm/smp_alt.h>
59 #ifndef CONFIG_X86_IO_APIC
60 #define Dprintk(args...)
61 #endif
62 #include <mach_wakecpu.h>
63 #include <smpboot_hooks.h>
65 #include <asm-xen/evtchn.h>
66 #include <asm-xen/xen-public/vcpu.h>
68 /* Set if we find a B stepping CPU */
69 static int __initdata smp_b_stepping;
71 /* Number of siblings per CPU package */
72 int smp_num_siblings = 1;
73 int phys_proc_id[NR_CPUS]; /* Package ID of each logical CPU */
74 EXPORT_SYMBOL(phys_proc_id);
75 int cpu_core_id[NR_CPUS]; /* Core ID of each logical CPU */
76 EXPORT_SYMBOL(cpu_core_id);
78 /* bitmap of online cpus */
79 cpumask_t cpu_online_map;
81 cpumask_t cpu_callin_map;
82 cpumask_t cpu_callout_map;
83 static cpumask_t smp_commenced_mask;
85 /* Per CPU bogomips and other parameters */
86 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
88 u8 x86_cpu_to_apicid[NR_CPUS] =
89 { [0 ... NR_CPUS-1] = 0xff };
90 EXPORT_SYMBOL(x86_cpu_to_apicid);
92 #if 0
93 /*
94 * Trampoline 80x86 program as an array.
95 */
97 extern unsigned char trampoline_data [];
98 extern unsigned char trampoline_end [];
99 static unsigned char *trampoline_base;
100 static int trampoline_exec;
101 #endif
103 #ifdef CONFIG_HOTPLUG_CPU
104 /* State of each CPU. */
105 DEFINE_PER_CPU(int, cpu_state) = { 0 };
106 #endif
108 static DEFINE_PER_CPU(int, resched_irq);
109 static DEFINE_PER_CPU(int, callfunc_irq);
110 static char resched_name[NR_CPUS][15];
111 static char callfunc_name[NR_CPUS][15];
113 #if 0
114 /*
115 * Currently trivial. Write the real->protected mode
116 * bootstrap into the page concerned. The caller
117 * has made sure it's suitably aligned.
118 */
120 static unsigned long __init setup_trampoline(void)
121 {
122 memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
123 return virt_to_phys(trampoline_base);
124 }
125 #endif
127 static void map_cpu_to_logical_apicid(void);
129 /*
130 * We are called very early to get the low memory for the
131 * SMP bootup trampoline page.
132 */
133 void __init smp_alloc_memory(void)
134 {
135 #if 0
136 trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
137 /*
138 * Has to be in very low memory so we can execute
139 * real-mode AP code.
140 */
141 if (__pa(trampoline_base) >= 0x9F000)
142 BUG();
143 /*
144 * Make the SMP trampoline executable:
145 */
146 trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1);
147 #endif
148 }
150 /*
151 * The bootstrap kernel entry code has set these up. Save them for
152 * a given CPU
153 */
155 static void __init smp_store_cpu_info(int id)
156 {
157 struct cpuinfo_x86 *c = cpu_data + id;
159 *c = boot_cpu_data;
160 if (id!=0)
161 identify_cpu(c);
162 /*
163 * Mask B, Pentium, but not Pentium MMX
164 */
165 if (c->x86_vendor == X86_VENDOR_INTEL &&
166 c->x86 == 5 &&
167 c->x86_mask >= 1 && c->x86_mask <= 4 &&
168 c->x86_model <= 3)
169 /*
170 * Remember we have B step Pentia with bugs
171 */
172 smp_b_stepping = 1;
174 /*
175 * Certain Athlons might work (for various values of 'work') in SMP
176 * but they are not certified as MP capable.
177 */
178 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
180 /* Athlon 660/661 is valid. */
181 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
182 goto valid_k7;
184 /* Duron 670 is valid */
185 if ((c->x86_model==7) && (c->x86_mask==0))
186 goto valid_k7;
188 /*
189 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
190 * It's worth noting that the A5 stepping (662) of some Athlon XP's
191 * have the MP bit set.
192 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
193 */
194 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
195 ((c->x86_model==7) && (c->x86_mask>=1)) ||
196 (c->x86_model> 7))
197 if (cpu_has_mp)
198 goto valid_k7;
200 /* If we get here, it's not a certified SMP capable AMD system. */
201 tainted |= TAINT_UNSAFE_SMP;
202 }
204 valid_k7:
205 ;
206 }
208 #if 0
209 /*
210 * TSC synchronization.
211 *
212 * We first check whether all CPUs have their TSC's synchronized,
213 * then we print a warning if not, and always resync.
214 */
216 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
217 static atomic_t tsc_count_start = ATOMIC_INIT(0);
218 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
219 static unsigned long long tsc_values[NR_CPUS];
221 #define NR_LOOPS 5
223 static void __init synchronize_tsc_bp (void)
224 {
225 int i;
226 unsigned long long t0;
227 unsigned long long sum, avg;
228 long long delta;
229 unsigned long one_usec;
230 int buggy = 0;
232 printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus());
234 /* convert from kcyc/sec to cyc/usec */
235 one_usec = cpu_khz / 1000;
237 atomic_set(&tsc_start_flag, 1);
238 wmb();
240 /*
241 * We loop a few times to get a primed instruction cache,
242 * then the last pass is more or less synchronized and
243 * the BP and APs set their cycle counters to zero all at
244 * once. This reduces the chance of having random offsets
245 * between the processors, and guarantees that the maximum
246 * delay between the cycle counters is never bigger than
247 * the latency of information-passing (cachelines) between
248 * two CPUs.
249 */
250 for (i = 0; i < NR_LOOPS; i++) {
251 /*
252 * all APs synchronize but they loop on '== num_cpus'
253 */
254 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1)
255 mb();
256 atomic_set(&tsc_count_stop, 0);
257 wmb();
258 /*
259 * this lets the APs save their current TSC:
260 */
261 atomic_inc(&tsc_count_start);
263 rdtscll(tsc_values[smp_processor_id()]);
264 /*
265 * We clear the TSC in the last loop:
266 */
267 if (i == NR_LOOPS-1)
268 write_tsc(0, 0);
270 /*
271 * Wait for all APs to leave the synchronization point:
272 */
273 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1)
274 mb();
275 atomic_set(&tsc_count_start, 0);
276 wmb();
277 atomic_inc(&tsc_count_stop);
278 }
280 sum = 0;
281 for (i = 0; i < NR_CPUS; i++) {
282 if (cpu_isset(i, cpu_callout_map)) {
283 t0 = tsc_values[i];
284 sum += t0;
285 }
286 }
287 avg = sum;
288 do_div(avg, num_booting_cpus());
290 sum = 0;
291 for (i = 0; i < NR_CPUS; i++) {
292 if (!cpu_isset(i, cpu_callout_map))
293 continue;
294 delta = tsc_values[i] - avg;
295 if (delta < 0)
296 delta = -delta;
297 /*
298 * We report bigger than 2 microseconds clock differences.
299 */
300 if (delta > 2*one_usec) {
301 long realdelta;
302 if (!buggy) {
303 buggy = 1;
304 printk("\n");
305 }
306 realdelta = delta;
307 do_div(realdelta, one_usec);
308 if (tsc_values[i] < avg)
309 realdelta = -realdelta;
311 printk(KERN_INFO "CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta);
312 }
314 sum += delta;
315 }
316 if (!buggy)
317 printk("passed.\n");
318 }
320 static void __init synchronize_tsc_ap (void)
321 {
322 int i;
324 /*
325 * Not every cpu is online at the time
326 * this gets called, so we first wait for the BP to
327 * finish SMP initialization:
328 */
329 while (!atomic_read(&tsc_start_flag)) mb();
331 for (i = 0; i < NR_LOOPS; i++) {
332 atomic_inc(&tsc_count_start);
333 while (atomic_read(&tsc_count_start) != num_booting_cpus())
334 mb();
336 rdtscll(tsc_values[smp_processor_id()]);
337 if (i == NR_LOOPS-1)
338 write_tsc(0, 0);
340 atomic_inc(&tsc_count_stop);
341 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
342 }
343 }
344 #undef NR_LOOPS
345 #endif
347 extern void calibrate_delay(void);
349 static atomic_t init_deasserted;
351 static void __init smp_callin(void)
352 {
353 int cpuid, phys_id;
354 unsigned long timeout;
356 #if 0
357 /*
358 * If waken up by an INIT in an 82489DX configuration
359 * we may get here before an INIT-deassert IPI reaches
360 * our local APIC. We have to wait for the IPI or we'll
361 * lock up on an APIC access.
362 */
363 wait_for_init_deassert(&init_deasserted);
364 #endif
366 /*
367 * (This works even if the APIC is not enabled.)
368 */
369 phys_id = smp_processor_id();
370 cpuid = smp_processor_id();
371 if (cpu_isset(cpuid, cpu_callin_map)) {
372 printk("huh, phys CPU#%d, CPU#%d already present??\n",
373 phys_id, cpuid);
374 BUG();
375 }
376 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
378 /*
379 * STARTUP IPIs are fragile beasts as they might sometimes
380 * trigger some glue motherboard logic. Complete APIC bus
381 * silence for 1 second, this overestimates the time the
382 * boot CPU is spending to send the up to 2 STARTUP IPIs
383 * by a factor of two. This should be enough.
384 */
386 /*
387 * Waiting 2s total for startup (udelay is not yet working)
388 */
389 timeout = jiffies + 2*HZ;
390 while (time_before(jiffies, timeout)) {
391 /*
392 * Has the boot CPU finished it's STARTUP sequence?
393 */
394 if (cpu_isset(cpuid, cpu_callout_map))
395 break;
396 rep_nop();
397 }
399 if (!time_before(jiffies, timeout)) {
400 printk("BUG: CPU%d started up but did not get a callout!\n",
401 cpuid);
402 BUG();
403 }
405 #if 0
406 /*
407 * the boot CPU has finished the init stage and is spinning
408 * on callin_map until we finish. We are free to set up this
409 * CPU, first the APIC. (this is probably redundant on most
410 * boards)
411 */
413 Dprintk("CALLIN, before setup_local_APIC().\n");
414 smp_callin_clear_local_apic();
415 setup_local_APIC();
416 #endif
417 map_cpu_to_logical_apicid();
419 /*
420 * Get our bogomips.
421 */
422 calibrate_delay();
423 Dprintk("Stack at about %p\n",&cpuid);
425 /*
426 * Save our processor parameters
427 */
428 smp_store_cpu_info(cpuid);
430 #if 0
431 disable_APIC_timer();
432 #endif
434 /*
435 * Allow the master to continue.
436 */
437 cpu_set(cpuid, cpu_callin_map);
439 #if 0
440 /*
441 * Synchronize the TSC with the BP
442 */
443 if (cpu_has_tsc && cpu_khz)
444 synchronize_tsc_ap();
445 #endif
446 }
448 static int cpucount;
450 extern void local_setup_timer(void);
452 /*
453 * Activate a secondary processor.
454 */
455 static void __init start_secondary(void *unused)
456 {
457 /*
458 * Dont put anything before smp_callin(), SMP
459 * booting is too fragile that we want to limit the
460 * things done here to the most necessary things.
461 */
462 cpu_init();
463 smp_callin();
464 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
465 rep_nop();
466 local_setup_timer();
467 smp_intr_init();
468 local_irq_enable();
469 /*
470 * low-memory mappings have been cleared, flush them from
471 * the local TLBs too.
472 */
473 local_flush_tlb();
474 cpu_set(smp_processor_id(), cpu_online_map);
476 /* We can take interrupts now: we're officially "up". */
477 local_irq_enable();
479 wmb();
480 cpu_idle();
481 }
483 /*
484 * Everything has been set up for the secondary
485 * CPUs - they just need to reload everything
486 * from the task structure
487 * This function must not return.
488 */
489 void __init initialize_secondary(void)
490 {
491 /*
492 * We don't actually need to load the full TSS,
493 * basically just the stack pointer and the eip.
494 */
496 asm volatile(
497 "movl %0,%%esp\n\t"
498 "jmp *%1"
499 :
500 :"r" (current->thread.esp),"r" (current->thread.eip));
501 }
503 extern struct {
504 void * esp;
505 unsigned short ss;
506 } stack_start;
508 #ifdef CONFIG_NUMA
510 /* which logical CPUs are on which nodes */
511 cpumask_t node_2_cpu_mask[MAX_NUMNODES] =
512 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
513 /* which node each logical CPU is on */
514 int cpu_2_node[NR_CPUS] = { [0 ... NR_CPUS-1] = 0 };
515 EXPORT_SYMBOL(cpu_2_node);
517 /* set up a mapping between cpu and node. */
518 static inline void map_cpu_to_node(int cpu, int node)
519 {
520 printk("Mapping cpu %d to node %d\n", cpu, node);
521 cpu_set(cpu, node_2_cpu_mask[node]);
522 cpu_2_node[cpu] = node;
523 }
525 /* undo a mapping between cpu and node. */
526 static inline void unmap_cpu_to_node(int cpu)
527 {
528 int node;
530 printk("Unmapping cpu %d from all nodes\n", cpu);
531 for (node = 0; node < MAX_NUMNODES; node ++)
532 cpu_clear(cpu, node_2_cpu_mask[node]);
533 cpu_2_node[cpu] = 0;
534 }
535 #else /* !CONFIG_NUMA */
537 #define map_cpu_to_node(cpu, node) ({})
538 #define unmap_cpu_to_node(cpu) ({})
540 #endif /* CONFIG_NUMA */
542 u8 cpu_2_logical_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
544 static void map_cpu_to_logical_apicid(void)
545 {
546 int cpu = smp_processor_id();
547 int apicid = smp_processor_id();
549 cpu_2_logical_apicid[cpu] = apicid;
550 map_cpu_to_node(cpu, apicid_to_node(apicid));
551 }
553 static void unmap_cpu_to_logical_apicid(int cpu)
554 {
555 cpu_2_logical_apicid[cpu] = BAD_APICID;
556 unmap_cpu_to_node(cpu);
557 }
559 #if APIC_DEBUG
560 static inline void __inquire_remote_apic(int apicid)
561 {
562 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
563 char *names[] = { "ID", "VERSION", "SPIV" };
564 int timeout, status;
566 printk("Inquiring remote APIC #%d...\n", apicid);
568 for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
569 printk("... APIC #%d %s: ", apicid, names[i]);
571 /*
572 * Wait for idle.
573 */
574 apic_wait_icr_idle();
576 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
577 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
579 timeout = 0;
580 do {
581 udelay(100);
582 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
583 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
585 switch (status) {
586 case APIC_ICR_RR_VALID:
587 status = apic_read(APIC_RRR);
588 printk("%08x\n", status);
589 break;
590 default:
591 printk("failed\n");
592 }
593 }
594 }
595 #endif
597 #if 0
598 #ifdef WAKE_SECONDARY_VIA_NMI
599 /*
600 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
601 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
602 * won't ... remember to clear down the APIC, etc later.
603 */
604 static int __init
605 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
606 {
607 unsigned long send_status = 0, accept_status = 0;
608 int timeout, maxlvt;
610 /* Target chip */
611 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
613 /* Boot on the stack */
614 /* Kick the second */
615 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
617 Dprintk("Waiting for send to finish...\n");
618 timeout = 0;
619 do {
620 Dprintk("+");
621 udelay(100);
622 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
623 } while (send_status && (timeout++ < 1000));
625 /*
626 * Give the other CPU some time to accept the IPI.
627 */
628 udelay(200);
629 /*
630 * Due to the Pentium erratum 3AP.
631 */
632 maxlvt = get_maxlvt();
633 if (maxlvt > 3) {
634 apic_read_around(APIC_SPIV);
635 apic_write(APIC_ESR, 0);
636 }
637 accept_status = (apic_read(APIC_ESR) & 0xEF);
638 Dprintk("NMI sent.\n");
640 if (send_status)
641 printk("APIC never delivered???\n");
642 if (accept_status)
643 printk("APIC delivery error (%lx).\n", accept_status);
645 return (send_status | accept_status);
646 }
647 #endif /* WAKE_SECONDARY_VIA_NMI */
649 #ifdef WAKE_SECONDARY_VIA_INIT
650 static int __init
651 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
652 {
653 unsigned long send_status = 0, accept_status = 0;
654 int maxlvt, timeout, num_starts, j;
656 /*
657 * Be paranoid about clearing APIC errors.
658 */
659 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
660 apic_read_around(APIC_SPIV);
661 apic_write(APIC_ESR, 0);
662 apic_read(APIC_ESR);
663 }
665 Dprintk("Asserting INIT.\n");
667 /*
668 * Turn INIT on target chip
669 */
670 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
672 /*
673 * Send IPI
674 */
675 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
676 | APIC_DM_INIT);
678 Dprintk("Waiting for send to finish...\n");
679 timeout = 0;
680 do {
681 Dprintk("+");
682 udelay(100);
683 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
684 } while (send_status && (timeout++ < 1000));
686 mdelay(10);
688 Dprintk("Deasserting INIT.\n");
690 /* Target chip */
691 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
693 /* Send IPI */
694 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
696 Dprintk("Waiting for send to finish...\n");
697 timeout = 0;
698 do {
699 Dprintk("+");
700 udelay(100);
701 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
702 } while (send_status && (timeout++ < 1000));
704 atomic_set(&init_deasserted, 1);
706 /*
707 * Should we send STARTUP IPIs ?
708 *
709 * Determine this based on the APIC version.
710 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
711 */
712 if (APIC_INTEGRATED(apic_version[phys_apicid]))
713 num_starts = 2;
714 else
715 num_starts = 0;
717 /*
718 * Run STARTUP IPI loop.
719 */
720 Dprintk("#startup loops: %d.\n", num_starts);
722 maxlvt = get_maxlvt();
724 for (j = 1; j <= num_starts; j++) {
725 Dprintk("Sending STARTUP #%d.\n",j);
726 apic_read_around(APIC_SPIV);
727 apic_write(APIC_ESR, 0);
728 apic_read(APIC_ESR);
729 Dprintk("After apic_write.\n");
731 /*
732 * STARTUP IPI
733 */
735 /* Target chip */
736 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
738 /* Boot on the stack */
739 /* Kick the second */
740 apic_write_around(APIC_ICR, APIC_DM_STARTUP
741 | (start_eip >> 12));
743 /*
744 * Give the other CPU some time to accept the IPI.
745 */
746 udelay(300);
748 Dprintk("Startup point 1.\n");
750 Dprintk("Waiting for send to finish...\n");
751 timeout = 0;
752 do {
753 Dprintk("+");
754 udelay(100);
755 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
756 } while (send_status && (timeout++ < 1000));
758 /*
759 * Give the other CPU some time to accept the IPI.
760 */
761 udelay(200);
762 /*
763 * Due to the Pentium erratum 3AP.
764 */
765 if (maxlvt > 3) {
766 apic_read_around(APIC_SPIV);
767 apic_write(APIC_ESR, 0);
768 }
769 accept_status = (apic_read(APIC_ESR) & 0xEF);
770 if (send_status || accept_status)
771 break;
772 }
773 Dprintk("After Startup.\n");
775 if (send_status)
776 printk("APIC never delivered???\n");
777 if (accept_status)
778 printk("APIC delivery error (%lx).\n", accept_status);
780 return (send_status | accept_status);
781 }
782 #endif /* WAKE_SECONDARY_VIA_INIT */
783 #endif
785 extern cpumask_t cpu_initialized;
787 static int __init do_boot_cpu(int apicid)
788 /*
789 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
790 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
791 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
792 */
793 {
794 struct task_struct *idle;
795 unsigned long boot_error;
796 int timeout, cpu;
797 unsigned long start_eip;
798 #if 0
799 unsigned short nmi_high = 0, nmi_low = 0;
800 #endif
801 vcpu_guest_context_t ctxt;
802 extern void startup_32_smp(void);
803 extern void hypervisor_callback(void);
804 extern void failsafe_callback(void);
805 extern void smp_trap_init(trap_info_t *);
807 cpu = ++cpucount;
808 /*
809 * We can't use kernel_thread since we must avoid to
810 * reschedule the child.
811 */
812 idle = fork_idle(cpu);
813 if (IS_ERR(idle))
814 panic("failed fork for CPU %d", cpu);
815 idle->thread.eip = (unsigned long) start_secondary;
816 /* start_eip had better be page-aligned! */
817 start_eip = (unsigned long)startup_32_smp;
819 /* So we see what's up */
820 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
821 /* Stack for startup_32 can be just as for start_secondary onwards */
822 stack_start.esp = (void *) idle->thread.esp;
824 irq_ctx_init(cpu);
826 /*
827 * This grunge runs the startup process for
828 * the targeted processor.
829 */
831 atomic_set(&init_deasserted, 0);
833 #if 1
834 cpu_gdt_descr[cpu].address = __get_free_page(GFP_KERNEL|__GFP_ZERO);
835 BUG_ON(cpu_gdt_descr[0].size > PAGE_SIZE);
836 cpu_gdt_descr[cpu].size = cpu_gdt_descr[0].size;
837 memcpy((void *)cpu_gdt_descr[cpu].address,
838 (void *)cpu_gdt_descr[0].address, cpu_gdt_descr[0].size);
840 memset(&ctxt, 0, sizeof(ctxt));
842 ctxt.user_regs.ds = __USER_DS;
843 ctxt.user_regs.es = __USER_DS;
844 ctxt.user_regs.fs = 0;
845 ctxt.user_regs.gs = 0;
846 ctxt.user_regs.ss = __KERNEL_DS;
847 ctxt.user_regs.cs = __KERNEL_CS;
848 ctxt.user_regs.eip = start_eip;
849 ctxt.user_regs.esp = idle->thread.esp;
850 #define X86_EFLAGS_IOPL_RING1 0x1000
851 ctxt.user_regs.eflags = X86_EFLAGS_IF | X86_EFLAGS_IOPL_RING1;
853 /* FPU is set up to default initial state. */
854 memset(&ctxt.fpu_ctxt, 0, sizeof(ctxt.fpu_ctxt));
856 smp_trap_init(ctxt.trap_ctxt);
858 /* No LDT. */
859 ctxt.ldt_ents = 0;
861 {
862 unsigned long va;
863 int f;
865 for (va = cpu_gdt_descr[cpu].address, f = 0;
866 va < cpu_gdt_descr[cpu].address + cpu_gdt_descr[cpu].size;
867 va += PAGE_SIZE, f++) {
868 ctxt.gdt_frames[f] = virt_to_mfn(va);
869 make_page_readonly((void *)va);
870 }
871 ctxt.gdt_ents = cpu_gdt_descr[cpu].size / 8;
872 }
874 /* Ring 1 stack is the initial stack. */
875 ctxt.kernel_ss = __KERNEL_DS;
876 ctxt.kernel_sp = idle->thread.esp;
878 /* Callback handlers. */
879 ctxt.event_callback_cs = __KERNEL_CS;
880 ctxt.event_callback_eip = (unsigned long)hypervisor_callback;
881 ctxt.failsafe_callback_cs = __KERNEL_CS;
882 ctxt.failsafe_callback_eip = (unsigned long)failsafe_callback;
884 ctxt.ctrlreg[3] = virt_to_mfn(swapper_pg_dir) << PAGE_SHIFT;
886 boot_error = HYPERVISOR_vcpu_op(VCPUOP_initialise, cpu, &ctxt);
887 if (boot_error)
888 printk("boot error: %ld\n", boot_error);
890 if (!boot_error) {
891 HYPERVISOR_vcpu_op(VCPUOP_up, cpu, NULL);
893 /*
894 * allow APs to start initializing.
895 */
896 Dprintk("Before Callout %d.\n", cpu);
897 cpu_set(cpu, cpu_callout_map);
898 Dprintk("After Callout %d.\n", cpu);
900 /*
901 * Wait 5s total for a response
902 */
903 for (timeout = 0; timeout < 50000; timeout++) {
904 if (cpu_isset(cpu, cpu_callin_map))
905 break; /* It has booted */
906 udelay(100);
907 }
909 if (cpu_isset(cpu, cpu_callin_map)) {
910 /* number CPUs logically, starting from 1 (BSP is 0) */
911 Dprintk("OK.\n");
912 printk("CPU%d: ", cpu);
913 print_cpu_info(&cpu_data[cpu]);
914 Dprintk("CPU has booted.\n");
915 } else {
916 boot_error= 1;
917 }
918 }
919 x86_cpu_to_apicid[cpu] = apicid;
920 if (boot_error) {
921 /* Try to put things back the way they were before ... */
922 unmap_cpu_to_logical_apicid(cpu);
923 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
924 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
925 cpucount--;
926 }
928 #else
929 Dprintk("Setting warm reset code and vector.\n");
931 store_NMI_vector(&nmi_high, &nmi_low);
933 smpboot_setup_warm_reset_vector(start_eip);
935 /*
936 * Starting actual IPI sequence...
937 */
938 boot_error = wakeup_secondary_cpu(apicid, start_eip);
940 if (!boot_error) {
941 /*
942 * allow APs to start initializing.
943 */
944 Dprintk("Before Callout %d.\n", cpu);
945 cpu_set(cpu, cpu_callout_map);
946 Dprintk("After Callout %d.\n", cpu);
948 /*
949 * Wait 5s total for a response
950 */
951 for (timeout = 0; timeout < 50000; timeout++) {
952 if (cpu_isset(cpu, cpu_callin_map))
953 break; /* It has booted */
954 udelay(100);
955 }
957 if (cpu_isset(cpu, cpu_callin_map)) {
958 /* number CPUs logically, starting from 1 (BSP is 0) */
959 Dprintk("OK.\n");
960 printk("CPU%d: ", cpu);
961 print_cpu_info(&cpu_data[cpu]);
962 Dprintk("CPU has booted.\n");
963 } else {
964 boot_error= 1;
965 if (*((volatile unsigned char *)trampoline_base)
966 == 0xA5)
967 /* trampoline started but...? */
968 printk("Stuck ??\n");
969 else
970 /* trampoline code not run */
971 printk("Not responding.\n");
972 inquire_remote_apic(apicid);
973 }
974 }
975 x86_cpu_to_apicid[cpu] = apicid;
976 if (boot_error) {
977 /* Try to put things back the way they were before ... */
978 unmap_cpu_to_logical_apicid(cpu);
979 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
980 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
981 cpucount--;
982 }
984 /* mark "stuck" area as not stuck */
985 *((volatile unsigned long *)trampoline_base) = 0;
986 #endif
988 return boot_error;
989 }
991 static void smp_tune_scheduling (void)
992 {
993 unsigned long cachesize; /* kB */
994 unsigned long bandwidth = 350; /* MB/s */
995 /*
996 * Rough estimation for SMP scheduling, this is the number of
997 * cycles it takes for a fully memory-limited process to flush
998 * the SMP-local cache.
999 *
1000 * (For a P5 this pretty much means we will choose another idle
1001 * CPU almost always at wakeup time (this is due to the small
1002 * L1 cache), on PIIs it's around 50-100 usecs, depending on
1003 * the cache size)
1004 */
1006 if (!cpu_khz) {
1007 /*
1008 * this basically disables processor-affinity
1009 * scheduling on SMP without a TSC.
1010 */
1011 return;
1012 } else {
1013 cachesize = boot_cpu_data.x86_cache_size;
1014 if (cachesize == -1) {
1015 cachesize = 16; /* Pentiums, 2x8kB cache */
1016 bandwidth = 100;
1021 /*
1022 * Cycle through the processors sending APIC IPIs to boot each.
1023 */
1025 #if 0
1026 static int boot_cpu_logical_apicid;
1027 #endif
1028 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1029 void *xquad_portio;
1031 cpumask_t cpu_sibling_map[NR_CPUS] __cacheline_aligned;
1032 cpumask_t cpu_core_map[NR_CPUS] __cacheline_aligned;
1033 EXPORT_SYMBOL(cpu_core_map);
1035 static void __init smp_boot_cpus(unsigned int max_cpus)
1037 int cpu, kicked;
1038 unsigned long bogosum = 0;
1039 #if 0
1040 int apicid, bit;
1041 #endif
1043 /*
1044 * Setup boot CPU information
1045 */
1046 smp_store_cpu_info(0); /* Final full version of the data */
1047 printk("CPU%d: ", 0);
1048 print_cpu_info(&cpu_data[0]);
1050 #if 0
1051 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
1052 boot_cpu_logical_apicid = logical_smp_processor_id();
1053 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
1054 #else
1055 // boot_cpu_physical_apicid = 0;
1056 // boot_cpu_logical_apicid = 0;
1057 x86_cpu_to_apicid[0] = 0;
1058 #endif
1060 current_thread_info()->cpu = 0;
1061 smp_tune_scheduling();
1062 cpus_clear(cpu_sibling_map[0]);
1063 cpu_set(0, cpu_sibling_map[0]);
1065 cpus_clear(cpu_core_map[0]);
1066 cpu_set(0, cpu_core_map[0]);
1068 #ifdef CONFIG_X86_IO_APIC
1069 /*
1070 * If we couldn't find an SMP configuration at boot time,
1071 * get out of here now!
1072 */
1073 if (!smp_found_config && !acpi_lapic) {
1074 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1075 smpboot_clear_io_apic_irqs();
1076 #if 0
1077 phys_cpu_present_map = physid_mask_of_physid(0);
1078 #endif
1079 #ifdef CONFIG_X86_LOCAL_APIC
1080 if (APIC_init_uniprocessor())
1081 printk(KERN_NOTICE "Local APIC not detected."
1082 " Using dummy APIC emulation.\n");
1083 #endif
1084 map_cpu_to_logical_apicid();
1085 cpu_set(0, cpu_sibling_map[0]);
1086 cpu_set(0, cpu_core_map[0]);
1087 return;
1089 #endif
1091 #if 0
1092 /*
1093 * Should not be necessary because the MP table should list the boot
1094 * CPU too, but we do it for the sake of robustness anyway.
1095 * Makes no sense to do this check in clustered apic mode, so skip it
1096 */
1097 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1098 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1099 boot_cpu_physical_apicid);
1100 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1103 /*
1104 * If we couldn't find a local APIC, then get out of here now!
1105 */
1106 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
1107 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1108 boot_cpu_physical_apicid);
1109 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1110 smpboot_clear_io_apic_irqs();
1111 phys_cpu_present_map = physid_mask_of_physid(0);
1112 cpu_set(0, cpu_sibling_map[0]);
1113 cpu_set(0, cpu_core_map[0]);
1114 cpu_set(0, cpu_sibling_map[0]);
1115 cpu_set(0, cpu_core_map[0]);
1116 return;
1119 verify_local_APIC();
1120 #endif
1122 /*
1123 * If SMP should be disabled, then really disable it!
1124 */
1125 if (!max_cpus) {
1126 HYPERVISOR_shared_info->n_vcpu = 1;
1127 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1128 smpboot_clear_io_apic_irqs();
1129 #if 0
1130 phys_cpu_present_map = physid_mask_of_physid(0);
1131 #endif
1132 return;
1135 smp_intr_init();
1137 #if 0
1138 connect_bsp_APIC();
1139 setup_local_APIC();
1140 #endif
1141 map_cpu_to_logical_apicid();
1142 #if 0
1145 setup_portio_remap();
1147 /*
1148 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1150 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1151 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1152 * clustered apic ID.
1153 */
1154 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1155 #endif
1156 Dprintk("CPU present map: %lx\n",
1157 (1UL << HYPERVISOR_shared_info->n_vcpu) - 1);
1159 kicked = 1;
1160 for (cpu = 1; kicked < NR_CPUS &&
1161 cpu < HYPERVISOR_shared_info->n_vcpu; cpu++) {
1162 if (max_cpus <= cpucount+1)
1163 continue;
1165 #ifdef CONFIG_SMP_ALTERNATIVES
1166 if (kicked == 1)
1167 prepare_for_smp();
1168 #endif
1169 if (do_boot_cpu(cpu))
1170 printk("CPU #%d not responding - cannot use it.\n",
1171 cpu);
1172 else
1173 ++kicked;
1176 #if 0
1177 /*
1178 * Cleanup possible dangling ends...
1179 */
1180 smpboot_restore_warm_reset_vector();
1181 #endif
1183 /*
1184 * Allow the user to impress friends.
1185 */
1186 Dprintk("Before bogomips.\n");
1187 for (cpu = 0; cpu < NR_CPUS; cpu++)
1188 if (cpu_isset(cpu, cpu_callout_map))
1189 bogosum += cpu_data[cpu].loops_per_jiffy;
1190 printk(KERN_INFO
1191 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1192 cpucount+1,
1193 bogosum/(500000/HZ),
1194 (bogosum/(5000/HZ))%100);
1196 Dprintk("Before bogocount - setting activated=1.\n");
1198 if (smp_b_stepping)
1199 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1201 /*
1202 * Don't taint if we are running SMP kernel on a single non-MP
1203 * approved Athlon
1204 */
1205 if (tainted & TAINT_UNSAFE_SMP) {
1206 if (cpucount)
1207 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1208 else
1209 tainted &= ~TAINT_UNSAFE_SMP;
1212 Dprintk("Boot done.\n");
1214 /*
1215 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1216 * efficiently.
1217 */
1218 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1219 cpus_clear(cpu_sibling_map[cpu]);
1220 cpus_clear(cpu_core_map[cpu]);
1223 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1224 struct cpuinfo_x86 *c = cpu_data + cpu;
1225 int siblings = 0;
1226 int i;
1227 if (!cpu_isset(cpu, cpu_callout_map))
1228 continue;
1230 if (smp_num_siblings > 1) {
1231 for (i = 0; i < NR_CPUS; i++) {
1232 if (!cpu_isset(i, cpu_callout_map))
1233 continue;
1234 if (cpu_core_id[cpu] == cpu_core_id[i]) {
1235 siblings++;
1236 cpu_set(i, cpu_sibling_map[cpu]);
1239 } else {
1240 siblings++;
1241 cpu_set(cpu, cpu_sibling_map[cpu]);
1244 if (siblings != smp_num_siblings) {
1245 printk(KERN_WARNING "WARNING: %d siblings found for CPU%d, should be %d\n", siblings, cpu, smp_num_siblings);
1246 smp_num_siblings = siblings;
1249 if (c->x86_num_cores > 1) {
1250 for (i = 0; i < NR_CPUS; i++) {
1251 if (!cpu_isset(i, cpu_callout_map))
1252 continue;
1253 if (phys_proc_id[cpu] == phys_proc_id[i]) {
1254 cpu_set(i, cpu_core_map[cpu]);
1257 } else {
1258 cpu_core_map[cpu] = cpu_sibling_map[cpu];
1262 smpboot_setup_io_apic();
1264 #if 0
1265 setup_boot_APIC_clock();
1267 /*
1268 * Synchronize the TSC with the AP
1269 */
1270 if (cpu_has_tsc && cpucount && cpu_khz)
1271 synchronize_tsc_bp();
1272 #endif
1275 /* These are wrappers to interface to the new boot process. Someone
1276 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1277 void __init smp_prepare_cpus(unsigned int max_cpus)
1279 smp_commenced_mask = cpumask_of_cpu(0);
1280 cpu_callin_map = cpumask_of_cpu(0);
1281 mb();
1282 smp_boot_cpus(max_cpus);
1285 void __devinit smp_prepare_boot_cpu(void)
1287 cpu_set(smp_processor_id(), cpu_online_map);
1288 cpu_set(smp_processor_id(), cpu_callout_map);
1291 #ifdef CONFIG_HOTPLUG_CPU
1292 #include <asm-xen/xenbus.h>
1293 /* hotplug down/up funtion pointer and target vcpu */
1294 struct vcpu_hotplug_handler_t {
1295 void (*fn) (int vcpu);
1296 u32 vcpu;
1297 };
1298 static struct vcpu_hotplug_handler_t vcpu_hotplug_handler;
1300 static int vcpu_hotplug_cpu_process(void *unused)
1302 struct vcpu_hotplug_handler_t *handler = &vcpu_hotplug_handler;
1304 if (handler->fn) {
1305 (*(handler->fn)) (handler->vcpu);
1306 handler->fn = NULL;
1308 return 0;
1311 static void __vcpu_hotplug_handler(void *unused)
1313 int err;
1315 err = kernel_thread(vcpu_hotplug_cpu_process,
1316 NULL, CLONE_FS | CLONE_FILES);
1317 if (err < 0)
1318 printk(KERN_ALERT "Error creating hotplug_cpu process!\n");
1321 static void handle_vcpu_hotplug_event(struct xenbus_watch *, const char *);
1322 static struct notifier_block xsn_cpu;
1324 /* xenbus watch struct */
1325 static struct xenbus_watch cpu_watch = {
1326 .node = "cpu",
1327 .callback = handle_vcpu_hotplug_event
1328 };
1330 static int setup_cpu_watcher(struct notifier_block *notifier,
1331 unsigned long event, void *data)
1333 int err;
1335 err = register_xenbus_watch(&cpu_watch);
1336 if (err)
1337 printk("Failed to register watch on /cpu\n");
1339 return NOTIFY_DONE;
1342 static void handle_vcpu_hotplug_event(struct xenbus_watch *watch, const char *node)
1344 static DECLARE_WORK(vcpu_hotplug_work, __vcpu_hotplug_handler, NULL);
1345 struct vcpu_hotplug_handler_t *handler = &vcpu_hotplug_handler;
1346 ssize_t ret;
1347 int err, cpu;
1348 char state[8];
1349 char dir[32];
1350 char *cpustr;
1352 /* get a pointer to start of cpu string */
1353 if ((cpustr = strstr(node, "cpu/")) != NULL) {
1355 /* find which cpu state changed, note vcpu for handler */
1356 sscanf(cpustr, "cpu/%d", &cpu);
1357 handler->vcpu = cpu;
1359 /* calc the dir for xenbus read */
1360 sprintf(dir, "cpu/%d", cpu);
1362 /* make sure watch that was triggered is changes to the correct key */
1363 if ((strcmp(node + strlen(dir), "/availability")) != 0)
1364 return;
1366 /* get the state value */
1367 err = xenbus_scanf(NULL, dir, "availability", "%s", state);
1369 if (err != 1) {
1370 printk(KERN_ERR
1371 "XENBUS: Unable to read cpu state\n");
1372 return;
1375 /* if we detect a state change, take action */
1376 if (strcmp(state, "online") == 0) {
1377 /* offline -> online */
1378 if (!cpu_isset(cpu, cpu_online_map)) {
1379 handler->fn = (void *)&cpu_up;
1380 ret = schedule_work(&vcpu_hotplug_work);
1382 } else if (strcmp(state, "offline") == 0) {
1383 /* online -> offline */
1384 if (cpu_isset(cpu, cpu_online_map)) {
1385 handler->fn = (void *)&cpu_down;
1386 ret = schedule_work(&vcpu_hotplug_work);
1388 } else {
1389 printk(KERN_ERR
1390 "XENBUS: unknown state(%s) on node(%s)\n", state,
1391 node);
1394 return;
1397 static int __init setup_vcpu_hotplug_event(void)
1399 xsn_cpu.notifier_call = setup_cpu_watcher;
1401 register_xenstore_notifier(&xsn_cpu);
1403 return 0;
1406 subsys_initcall(setup_vcpu_hotplug_event);
1408 /* must be called with the cpucontrol mutex held */
1409 static int __devinit cpu_enable(unsigned int cpu)
1411 #ifdef CONFIG_SMP_ALTERNATIVES
1412 if (num_online_cpus() == 1)
1413 prepare_for_smp();
1414 #endif
1416 /* get the target out of its holding state */
1417 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1418 wmb();
1420 /* wait for the processor to ack it. timeout? */
1421 while (!cpu_online(cpu))
1422 cpu_relax();
1424 fixup_irqs(cpu_online_map);
1426 /* counter the disable in fixup_irqs() */
1427 local_irq_enable();
1428 return 0;
1431 int __cpu_disable(void)
1433 cpumask_t map = cpu_online_map;
1434 int cpu = smp_processor_id();
1436 /*
1437 * Perhaps use cpufreq to drop frequency, but that could go
1438 * into generic code.
1440 * We won't take down the boot processor on i386 due to some
1441 * interrupts only being able to be serviced by the BSP.
1442 * Especially so if we're not using an IOAPIC -zwane
1443 */
1444 if (cpu == 0)
1445 return -EBUSY;
1447 cpu_clear(cpu, map);
1448 fixup_irqs(map);
1450 /* It's now safe to remove this processor from the online map */
1451 cpu_clear(cpu, cpu_online_map);
1453 #ifdef CONFIG_SMP_ALTERNATIVES
1454 if (num_online_cpus() == 1)
1455 unprepare_for_smp();
1456 #endif
1458 return 0;
1461 void __cpu_die(unsigned int cpu)
1463 /* We don't do anything here: idle task is faking death itself. */
1464 unsigned int i;
1466 for (i = 0; i < 10; i++) {
1467 /* They ack this in play_dead by setting CPU_DEAD */
1468 if (per_cpu(cpu_state, cpu) == CPU_DEAD)
1469 return;
1470 current->state = TASK_UNINTERRUPTIBLE;
1471 schedule_timeout(HZ/10);
1473 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1476 #else /* ... !CONFIG_HOTPLUG_CPU */
1477 int __cpu_disable(void)
1479 return -ENOSYS;
1482 void __cpu_die(unsigned int cpu)
1484 /* We said "no" in __cpu_disable */
1485 BUG();
1487 #endif /* CONFIG_HOTPLUG_CPU */
1489 int __devinit __cpu_up(unsigned int cpu)
1491 /* In case one didn't come up */
1492 if (!cpu_isset(cpu, cpu_callin_map)) {
1493 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1494 local_irq_enable();
1495 return -EIO;
1498 #ifdef CONFIG_HOTPLUG_CPU
1499 #ifdef CONFIG_XEN
1500 /* Tell hypervisor to bring vcpu up. */
1501 HYPERVISOR_vcpu_op(VCPUOP_up, cpu, NULL);
1502 #endif
1503 /* Already up, and in cpu_quiescent now? */
1504 if (cpu_isset(cpu, smp_commenced_mask)) {
1505 cpu_enable(cpu);
1506 return 0;
1508 #endif
1510 local_irq_enable();
1511 /* Unleash the CPU! */
1512 cpu_set(cpu, smp_commenced_mask);
1513 while (!cpu_isset(cpu, cpu_online_map))
1514 mb();
1515 return 0;
1518 void __init smp_cpus_done(unsigned int max_cpus)
1520 #if 1
1521 #else
1522 #ifdef CONFIG_X86_IO_APIC
1523 setup_ioapic_dest();
1524 #endif
1525 zap_low_mappings();
1526 /*
1527 * Disable executability of the SMP trampoline:
1528 */
1529 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1530 #endif
1533 extern irqreturn_t smp_reschedule_interrupt(int, void *, struct pt_regs *);
1534 extern irqreturn_t smp_call_function_interrupt(int, void *, struct pt_regs *);
1536 void smp_intr_init(void)
1538 int cpu = smp_processor_id();
1540 per_cpu(resched_irq, cpu) =
1541 bind_ipi_to_irq(RESCHEDULE_VECTOR);
1542 sprintf(resched_name[cpu], "resched%d", cpu);
1543 BUG_ON(request_irq(per_cpu(resched_irq, cpu), smp_reschedule_interrupt,
1544 SA_INTERRUPT, resched_name[cpu], NULL));
1546 per_cpu(callfunc_irq, cpu) =
1547 bind_ipi_to_irq(CALL_FUNCTION_VECTOR);
1548 sprintf(callfunc_name[cpu], "callfunc%d", cpu);
1549 BUG_ON(request_irq(per_cpu(callfunc_irq, cpu),
1550 smp_call_function_interrupt,
1551 SA_INTERRUPT, callfunc_name[cpu], NULL));
1554 static void smp_intr_exit(void)
1556 int cpu = smp_processor_id();
1558 free_irq(per_cpu(resched_irq, cpu), NULL);
1559 unbind_ipi_from_irq(RESCHEDULE_VECTOR);
1561 free_irq(per_cpu(callfunc_irq, cpu), NULL);
1562 unbind_ipi_from_irq(CALL_FUNCTION_VECTOR);
1565 extern void local_setup_timer_irq(void);
1566 extern void local_teardown_timer_irq(void);
1568 void smp_suspend(void)
1570 local_teardown_timer_irq();
1571 smp_intr_exit();
1574 void smp_resume(void)
1576 smp_intr_init();
1577 local_setup_timer();
1580 void vcpu_prepare(int vcpu)
1582 extern void hypervisor_callback(void);
1583 extern void failsafe_callback(void);
1584 extern void smp_trap_init(trap_info_t *);
1585 extern void cpu_restore(void);
1586 vcpu_guest_context_t ctxt;
1587 struct task_struct *idle = idle_task(vcpu);
1589 if (vcpu == 0)
1590 return;
1592 memset(&ctxt, 0, sizeof(ctxt));
1594 ctxt.user_regs.ds = __USER_DS;
1595 ctxt.user_regs.es = __USER_DS;
1596 ctxt.user_regs.fs = 0;
1597 ctxt.user_regs.gs = 0;
1598 ctxt.user_regs.ss = __KERNEL_DS;
1599 ctxt.user_regs.cs = __KERNEL_CS;
1600 ctxt.user_regs.eip = (unsigned long)cpu_restore;
1601 ctxt.user_regs.esp = idle->thread.esp;
1602 ctxt.user_regs.eflags = X86_EFLAGS_IF | X86_EFLAGS_IOPL_RING1;
1604 memset(&ctxt.fpu_ctxt, 0, sizeof(ctxt.fpu_ctxt));
1606 smp_trap_init(ctxt.trap_ctxt);
1608 ctxt.ldt_ents = 0;
1610 ctxt.gdt_frames[0] = virt_to_mfn(cpu_gdt_descr[vcpu].address);
1611 ctxt.gdt_ents = cpu_gdt_descr[vcpu].size / 8;
1613 ctxt.kernel_ss = __KERNEL_DS;
1614 ctxt.kernel_sp = idle->thread.esp0;
1616 ctxt.event_callback_cs = __KERNEL_CS;
1617 ctxt.event_callback_eip = (unsigned long)hypervisor_callback;
1618 ctxt.failsafe_callback_cs = __KERNEL_CS;
1619 ctxt.failsafe_callback_eip = (unsigned long)failsafe_callback;
1621 ctxt.ctrlreg[3] = virt_to_mfn(swapper_pg_dir) << PAGE_SHIFT;
1623 (void)HYPERVISOR_vcpu_op(VCPUOP_initialise, vcpu, &ctxt);
1624 (void)HYPERVISOR_vcpu_op(VCPUOP_up, vcpu, NULL);