ia64/xen-unstable

view tools/misc/cpuperf/cpuperf.c @ 6403:6e899a3840b2

Rename libxc => libxenctrl and xc.h => xen/xenctrl.h
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Christian Limpach <Christian.Limpach@cl.cam.ac.uk>
author cl349@firebug.cl.cam.ac.uk
date Wed Aug 24 23:07:29 2005 +0000 (2005-08-24)
parents 47e1cb8a3d38
children a66a41032226 1fc6473ecc01 b2f4823b6ff0
line source
1 /*
2 * User mode program to program performance counters.
3 *
4 * JRB/IAP October 2003.
5 *
6 * $Id: cpuperf.c,v 1.2 2003/10/14 11:00:59 jrb44 Exp $
7 *
8 * $Log: cpuperf.c,v $
9 * Revision 1.2 2003/10/14 11:00:59 jrb44
10 * Added dcefault CPU. Added NONE CCCR.
11 *
12 * Revision 1.1 2003/10/13 16:49:44 jrb44
13 * Initial revision
14 *
15 */
17 #include <sys/types.h>
18 #include <sched.h>
19 #include <error.h>
20 #include <stdio.h>
21 #include <unistd.h>
22 #include <stdlib.h>
23 #include <string.h>
24 #include <errno.h>
26 #include "p4perf.h"
28 static inline void cpus_wrmsr(int cpu_mask,
29 int msr,
30 unsigned int low,
31 unsigned int high )
32 {
33 fprintf(stderr, "No backend to write MSR 0x%x <= 0x%08x%08x on %08x\n",
34 msr, high, low, cpu_mask);
35 }
37 static inline unsigned long long cpus_rdmsr( int cpu_mask, int msr )
38 {
39 fprintf(stderr, "No backend to read MSR 0x%x on %08x\n", msr, cpu_mask);
40 return 0;
41 }
43 #ifdef PERFCNTR
44 #include "cpuperf_perfcntr.h"
45 #define cpus_wrmsr perfcntr_wrmsr
46 #define cpus_rdmsr perfcntr_rdmsr
47 #endif
49 #ifdef XENO
50 #include "cpuperf_xeno.h"
51 #define cpus_wrmsr dom0_wrmsr
52 #define cpus_rdmsr dom0_rdmsr
53 #endif
55 struct macros {
56 char *name;
57 unsigned long msr_addr;
58 int number;
59 };
61 #define NO_CCCR 0xfffffffe
63 struct macros msr[] = {
64 {"BPU_COUNTER0", 0x300, 0},
65 {"BPU_COUNTER1", 0x301, 1},
66 {"BPU_COUNTER2", 0x302, 2},
67 {"BPU_COUNTER3", 0x303, 3},
68 {"MS_COUNTER0", 0x304, 4},
69 {"MS_COUNTER1", 0x305, 5},
70 {"MS_COUNTER2", 0x306, 6},
71 {"MS_COUNTER3", 0x307, 7},
72 {"FLAME_COUNTER0", 0x308, 8},
73 {"FLAME_COUNTER1", 0x309, 9},
74 {"FLAME_COUNTER2", 0x30a, 10},
75 {"FLAME_COUNTER3", 0x30b, 11},
76 {"IQ_COUNTER0", 0x30c, 12},
77 {"IQ_COUNTER1", 0x30d, 13},
78 {"IQ_COUNTER2", 0x30e, 14},
79 {"IQ_COUNTER3", 0x30f, 15},
80 {"IQ_COUNTER4", 0x310, 16},
81 {"IQ_COUNTER5", 0x311, 17},
82 {"BPU_CCCR0", 0x360, 0},
83 {"BPU_CCCR1", 0x361, 1},
84 {"BPU_CCCR2", 0x362, 2},
85 {"BPU_CCCR3", 0x363, 3},
86 {"MS_CCCR0", 0x364, 4},
87 {"MS_CCCR1", 0x365, 5},
88 {"MS_CCCR2", 0x366, 6},
89 {"MS_CCCR3", 0x367, 7},
90 {"FLAME_CCCR0", 0x368, 8},
91 {"FLAME_CCCR1", 0x369, 9},
92 {"FLAME_CCCR2", 0x36a, 10},
93 {"FLAME_CCCR3", 0x36b, 11},
94 {"IQ_CCCR0", 0x36c, 12},
95 {"IQ_CCCR1", 0x36d, 13},
96 {"IQ_CCCR2", 0x36e, 14},
97 {"IQ_CCCR3", 0x36f, 15},
98 {"IQ_CCCR4", 0x370, 16},
99 {"IQ_CCCR5", 0x371, 17},
100 {"BSU_ESCR0", 0x3a0, 7},
101 {"BSU_ESCR1", 0x3a1, 7},
102 {"FSB_ESCR0", 0x3a2, 6},
103 {"FSB_ESCR1", 0x3a3, 6},
104 {"MOB_ESCR0", 0x3aa, 2},
105 {"MOB_ESCR1", 0x3ab, 2},
106 {"PMH_ESCR0", 0x3ac, 4},
107 {"PMH_ESCR1", 0x3ad, 4},
108 {"BPU_ESCR0", 0x3b2, 0},
109 {"BPU_ESCR1", 0x3b3, 0},
110 {"IS_ESCR0", 0x3b4, 1},
111 {"IS_ESCR1", 0x3b5, 1},
112 {"ITLB_ESCR0", 0x3b6, 3},
113 {"ITLB_ESCR1", 0x3b7, 3},
114 {"IX_ESCR0", 0x3c8, 5},
115 {"IX_ESCR1", 0x3c9, 5},
116 {"MS_ESCR0", 0x3c0, 0},
117 {"MS_ESCR1", 0x3c1, 0},
118 {"TBPU_ESCR0", 0x3c2, 2},
119 {"TBPU_ESCR1", 0x3c3, 2},
120 {"TC_ESCR0", 0x3c4, 1},
121 {"TC_ESCR1", 0x3c5, 1},
122 {"FIRM_ESCR0", 0x3a4, 1},
123 {"FIRM_ESCR1", 0x3a5, 1},
124 {"FLAME_ESCR0", 0x3a6, 0},
125 {"FLAME_ESCR1", 0x3a7, 0},
126 {"DAC_ESCR0", 0x3a8, 5},
127 {"DAC_ESCR1", 0x3a9, 5},
128 {"SAAT_ESCR0", 0x3ae, 2},
129 {"SAAT_ESCR1", 0x3af, 2},
130 {"U2L_ESCR0", 0x3b0, 3},
131 {"U2L_ESCR1", 0x3b1, 3},
132 {"CRU_ESCR0", 0x3b8, 4},
133 {"CRU_ESCR1", 0x3b9, 4},
134 {"CRU_ESCR2", 0x3cc, 5},
135 {"CRU_ESCR3", 0x3cd, 5},
136 {"CRU_ESCR4", 0x3e0, 6},
137 {"CRU_ESCR5", 0x3e1, 6},
138 {"IQ_ESCR0", 0x3ba, 0},
139 {"IQ_ESCR1", 0x3bb, 0},
140 {"RAT_ESCR0", 0x3bc, 2},
141 {"RAT_ESCR1", 0x3bd, 2},
142 {"SSU_ESCR0", 0x3be, 3},
143 {"SSU_ESCR1", 0x3bf, 3},
144 {"ALF_ESCR0", 0x3ca, 1},
145 {"ALF_ESCR1", 0x3cb, 1},
146 {"PEBS_ENABLE", 0x3f1, 0},
147 {"PEBS_MATRIX_VERT", 0x3f2, 0},
148 {"NONE", NO_CCCR, 0},
149 {NULL, 0, 0}
150 };
152 struct macros *lookup_macro(char *str)
153 {
154 struct macros *m;
156 m = msr;
157 while (m->name) {
158 if (strcmp(m->name, str) == 0)
159 return m;
160 m++;
161 }
162 return NULL;
163 }
165 int main(int argc, char **argv)
166 {
167 int c, t = 0xc, es = 0, em = 0, tv = 0, te = 0;
168 unsigned int cpu_mask = 1;
169 struct macros *escr = NULL, *cccr = NULL;
170 unsigned long escr_val, cccr_val;
171 int debug = 0;
172 unsigned long pebs = 0, pebs_vert = 0;
173 int pebs_x = 0, pebs_vert_x = 0;
174 int read = 0;
175 int compare = 0;
176 int complement = 0;
177 int edge = 0;
179 #ifdef XENO
180 xen_init();
181 #endif
184 while ((c = getopt(argc, argv, "dc:t:e:m:T:E:C:P:V:rkng")) != -1) {
185 switch((char)c) {
186 case 'P':
187 pebs |= 1 << atoi(optarg);
188 pebs_x = 1;
189 break;
190 case 'V':
191 pebs_vert |= 1 << atoi(optarg);
192 pebs_vert_x = 1;
193 break;
194 case 'd':
195 debug = 1;
196 break;
197 case 'c':
198 {
199 int cpu = atoi(optarg);
200 cpu_mask = (cpu == -1)?(~0):(1<<cpu);
201 }
202 break;
203 case 't': // ESCR thread bits
204 t = atoi(optarg);
205 break;
206 case 'e': // eventsel
207 es = atoi(optarg);
208 break;
209 case 'm': // eventmask
210 em = atoi(optarg);
211 break;
212 case 'T': // tag value
213 tv = atoi(optarg);
214 te = 1;
215 break;
216 case 'E':
217 escr = lookup_macro(optarg);
218 if (!escr) {
219 fprintf(stderr, "Macro '%s' not found.\n", optarg);
220 exit(1);
221 }
222 break;
223 case 'C':
224 cccr = lookup_macro(optarg);
225 if (!cccr) {
226 fprintf(stderr, "Macro '%s' not found.\n", optarg);
227 exit(1);
228 }
229 break;
230 case 'r':
231 read = 1;
232 break;
233 case 'k':
234 compare = 1;
235 break;
236 case 'n':
237 complement = 1;
238 break;
239 case 'g':
240 edge = 1;
241 break;
242 }
243 }
245 if (read) {
246 while((cpu_mask&1)) {
247 int i;
248 for (i=0x300;i<0x312;i++) {
249 printf("%010llu ",cpus_rdmsr( cpu_mask, i ) );
250 }
251 printf("\n");
252 cpu_mask>>=1;
253 }
254 exit(1);
255 }
257 if (!escr) {
258 fprintf(stderr, "Need an ESCR.\n");
259 exit(1);
260 }
261 if (!cccr) {
262 fprintf(stderr, "Need a counter number.\n");
263 exit(1);
264 }
266 escr_val = P4_ESCR_THREADS(t) | P4_ESCR_EVNTSEL(es) |
267 P4_ESCR_EVNTMASK(em) | P4_ESCR_TV(tv) | ((te)?P4_ESCR_TE:0);
268 cccr_val = P4_CCCR_ENABLE | P4_CCCR_ESCR(escr->number) |
269 ((compare)?P4_CCCR_COMPARE:0) |
270 ((complement)?P4_CCCR_COMPLEMENT:0) |
271 ((edge)?P4_CCCR_EDGE:0) |
272 P4_CCCR_ACTIVE_THREAD(3)/*reserved*/;
274 if (debug) {
275 fprintf(stderr, "ESCR 0x%lx <= 0x%08lx\n", escr->msr_addr, escr_val);
276 if (cccr->msr_addr != NO_CCCR)
277 fprintf(stderr, "CCCR 0x%lx <= 0x%08lx (%u)\n",
278 cccr->msr_addr, cccr_val, cccr->number);
279 if (pebs_x)
280 fprintf(stderr, "PEBS 0x%x <= 0x%08lx\n",
281 MSR_P4_PEBS_ENABLE, pebs);
282 if (pebs_vert_x)
283 fprintf(stderr, "PMV 0x%x <= 0x%08lx\n",
284 MSR_P4_PEBS_MATRIX_VERT, pebs_vert);
285 }
287 cpus_wrmsr( cpu_mask, escr->msr_addr, escr_val, 0 );
288 if (cccr->msr_addr != NO_CCCR)
289 cpus_wrmsr( cpu_mask, cccr->msr_addr, cccr_val, 0 );
291 if (pebs_x)
292 cpus_wrmsr( cpu_mask, MSR_P4_PEBS_ENABLE, pebs, 0 );
294 if (pebs_vert_x)
295 cpus_wrmsr( cpu_mask, MSR_P4_PEBS_MATRIX_VERT, pebs_vert, 0 );
297 return 0;
298 }
300 // End of $RCSfile: cpuperf.c,v $