ia64/xen-unstable

view xen/include/asm-ia64/vmmu.h @ 17601:6df8dcf48d9d

[IA64] cleanup: VTLB_PTE_IO_BIT is not used

VTLB_PTE_IO_BIT is not used any more.

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon May 12 11:24:47 2008 +0900 (2008-05-12)
parents 408fcc50fd35
children eb0fc71cfc72
line source
2 /* -*- Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
3 /*
4 * vmmu.h: virtual memory management unit related APIs and data structure.
5 * Copyright (c) 2004, Intel Corporation.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
18 * Place - Suite 330, Boston, MA 02111-1307 USA.
19 *
20 * Yaozu Dong (Eddie Dong) (Eddie.dong@intel.com)
21 */
23 #ifndef XEN_TLBthash_H
24 #define XEN_TLBthash_H
26 #define MAX_CCN_DEPTH (15) // collision chain depth
27 #define DEFAULT_VTLB_SZ (14) // 16K hash + 16K c-chain for VTLB
28 #define DEFAULT_VHPT_SZ (23) // 8M hash + 8M c-chain for VHPT
29 #define VTLB(v,_x) (v->arch.vtlb._x)
30 #define VHPT(v,_x) (v->arch.vhpt._x)
32 #ifndef __ASSEMBLY__
34 #include <xen/config.h>
35 #include <xen/types.h>
36 #include <public/xen.h>
37 #include <asm/tlb.h>
38 #include <asm/regionreg.h>
39 #include <asm/vmx_mm_def.h>
40 #include <asm/bundle.h>
42 enum {
43 ISIDE_TLB=0,
44 DSIDE_TLB=1
45 };
46 #endif /* __ASSEMBLY__ */
48 #define VTLB_PTE_P_BIT 0
49 #define VTLB_PTE_P (1UL<<VTLB_PTE_P_BIT)
51 #define ITIR_RV_MASK (((1UL<<32)-1)<<32 | 0x3)
52 #define PAGE_FLAGS_RV_MASK (0x2 | (0x3UL<<50)|(((1UL<<11)-1)<<53))
53 #define PAGE_FLAGS_AR_PL_MASK ((0x7UL<<9)|(0x3UL<<7))
55 #ifndef __ASSEMBLY__
56 typedef struct thash_data {
57 union {
58 struct {
59 u64 p : 1; // 0
60 u64 rv1 : 1; // 1
61 u64 ma : 3; // 2-4
62 u64 a : 1; // 5
63 u64 d : 1; // 6
64 u64 pl : 2; // 7-8
65 u64 ar : 3; // 9-11
66 u64 ppn : 38; // 12-49
67 u64 rv2 : 2; // 50-51
68 u64 ed : 1; // 52
69 u64 ig1 : 3; // 53-63
70 };
71 u64 page_flags;
72 }; // same for VHPT and TLB
74 union {
75 struct {
76 u64 rv3 : 2; // 0-1
77 u64 ps : 6; // 2-7
78 u64 key : 24; // 8-31
79 u64 rv4 : 32; // 32-63
80 };
81 u64 itir;
82 };
83 union {
84 struct { // For TLB
85 u64 ig2 : 12; // 0-11
86 u64 vpn : 49; // 12-60
87 u64 vrn : 3; // 61-63
88 };
89 u64 vadr;
90 u64 ifa;
91 struct { // For VHPT
92 u64 tag : 63; // 0-62
93 u64 ti : 1; // 63, invalid entry for VHPT
94 };
95 u64 etag; // extended tag for VHPT
96 };
97 union {
98 struct thash_data *next;
99 u64 rid; // only used in guest TR
100 // u64 tr_idx;
101 };
102 } thash_data_t;
104 #define INVALIDATE_VHPT_HEADER(hdata) \
105 { ((hdata)->page_flags)=0; \
106 ((hdata)->itir)=PAGE_SHIFT<<2; \
107 ((hdata)->etag)=1UL<<63; \
108 ((hdata)->next)=0;}
110 #define INVALIDATE_TLB_HEADER(hash) INVALIDATE_VHPT_HEADER(hash)
112 #define INVALIDATE_HASH_HEADER(hcb,hash) INVALIDATE_VHPT_HEADER(hash)
114 #define INVALID_VHPT(hdata) ((hdata)->ti)
115 #define INVALID_TLB(hdata) ((hdata)->ti)
116 #define INVALID_TR(hdata) (!(hdata)->p)
117 #define INVALID_ENTRY(hcb, hdata) INVALID_VHPT(hdata)
119 static inline u64 thash_translate(thash_data_t *hdata, u64 vadr)
120 {
121 int ps = hdata->ps;
122 return (hdata->ppn >> (ps - 12) << ps) | (vadr & ((1UL << ps) - 1));
123 }
125 typedef struct thash_cb {
126 /* THASH base information */
127 thash_data_t *hash; // hash table pointer, aligned at thash_sz.
128 u64 hash_sz; // size of above data.
129 void *cch_buf; // base address of collision chain.
130 u64 cch_sz; // size of above data.
131 u64 cch_free_idx; // index of free entry.
132 thash_data_t *cch_freelist;
133 PTA pta;
134 } thash_cb_t;
136 /*
137 * Allocate and initialize internal control data before service.
138 */
139 extern int thash_alloc(thash_cb_t *hcb, u64 sz, char *what);
141 extern void thash_free(thash_cb_t *hcb);
143 /*
144 * Insert an entry to hash table.
145 * NOTES:
146 * 1: TLB entry may be TR, TC or Foreign Map. For TR entry,
147 * itr[]/dtr[] need to be updated too.
148 * 2: Inserting to collision chain may trigger recycling if
149 * the buffer for collision chain is empty.
150 * 3: The new entry is inserted at the hash table.
151 * (I.e. head of the collision chain)
152 * 4: Return the entry in hash table or collision chain.
153 *
154 */
155 //extern void thash_insert(thash_cb_t *hcb, thash_data_t *entry, u64 va);
156 //extern void thash_tr_insert(thash_cb_t *hcb, thash_data_t *entry, u64 va, int idx);
157 extern int vtr_find_overlap(struct vcpu *vcpu, u64 va, u64 ps, int is_data);
159 /*
160 * Find and purge overlap entries in hash table and its collision chain.
161 * PARAS:
162 * 1: in: TLB format entry, rid:ps must be same with vrr[].
163 * rid, va & ps identify the address space for purge
164 * 2: section can be combination of TR, TC and FM. (thash_SECTION_XX)
165 * 3: cl means I side or D side.
166 * NOTES:
167 *
168 */
169 extern void thash_purge_entries(struct vcpu *v, u64 va, u64 ps);
170 extern void thash_purge_entries_remote(struct vcpu *v, u64 va, u64 ps);
171 extern int thash_purge_and_insert(struct vcpu *v, u64 pte, u64 itir, u64 ifa, int type);
173 /*
174 * Purge all TCs or VHPT entries including those in Hash table.
175 *
176 */
177 extern void thash_purge_all(struct vcpu *v);
179 /*
180 * Lookup the hash table and its collision chain to find an entry
181 * covering this address rid:va.
182 *
183 */
184 extern thash_data_t *vtlb_lookup(struct vcpu *v,u64 va,int is_data);
187 extern int init_domain_tlb(struct vcpu *v);
188 extern void free_domain_tlb(struct vcpu *v);
189 extern thash_data_t * vhpt_lookup(u64 va);
190 extern unsigned long fetch_code(struct vcpu *vcpu, u64 gip, IA64_BUNDLE *pbundle);
191 extern void emulate_io_inst(struct vcpu *vcpu, u64 padr, u64 ma, u64 iot);
192 extern void emulate_io_update(struct vcpu *vcpu, u64 word, u64 d, u64 d1);
193 extern int vhpt_enabled(struct vcpu *vcpu, uint64_t vadr, vhpt_ref_t ref);
194 extern void thash_vhpt_insert(struct vcpu *v, u64 pte, u64 itir, u64 ifa,
195 int type);
196 extern u64 guest_vhpt_lookup(u64 iha, u64 *pte);
197 extern int vhpt_access_rights_fixup(struct vcpu *v, u64 ifa, int is_data);
199 /*
200 * Purge machine tlb.
201 * INPUT
202 * rr: guest rr.
203 * va: only bits 0:60 is valid
204 * size: bits format (1<<size) for the address range to purge.
205 *
206 */
207 static inline void machine_tlb_purge(u64 va, u64 ps)
208 {
209 ia64_ptcl(va, ps << 2);
210 }
212 static inline void vmx_vcpu_set_tr (thash_data_t *trp, u64 pte, u64 itir, u64 va, u64 rid)
213 {
214 trp->page_flags = pte;
215 trp->itir = itir;
216 trp->vadr = va;
217 trp->rid = rid;
218 }
220 #endif /* __ASSEMBLY__ */
222 #endif /* XEN_TLBthash_H */