ia64/xen-unstable

view xen/arch/x86/smpboot.c @ 19107:696351cde9a4

Allow memflags to be specified to alloc_xenheap_pages().

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Jan 28 16:58:41 2009 +0000 (2009-01-28)
parents 9f9ba1a7cc92
children 4c92a04f4f5e
line source
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 *
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
9 *
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
13 *
14 * This code is released under the GNU General Public License version 2 or
15 * later.
16 *
17 * Fixes
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
28 * from Jose Renau
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <xen/config.h>
37 #include <xen/init.h>
38 #include <xen/kernel.h>
39 #include <xen/mm.h>
40 #include <xen/domain.h>
41 #include <xen/sched.h>
42 #include <xen/irq.h>
43 #include <xen/delay.h>
44 #include <xen/softirq.h>
45 #include <xen/serial.h>
46 #include <xen/numa.h>
47 #include <asm/current.h>
48 #include <asm/mc146818rtc.h>
49 #include <asm/desc.h>
50 #include <asm/div64.h>
51 #include <asm/flushtlb.h>
52 #include <asm/msr.h>
53 #include <asm/mtrr.h>
54 #include <mach_apic.h>
55 #include <mach_wakecpu.h>
56 #include <smpboot_hooks.h>
57 #include <xen/stop_machine.h>
58 #include <acpi/cpufreq/processor_perf.h>
60 #define set_kernel_exec(x, y) (0)
61 #define setup_trampoline() (bootsym_phys(trampoline_realmode_entry))
63 /* Set if we find a B stepping CPU */
64 static int __devinitdata smp_b_stepping;
66 /* Package ID of each logical CPU */
67 int phys_proc_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
69 /* Core ID of each logical CPU */
70 int cpu_core_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
72 /* representing HT siblings of each logical CPU */
73 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
74 EXPORT_SYMBOL(cpu_sibling_map);
76 /* representing HT and core siblings of each logical CPU */
77 cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
78 EXPORT_SYMBOL(cpu_core_map);
80 /* bitmap of online cpus */
81 cpumask_t cpu_online_map __read_mostly;
82 EXPORT_SYMBOL(cpu_online_map);
84 cpumask_t cpu_callin_map;
85 cpumask_t cpu_callout_map;
86 EXPORT_SYMBOL(cpu_callout_map);
87 cpumask_t cpu_possible_map;
88 EXPORT_SYMBOL(cpu_possible_map);
89 static cpumask_t smp_commenced_mask;
91 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
92 * is no way to resync one AP against BP. TBD: for prescott and above, we
93 * should use IA64's algorithm
94 */
95 static int __devinitdata tsc_sync_disabled;
97 /* Per CPU bogomips and other parameters */
98 struct cpuinfo_x86 cpu_data[NR_CPUS];
99 EXPORT_SYMBOL(cpu_data);
101 u32 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
102 { [0 ... NR_CPUS-1] = -1U };
103 EXPORT_SYMBOL(x86_cpu_to_apicid);
105 static void map_cpu_to_logical_apicid(void);
106 /* State of each CPU. */
107 DEFINE_PER_CPU(int, cpu_state) = { 0 };
109 static void *stack_base[NR_CPUS];
110 static DEFINE_SPINLOCK(cpu_add_remove_lock);
112 /*
113 * The bootstrap kernel entry code has set these up. Save them for
114 * a given CPU
115 */
117 static void __devinit smp_store_cpu_info(int id)
118 {
119 struct cpuinfo_x86 *c = cpu_data + id;
121 *c = boot_cpu_data;
122 if (id!=0)
123 identify_cpu(c);
124 /*
125 * Mask B, Pentium, but not Pentium MMX
126 */
127 if (c->x86_vendor == X86_VENDOR_INTEL &&
128 c->x86 == 5 &&
129 c->x86_mask >= 1 && c->x86_mask <= 4 &&
130 c->x86_model <= 3)
131 /*
132 * Remember we have B step Pentia with bugs
133 */
134 smp_b_stepping = 1;
136 /*
137 * Certain Athlons might work (for various values of 'work') in SMP
138 * but they are not certified as MP capable.
139 */
140 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
142 /* Athlon 660/661 is valid. */
143 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
144 goto valid_k7;
146 /* Duron 670 is valid */
147 if ((c->x86_model==7) && (c->x86_mask==0))
148 goto valid_k7;
150 /*
151 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
152 * It's worth noting that the A5 stepping (662) of some Athlon XP's
153 * have the MP bit set.
154 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
155 */
156 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
157 ((c->x86_model==7) && (c->x86_mask>=1)) ||
158 (c->x86_model> 7))
159 if (cpu_has_mp)
160 goto valid_k7;
162 /* If we get here, it's not a certified SMP capable AMD system. */
163 add_taint(TAINT_UNSAFE_SMP);
164 }
166 valid_k7:
167 ;
168 }
170 /*
171 * TSC synchronization.
172 *
173 * We first check whether all CPUs have their TSC's synchronized,
174 * then we print a warning if not, and always resync.
175 */
177 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
178 static atomic_t tsc_count_start = ATOMIC_INIT(0);
179 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
180 static unsigned long long tsc_values[NR_CPUS];
182 #define NR_LOOPS 5
184 static void __init synchronize_tsc_bp (void)
185 {
186 int i;
187 unsigned long long t0;
188 unsigned long long sum, avg;
189 long long delta;
190 unsigned int one_usec;
191 int buggy = 0;
193 printk("checking TSC synchronization across %u CPUs: ", num_booting_cpus());
195 /* convert from kcyc/sec to cyc/usec */
196 one_usec = cpu_khz / 1000;
198 atomic_set(&tsc_start_flag, 1);
199 wmb();
201 /*
202 * We loop a few times to get a primed instruction cache,
203 * then the last pass is more or less synchronized and
204 * the BP and APs set their cycle counters to zero all at
205 * once. This reduces the chance of having random offsets
206 * between the processors, and guarantees that the maximum
207 * delay between the cycle counters is never bigger than
208 * the latency of information-passing (cachelines) between
209 * two CPUs.
210 */
211 for (i = 0; i < NR_LOOPS; i++) {
212 /*
213 * all APs synchronize but they loop on '== num_cpus'
214 */
215 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1)
216 mb();
217 atomic_set(&tsc_count_stop, 0);
218 wmb();
219 /*
220 * this lets the APs save their current TSC:
221 */
222 atomic_inc(&tsc_count_start);
224 rdtscll(tsc_values[smp_processor_id()]);
225 /*
226 * We clear the TSC in the last loop:
227 */
228 if (i == NR_LOOPS-1)
229 write_tsc(0, 0);
231 /*
232 * Wait for all APs to leave the synchronization point:
233 */
234 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1)
235 mb();
236 atomic_set(&tsc_count_start, 0);
237 wmb();
238 atomic_inc(&tsc_count_stop);
239 }
241 sum = 0;
242 for (i = 0; i < NR_CPUS; i++) {
243 if (cpu_isset(i, cpu_callout_map)) {
244 t0 = tsc_values[i];
245 sum += t0;
246 }
247 }
248 avg = sum;
249 do_div(avg, num_booting_cpus());
251 sum = 0;
252 for (i = 0; i < NR_CPUS; i++) {
253 if (!cpu_isset(i, cpu_callout_map))
254 continue;
255 delta = tsc_values[i] - avg;
256 if (delta < 0)
257 delta = -delta;
258 /*
259 * We report bigger than 2 microseconds clock differences.
260 */
261 if (delta > 2*one_usec) {
262 long realdelta;
263 if (!buggy) {
264 buggy = 1;
265 printk("\n");
266 }
267 realdelta = delta;
268 do_div(realdelta, one_usec);
269 if (tsc_values[i] < avg)
270 realdelta = -realdelta;
272 printk("CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta);
273 }
275 sum += delta;
276 }
277 if (!buggy)
278 printk("passed.\n");
279 }
281 static void __init synchronize_tsc_ap (void)
282 {
283 int i;
285 /*
286 * Not every cpu is online at the time
287 * this gets called, so we first wait for the BP to
288 * finish SMP initialization:
289 */
290 while (!atomic_read(&tsc_start_flag)) mb();
292 for (i = 0; i < NR_LOOPS; i++) {
293 atomic_inc(&tsc_count_start);
294 while (atomic_read(&tsc_count_start) != num_booting_cpus())
295 mb();
297 rdtscll(tsc_values[smp_processor_id()]);
298 if (i == NR_LOOPS-1)
299 write_tsc(0, 0);
301 atomic_inc(&tsc_count_stop);
302 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
303 }
304 }
305 #undef NR_LOOPS
307 extern void calibrate_delay(void);
309 static atomic_t init_deasserted;
311 void __devinit smp_callin(void)
312 {
313 int cpuid, phys_id, i;
315 /*
316 * If waken up by an INIT in an 82489DX configuration
317 * we may get here before an INIT-deassert IPI reaches
318 * our local APIC. We have to wait for the IPI or we'll
319 * lock up on an APIC access.
320 */
321 wait_for_init_deassert(&init_deasserted);
323 if ( x2apic_enabled )
324 enable_x2apic();
326 /*
327 * (This works even if the APIC is not enabled.)
328 */
329 phys_id = get_apic_id();
330 cpuid = smp_processor_id();
331 if (cpu_isset(cpuid, cpu_callin_map)) {
332 printk("huh, phys CPU#%d, CPU#%d already present??\n",
333 phys_id, cpuid);
334 BUG();
335 }
336 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
338 /*
339 * STARTUP IPIs are fragile beasts as they might sometimes
340 * trigger some glue motherboard logic. Complete APIC bus
341 * silence for 1 second, this overestimates the time the
342 * boot CPU is spending to send the up to 2 STARTUP IPIs
343 * by a factor of two. This should be enough.
344 */
346 /*
347 * Waiting 2s total for startup
348 */
349 for (i = 0; i < 200; i++) {
350 /*
351 * Has the boot CPU finished it's STARTUP sequence?
352 */
353 if (cpu_isset(cpuid, cpu_callout_map))
354 break;
355 rep_nop();
356 mdelay(10);
357 }
359 if (!cpu_isset(cpuid, cpu_callout_map)) {
360 printk("BUG: CPU%d started up but did not get a callout!\n",
361 cpuid);
362 BUG();
363 }
365 /*
366 * the boot CPU has finished the init stage and is spinning
367 * on callin_map until we finish. We are free to set up this
368 * CPU, first the APIC. (this is probably redundant on most
369 * boards)
370 */
372 Dprintk("CALLIN, before setup_local_APIC().\n");
373 smp_callin_clear_local_apic();
374 setup_local_APIC();
375 map_cpu_to_logical_apicid();
377 #if 0
378 /*
379 * Get our bogomips.
380 */
381 calibrate_delay();
382 Dprintk("Stack at about %p\n",&cpuid);
383 #endif
385 /*
386 * Save our processor parameters
387 */
388 smp_store_cpu_info(cpuid);
390 disable_APIC_timer();
392 /*
393 * Allow the master to continue.
394 */
395 cpu_set(cpuid, cpu_callin_map);
397 /*
398 * Synchronize the TSC with the BP
399 */
400 if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled) {
401 synchronize_tsc_ap();
402 /* No sync for same reason as above */
403 calibrate_tsc_ap();
404 }
405 }
407 static int cpucount, booting_cpu;
409 /* representing cpus for which sibling maps can be computed */
410 static cpumask_t cpu_sibling_setup_map;
412 static inline void
413 set_cpu_sibling_map(int cpu)
414 {
415 int i;
416 struct cpuinfo_x86 *c = cpu_data;
418 cpu_set(cpu, cpu_sibling_setup_map);
420 if (c[cpu].x86_num_siblings > 1) {
421 for_each_cpu_mask(i, cpu_sibling_setup_map) {
422 if (phys_proc_id[cpu] == phys_proc_id[i] &&
423 cpu_core_id[cpu] == cpu_core_id[i]) {
424 cpu_set(i, cpu_sibling_map[cpu]);
425 cpu_set(cpu, cpu_sibling_map[i]);
426 cpu_set(i, cpu_core_map[cpu]);
427 cpu_set(cpu, cpu_core_map[i]);
428 }
429 }
430 } else {
431 cpu_set(cpu, cpu_sibling_map[cpu]);
432 }
434 if (c[cpu].x86_max_cores == 1) {
435 cpu_core_map[cpu] = cpu_sibling_map[cpu];
436 c[cpu].booted_cores = 1;
437 return;
438 }
440 for_each_cpu_mask(i, cpu_sibling_setup_map) {
441 if (phys_proc_id[cpu] == phys_proc_id[i]) {
442 cpu_set(i, cpu_core_map[cpu]);
443 cpu_set(cpu, cpu_core_map[i]);
444 /*
445 * Does this new cpu bringup a new core?
446 */
447 if (cpus_weight(cpu_sibling_map[cpu]) == 1) {
448 /*
449 * for each core in package, increment
450 * the booted_cores for this new cpu
451 */
452 if (first_cpu(cpu_sibling_map[i]) == i)
453 c[cpu].booted_cores++;
454 /*
455 * increment the core count for all
456 * the other cpus in this package
457 */
458 if (i != cpu)
459 c[i].booted_cores++;
460 } else if (i != cpu && !c[cpu].booted_cores)
461 c[cpu].booted_cores = c[i].booted_cores;
462 }
463 }
464 }
466 static void construct_percpu_idt(unsigned int cpu)
467 {
468 unsigned char idt_load[10];
470 *(unsigned short *)(&idt_load[0]) = (IDT_ENTRIES*sizeof(idt_entry_t))-1;
471 *(unsigned long *)(&idt_load[2]) = (unsigned long)idt_tables[cpu];
472 __asm__ __volatile__ ( "lidt %0" : "=m" (idt_load) );
473 }
475 /*
476 * Activate a secondary processor.
477 */
478 void __devinit start_secondary(void *unused)
479 {
480 /*
481 * Dont put anything before smp_callin(), SMP
482 * booting is too fragile that we want to limit the
483 * things done here to the most necessary things.
484 */
485 unsigned int cpu = booting_cpu;
487 set_processor_id(cpu);
488 set_current(idle_vcpu[cpu]);
489 this_cpu(curr_vcpu) = idle_vcpu[cpu];
490 if ( cpu_has_efer )
491 rdmsrl(MSR_EFER, this_cpu(efer));
492 asm volatile ( "mov %%cr4,%0" : "=r" (this_cpu(cr4)) );
494 percpu_traps_init();
496 cpu_init();
497 /*preempt_disable();*/
498 smp_callin();
499 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
500 rep_nop();
502 /*
503 * At this point, boot CPU has fully initialised the IDT. It is
504 * now safe to make ourselves a private copy.
505 */
506 construct_percpu_idt(cpu);
508 setup_secondary_APIC_clock();
509 enable_APIC_timer();
510 /*
511 * low-memory mappings have been cleared, flush them from
512 * the local TLBs too.
513 */
514 flush_tlb_local();
516 /* This must be done before setting cpu_online_map */
517 set_cpu_sibling_map(raw_smp_processor_id());
518 wmb();
520 cpu_set(smp_processor_id(), cpu_online_map);
521 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
523 init_percpu_time();
525 /* We can take interrupts now: we're officially "up". */
526 local_irq_enable();
528 microcode_resume_cpu(cpu);
530 wmb();
531 startup_cpu_idle_loop();
532 }
534 extern struct {
535 void * esp;
536 unsigned short ss;
537 } stack_start;
539 u32 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
541 static void map_cpu_to_logical_apicid(void)
542 {
543 int cpu = smp_processor_id();
544 int apicid = logical_smp_processor_id();
546 cpu_2_logical_apicid[cpu] = apicid;
547 }
549 static void unmap_cpu_to_logical_apicid(int cpu)
550 {
551 cpu_2_logical_apicid[cpu] = BAD_APICID;
552 }
554 #if APIC_DEBUG
555 static inline void __inquire_remote_apic(int apicid)
556 {
557 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
558 char *names[] = { "ID", "VERSION", "SPIV" };
559 int timeout, status;
561 printk("Inquiring remote APIC #%d...\n", apicid);
563 for (i = 0; i < ARRAY_SIZE(regs); i++) {
564 printk("... APIC #%d %s: ", apicid, names[i]);
566 /*
567 * Wait for idle.
568 */
569 apic_wait_icr_idle();
571 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
573 timeout = 0;
574 do {
575 udelay(100);
576 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
577 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
579 switch (status) {
580 case APIC_ICR_RR_VALID:
581 status = apic_read(APIC_RRR);
582 printk("%08x\n", status);
583 break;
584 default:
585 printk("failed\n");
586 }
587 }
588 }
589 #endif
591 #ifdef WAKE_SECONDARY_VIA_NMI
593 static int logical_apicid_to_cpu(int logical_apicid)
594 {
595 int i;
597 for ( i = 0; i < sizeof(cpu_2_logical_apicid); i++ )
598 if ( cpu_2_logical_apicid[i] == logical_apicid )
599 break;
601 if ( i == sizeof(cpu_2_logical_apicid) );
602 i = -1; /* not found */
604 return i;
605 }
607 /*
608 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
609 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
610 * won't ... remember to clear down the APIC, etc later.
611 */
612 static int __devinit
613 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
614 {
615 unsigned long send_status = 0, accept_status = 0;
616 int timeout, maxlvt;
617 int dest_cpu;
618 u32 dest;
620 dest_cpu = logical_apicid_to_cpu(logical_apicid);
621 BUG_ON(dest_cpu == -1);
623 dest = cpu_physical_id(dest_cpu);
625 /* Boot on the stack */
626 apic_icr_write(APIC_DM_NMI | APIC_DEST_PHYSICAL, dest_cpu);
628 Dprintk("Waiting for send to finish...\n");
629 timeout = 0;
630 do {
631 Dprintk("+");
632 udelay(100);
633 if ( !x2apic_enabled )
634 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
635 else
636 send_status = 0; /* We go out of the loop directly. */
637 } while (send_status && (timeout++ < 1000));
639 /*
640 * Give the other CPU some time to accept the IPI.
641 */
642 udelay(200);
643 /*
644 * Due to the Pentium erratum 3AP.
645 */
646 maxlvt = get_maxlvt();
647 if (maxlvt > 3) {
648 apic_read_around(APIC_SPIV);
649 apic_write(APIC_ESR, 0);
650 }
651 accept_status = (apic_read(APIC_ESR) & 0xEF);
652 Dprintk("NMI sent.\n");
654 if (send_status)
655 printk("APIC never delivered???\n");
656 if (accept_status)
657 printk("APIC delivery error (%lx).\n", accept_status);
659 return (send_status | accept_status);
660 }
661 #endif /* WAKE_SECONDARY_VIA_NMI */
663 #ifdef WAKE_SECONDARY_VIA_INIT
664 static int __devinit
665 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
666 {
667 unsigned long send_status = 0, accept_status = 0;
668 int maxlvt, timeout, num_starts, j;
670 /*
671 * Be paranoid about clearing APIC errors.
672 */
673 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
674 apic_read_around(APIC_SPIV);
675 apic_write(APIC_ESR, 0);
676 apic_read(APIC_ESR);
677 }
679 Dprintk("Asserting INIT.\n");
681 /*
682 * Turn INIT on target chip via IPI
683 */
684 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
685 phys_apicid);
687 Dprintk("Waiting for send to finish...\n");
688 timeout = 0;
689 do {
690 Dprintk("+");
691 udelay(100);
692 if ( !x2apic_enabled )
693 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
694 else
695 send_status = 0; /* We go out of the loop dirctly. */
696 } while (send_status && (timeout++ < 1000));
698 mdelay(10);
700 Dprintk("Deasserting INIT.\n");
702 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
704 Dprintk("Waiting for send to finish...\n");
705 timeout = 0;
706 do {
707 Dprintk("+");
708 udelay(100);
709 if ( !x2apic_enabled )
710 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
711 else
712 send_status = 0; /* We go out of the loop dirctly. */
713 } while (send_status && (timeout++ < 1000));
715 atomic_set(&init_deasserted, 1);
717 /*
718 * Should we send STARTUP IPIs ?
719 *
720 * Determine this based on the APIC version.
721 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
722 */
723 if (APIC_INTEGRATED(apic_version[phys_apicid]))
724 num_starts = 2;
725 else
726 num_starts = 0;
728 /*
729 * Run STARTUP IPI loop.
730 */
731 Dprintk("#startup loops: %d.\n", num_starts);
733 maxlvt = get_maxlvt();
735 for (j = 1; j <= num_starts; j++) {
736 Dprintk("Sending STARTUP #%d.\n",j);
737 apic_read_around(APIC_SPIV);
738 apic_write(APIC_ESR, 0);
739 apic_read(APIC_ESR);
740 Dprintk("After apic_write.\n");
742 /*
743 * STARTUP IPI
744 * Boot on the stack
745 */
746 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), phys_apicid);
748 /*
749 * Give the other CPU some time to accept the IPI.
750 */
751 udelay(300);
753 Dprintk("Startup point 1.\n");
755 Dprintk("Waiting for send to finish...\n");
756 timeout = 0;
757 do {
758 Dprintk("+");
759 udelay(100);
760 if ( !x2apic_enabled )
761 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
762 else
763 send_status = 0; /* We go out of the loop dirctly. */
764 } while (send_status && (timeout++ < 1000));
766 /*
767 * Give the other CPU some time to accept the IPI.
768 */
769 udelay(200);
770 /*
771 * Due to the Pentium erratum 3AP.
772 */
773 if (maxlvt > 3) {
774 apic_read_around(APIC_SPIV);
775 apic_write(APIC_ESR, 0);
776 }
777 accept_status = (apic_read(APIC_ESR) & 0xEF);
778 if (send_status || accept_status)
779 break;
780 }
781 Dprintk("After Startup.\n");
783 if (send_status)
784 printk("APIC never delivered???\n");
785 if (accept_status)
786 printk("APIC delivery error (%lx).\n", accept_status);
788 return (send_status | accept_status);
789 }
790 #endif /* WAKE_SECONDARY_VIA_INIT */
792 extern cpumask_t cpu_initialized;
793 static inline int alloc_cpu_id(void)
794 {
795 cpumask_t tmp_map;
796 int cpu;
797 cpus_complement(tmp_map, cpu_present_map);
798 cpu = first_cpu(tmp_map);
799 if (cpu >= NR_CPUS)
800 return -ENODEV;
801 return cpu;
802 }
804 static void *prepare_idle_stack(unsigned int cpu)
805 {
806 if (!stack_base[cpu])
807 stack_base[cpu] = alloc_xenheap_pages(STACK_ORDER, 0);
809 return stack_base[cpu];
810 }
812 static int __devinit do_boot_cpu(int apicid, int cpu)
813 /*
814 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
815 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
816 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
817 */
818 {
819 unsigned long boot_error;
820 unsigned int order;
821 int timeout;
822 unsigned long start_eip;
823 unsigned short nmi_high = 0, nmi_low = 0;
824 struct vcpu *v;
825 struct desc_struct *gdt;
826 #ifdef __x86_64__
827 struct page_info *page;
828 #endif
830 /*
831 * Save current MTRR state in case it was changed since early boot
832 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
833 */
834 mtrr_save_state();
836 ++cpucount;
838 booting_cpu = cpu;
840 v = alloc_idle_vcpu(cpu);
841 BUG_ON(v == NULL);
843 /* start_eip had better be page-aligned! */
844 start_eip = setup_trampoline();
846 /* So we see what's up */
847 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
849 stack_start.esp = prepare_idle_stack(cpu);
851 /* Debug build: detect stack overflow by setting up a guard page. */
852 memguard_guard_stack(stack_start.esp);
854 gdt = per_cpu(gdt_table, cpu);
855 if (gdt == boot_cpu_gdt_table) {
856 order = get_order_from_pages(NR_RESERVED_GDT_PAGES);
857 #ifdef __x86_64__
858 #ifdef CONFIG_COMPAT
859 page = alloc_domheap_pages(NULL, order,
860 MEMF_node(cpu_to_node(cpu)));
861 per_cpu(compat_gdt_table, cpu) = gdt = page_to_virt(page);
862 memcpy(gdt, boot_cpu_compat_gdt_table,
863 NR_RESERVED_GDT_PAGES * PAGE_SIZE);
864 gdt[PER_CPU_GDT_ENTRY - FIRST_RESERVED_GDT_ENTRY].a = cpu;
865 #endif
866 page = alloc_domheap_pages(NULL, order,
867 MEMF_node(cpu_to_node(cpu)));
868 per_cpu(gdt_table, cpu) = gdt = page_to_virt(page);
869 #else
870 per_cpu(gdt_table, cpu) = gdt = alloc_xenheap_pages(order, 0);
871 #endif
872 memcpy(gdt, boot_cpu_gdt_table,
873 NR_RESERVED_GDT_PAGES * PAGE_SIZE);
874 BUILD_BUG_ON(NR_CPUS > 0x10000);
875 gdt[PER_CPU_GDT_ENTRY - FIRST_RESERVED_GDT_ENTRY].a = cpu;
876 }
878 #ifdef __i386__
879 if (!per_cpu(doublefault_tss, cpu)) {
880 per_cpu(doublefault_tss, cpu) = alloc_xenheap_page();
881 memset(per_cpu(doublefault_tss, cpu), 0, PAGE_SIZE);
882 }
883 #endif
885 if (!idt_tables[cpu]) {
886 idt_tables[cpu] = xmalloc_array(idt_entry_t, IDT_ENTRIES);
887 memcpy(idt_tables[cpu], idt_table,
888 IDT_ENTRIES*sizeof(idt_entry_t));
889 }
891 /*
892 * This grunge runs the startup process for
893 * the targeted processor.
894 */
896 atomic_set(&init_deasserted, 0);
898 Dprintk("Setting warm reset code and vector.\n");
900 store_NMI_vector(&nmi_high, &nmi_low);
902 smpboot_setup_warm_reset_vector(start_eip);
904 /*
905 * Starting actual IPI sequence...
906 */
907 boot_error = wakeup_secondary_cpu(apicid, start_eip);
909 if (!boot_error) {
910 /*
911 * allow APs to start initializing.
912 */
913 Dprintk("Before Callout %d.\n", cpu);
914 cpu_set(cpu, cpu_callout_map);
915 Dprintk("After Callout %d.\n", cpu);
917 /*
918 * Wait 5s total for a response
919 */
920 for (timeout = 0; timeout < 50000; timeout++) {
921 if (cpu_isset(cpu, cpu_callin_map))
922 break; /* It has booted */
923 udelay(100);
924 }
926 if (cpu_isset(cpu, cpu_callin_map)) {
927 /* number CPUs logically, starting from 1 (BSP is 0) */
928 Dprintk("OK.\n");
929 printk("CPU%d: ", cpu);
930 print_cpu_info(&cpu_data[cpu]);
931 Dprintk("CPU has booted.\n");
932 } else {
933 boot_error = 1;
934 mb();
935 if (bootsym(trampoline_cpu_started) == 0xA5)
936 /* trampoline started but...? */
937 printk("Stuck ??\n");
938 else
939 /* trampoline code not run */
940 printk("Not responding.\n");
941 inquire_remote_apic(apicid);
942 }
943 }
945 if (boot_error) {
946 /* Try to put things back the way they were before ... */
947 unmap_cpu_to_logical_apicid(cpu);
948 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
949 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
950 cpucount--;
951 } else {
952 x86_cpu_to_apicid[cpu] = apicid;
953 cpu_set(cpu, cpu_present_map);
954 }
956 /* mark "stuck" area as not stuck */
957 bootsym(trampoline_cpu_started) = 0;
958 mb();
960 return boot_error;
961 }
963 #ifdef CONFIG_HOTPLUG_CPU
964 static void idle_task_exit(void)
965 {
966 /* Give up lazy state borrowed by this idle vcpu */
967 __sync_lazy_execstate();
968 }
970 void cpu_exit_clear(void)
971 {
972 int cpu = raw_smp_processor_id();
974 idle_task_exit();
976 cpucount --;
977 cpu_uninit();
979 cpu_clear(cpu, cpu_callout_map);
980 cpu_clear(cpu, cpu_callin_map);
982 cpu_clear(cpu, smp_commenced_mask);
983 unmap_cpu_to_logical_apicid(cpu);
984 }
986 static int __cpuinit __smp_prepare_cpu(int cpu)
987 {
988 int apicid, ret;
990 apicid = x86_cpu_to_apicid[cpu];
991 if (apicid == BAD_APICID) {
992 ret = -ENODEV;
993 goto exit;
994 }
996 tsc_sync_disabled = 1;
998 do_boot_cpu(apicid, cpu);
1000 tsc_sync_disabled = 0;
1002 ret = 0;
1003 exit:
1004 return ret;
1006 #endif
1008 /*
1009 * Cycle through the processors sending APIC IPIs to boot each.
1010 */
1012 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1013 void *xquad_portio;
1014 #ifdef CONFIG_X86_NUMAQ
1015 EXPORT_SYMBOL(xquad_portio);
1016 #endif
1018 static void __init smp_boot_cpus(unsigned int max_cpus)
1020 int apicid, cpu, bit, kicked;
1021 #ifdef BOGOMIPS
1022 unsigned long bogosum = 0;
1023 #endif
1025 /*
1026 * Setup boot CPU information
1027 */
1028 smp_store_cpu_info(0); /* Final full version of the data */
1029 printk("CPU%d: ", 0);
1030 print_cpu_info(&cpu_data[0]);
1032 boot_cpu_physical_apicid = get_apic_id();
1033 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
1035 stack_base[0] = stack_start.esp;
1037 /*current_thread_info()->cpu = 0;*/
1038 /*smp_tune_scheduling();*/
1040 set_cpu_sibling_map(0);
1042 /*
1043 * If we couldn't find an SMP configuration at boot time,
1044 * get out of here now!
1045 */
1046 if (!smp_found_config && !acpi_lapic) {
1047 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1048 init_uniprocessor:
1049 phys_cpu_present_map = physid_mask_of_physid(0);
1050 if (APIC_init_uniprocessor())
1051 printk(KERN_NOTICE "Local APIC not detected."
1052 " Using dummy APIC emulation.\n");
1053 map_cpu_to_logical_apicid();
1054 cpu_set(0, cpu_sibling_map[0]);
1055 cpu_set(0, cpu_core_map[0]);
1056 return;
1059 /*
1060 * Should not be necessary because the MP table should list the boot
1061 * CPU too, but we do it for the sake of robustness anyway.
1062 * Makes no sense to do this check in clustered apic mode, so skip it
1063 */
1064 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1065 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1066 boot_cpu_physical_apicid);
1067 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1070 /*
1071 * If we couldn't find a local APIC, then get out of here now!
1072 */
1073 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
1074 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1075 boot_cpu_physical_apicid);
1076 goto init_uniprocessor;
1079 verify_local_APIC();
1081 /*
1082 * If SMP should be disabled, then really disable it!
1083 */
1084 if (!max_cpus)
1085 goto init_uniprocessor;
1087 connect_bsp_APIC();
1088 setup_local_APIC();
1089 map_cpu_to_logical_apicid();
1092 setup_portio_remap();
1094 /*
1095 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1097 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1098 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1099 * clustered apic ID.
1100 */
1101 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1103 kicked = 1;
1104 for (bit = 0; kicked < NR_CPUS && bit < NR_CPUS; bit++) {
1105 apicid = cpu_present_to_apicid(bit);
1106 /*
1107 * Don't even attempt to start the boot CPU!
1108 */
1109 if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
1110 continue;
1112 if (!check_apicid_present(apicid))
1113 continue;
1114 if (max_cpus <= cpucount+1)
1115 continue;
1117 if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
1118 printk("CPU #%d not responding - cannot use it.\n",
1119 apicid);
1120 else
1121 ++kicked;
1124 /*
1125 * Cleanup possible dangling ends...
1126 */
1127 smpboot_restore_warm_reset_vector();
1129 #ifdef BOGOMIPS
1130 /*
1131 * Allow the user to impress friends.
1132 */
1133 Dprintk("Before bogomips.\n");
1134 for (cpu = 0; cpu < NR_CPUS; cpu++)
1135 if (cpu_isset(cpu, cpu_callout_map))
1136 bogosum += cpu_data[cpu].loops_per_jiffy;
1137 printk(KERN_INFO
1138 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1139 cpucount+1,
1140 bogosum/(500000/HZ),
1141 (bogosum/(5000/HZ))%100);
1142 #else
1143 printk("Total of %d processors activated.\n", cpucount+1);
1144 #endif
1146 Dprintk("Before bogocount - setting activated=1.\n");
1148 if (smp_b_stepping)
1149 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1151 /*
1152 * Don't taint if we are running SMP kernel on a single non-MP
1153 * approved Athlon
1154 */
1155 if (tainted & TAINT_UNSAFE_SMP) {
1156 if (cpucount)
1157 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1158 else
1159 tainted &= ~TAINT_UNSAFE_SMP;
1162 Dprintk("Boot done.\n");
1164 /*
1165 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1166 * efficiently.
1167 */
1168 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1169 cpus_clear(cpu_sibling_map[cpu]);
1170 cpus_clear(cpu_core_map[cpu]);
1173 cpu_set(0, cpu_sibling_map[0]);
1174 cpu_set(0, cpu_core_map[0]);
1176 if (nmi_watchdog == NMI_LOCAL_APIC)
1177 check_nmi_watchdog();
1179 smpboot_setup_io_apic();
1181 setup_boot_APIC_clock();
1183 /*
1184 * Synchronize the TSC with the AP
1185 */
1186 if (cpu_has_tsc && cpucount && cpu_khz)
1187 synchronize_tsc_bp();
1188 calibrate_tsc_bp();
1191 /* These are wrappers to interface to the new boot process. Someone
1192 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1193 void __init smp_prepare_cpus(unsigned int max_cpus)
1195 smp_commenced_mask = cpumask_of_cpu(0);
1196 cpu_callin_map = cpumask_of_cpu(0);
1197 mb();
1198 smp_boot_cpus(max_cpus);
1201 void __devinit smp_prepare_boot_cpu(void)
1203 cpu_set(smp_processor_id(), cpu_online_map);
1204 cpu_set(smp_processor_id(), cpu_callout_map);
1205 cpu_set(smp_processor_id(), cpu_present_map);
1206 cpu_set(smp_processor_id(), cpu_possible_map);
1207 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
1210 #ifdef CONFIG_HOTPLUG_CPU
1211 static void
1212 remove_siblinginfo(int cpu)
1214 int sibling;
1215 struct cpuinfo_x86 *c = cpu_data;
1217 for_each_cpu_mask(sibling, cpu_core_map[cpu]) {
1218 cpu_clear(cpu, cpu_core_map[sibling]);
1219 /*
1220 * last thread sibling in this cpu core going down
1221 */
1222 if (cpus_weight(cpu_sibling_map[cpu]) == 1)
1223 c[sibling].booted_cores--;
1226 for_each_cpu_mask(sibling, cpu_sibling_map[cpu])
1227 cpu_clear(cpu, cpu_sibling_map[sibling]);
1228 cpus_clear(cpu_sibling_map[cpu]);
1229 cpus_clear(cpu_core_map[cpu]);
1230 phys_proc_id[cpu] = BAD_APICID;
1231 cpu_core_id[cpu] = BAD_APICID;
1232 cpu_clear(cpu, cpu_sibling_setup_map);
1235 extern void fixup_irqs(cpumask_t map);
1236 int __cpu_disable(void)
1238 cpumask_t map = cpu_online_map;
1239 int cpu = smp_processor_id();
1241 /*
1242 * Perhaps use cpufreq to drop frequency, but that could go
1243 * into generic code.
1245 * We won't take down the boot processor on i386 due to some
1246 * interrupts only being able to be serviced by the BSP.
1247 * Especially so if we're not using an IOAPIC -zwane
1248 */
1249 if (cpu == 0)
1250 return -EBUSY;
1252 local_irq_disable();
1253 clear_local_APIC();
1254 /* Allow any queued timer interrupts to get serviced */
1255 local_irq_enable();
1256 mdelay(1);
1257 local_irq_disable();
1259 cpufreq_del_cpu(cpu);
1261 time_suspend();
1263 cpu_mcheck_disable();
1265 remove_siblinginfo(cpu);
1267 cpu_clear(cpu, map);
1268 fixup_irqs(map);
1269 /* It's now safe to remove this processor from the online map */
1270 cpu_clear(cpu, cpu_online_map);
1272 cpu_disable_scheduler();
1274 return 0;
1277 void __cpu_die(unsigned int cpu)
1279 /* We don't do anything here: idle task is faking death itself. */
1280 unsigned int i = 0;
1282 for (;;) {
1283 /* They ack this in play_dead by setting CPU_DEAD */
1284 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1285 printk ("CPU %u is now offline\n", cpu);
1286 return;
1288 mdelay(100);
1289 mb();
1290 process_pending_timers();
1291 if ((++i % 10) == 0)
1292 printk(KERN_ERR "CPU %u still not dead...\n", cpu);
1296 static int take_cpu_down(void *unused)
1298 return __cpu_disable();
1301 int cpu_down(unsigned int cpu)
1303 int err = 0;
1305 spin_lock(&cpu_add_remove_lock);
1306 if (num_online_cpus() == 1) {
1307 err = -EBUSY;
1308 goto out;
1311 /* Can not offline BSP */
1312 if (cpu == 0) {
1313 err = -EINVAL;
1314 goto out;
1317 if (!cpu_online(cpu)) {
1318 err = -EINVAL;
1319 goto out;
1322 printk("Prepare to bring CPU%d down...\n", cpu);
1324 err = stop_machine_run(take_cpu_down, NULL, cpu);
1325 if (err < 0)
1326 goto out;
1328 __cpu_die(cpu);
1330 BUG_ON(cpu_online(cpu));
1332 cpu_mcheck_distribute_cmci();
1334 out:
1335 spin_unlock(&cpu_add_remove_lock);
1336 return err;
1339 int cpu_up(unsigned int cpu)
1341 int err = 0;
1343 spin_lock(&cpu_add_remove_lock);
1344 if (cpu_online(cpu)) {
1345 printk("Bring up a online cpu. Bogus!\n");
1346 err = -EBUSY;
1347 goto out;
1350 err = __cpu_up(cpu);
1351 if (err < 0)
1352 goto out;
1354 out:
1355 spin_unlock(&cpu_add_remove_lock);
1356 return err;
1359 /* From kernel/power/main.c */
1360 /* This is protected by pm_sem semaphore */
1361 static cpumask_t frozen_cpus;
1363 void disable_nonboot_cpus(void)
1365 int cpu, error;
1367 error = 0;
1368 cpus_clear(frozen_cpus);
1369 printk("Freezing cpus ...\n");
1370 for_each_online_cpu(cpu) {
1371 if (cpu == 0)
1372 continue;
1373 error = cpu_down(cpu);
1374 if (!error) {
1375 cpu_set(cpu, frozen_cpus);
1376 printk("CPU%d is down\n", cpu);
1377 continue;
1379 printk("Error taking cpu %d down: %d\n", cpu, error);
1381 BUG_ON(raw_smp_processor_id() != 0);
1382 if (error)
1383 panic("cpus not sleeping");
1386 void enable_nonboot_cpus(void)
1388 int cpu, error;
1390 printk("Thawing cpus ...\n");
1391 for_each_cpu_mask(cpu, frozen_cpus) {
1392 error = cpu_up(cpu);
1393 if (!error) {
1394 printk("CPU%d is up\n", cpu);
1395 continue;
1397 printk("Error taking cpu %d up: %d\n", cpu, error);
1398 panic("Not enough cpus");
1400 cpus_clear(frozen_cpus);
1402 /*
1403 * Cleanup possible dangling ends after sleep...
1404 */
1405 smpboot_restore_warm_reset_vector();
1407 #else /* ... !CONFIG_HOTPLUG_CPU */
1408 int __cpu_disable(void)
1410 return -ENOSYS;
1413 void __cpu_die(unsigned int cpu)
1415 /* We said "no" in __cpu_disable */
1416 BUG();
1418 #endif /* CONFIG_HOTPLUG_CPU */
1420 int __devinit __cpu_up(unsigned int cpu)
1422 #ifdef CONFIG_HOTPLUG_CPU
1423 int ret=0;
1425 /*
1426 * We do warm boot only on cpus that had booted earlier
1427 * Otherwise cold boot is all handled from smp_boot_cpus().
1428 * cpu_callin_map is set during AP kickstart process. Its reset
1429 * when a cpu is taken offline from cpu_exit_clear().
1430 */
1431 if (!cpu_isset(cpu, cpu_callin_map))
1432 ret = __smp_prepare_cpu(cpu);
1434 if (ret)
1435 return -EIO;
1436 #endif
1438 /* In case one didn't come up */
1439 if (!cpu_isset(cpu, cpu_callin_map)) {
1440 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1441 local_irq_enable();
1442 return -EIO;
1445 local_irq_enable();
1446 /*per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;*/
1447 /* Unleash the CPU! */
1448 cpu_set(cpu, smp_commenced_mask);
1449 while (!cpu_isset(cpu, cpu_online_map)) {
1450 mb();
1451 process_pending_timers();
1454 cpufreq_add_cpu(cpu);
1455 return 0;
1459 void __init smp_cpus_done(unsigned int max_cpus)
1461 #ifdef CONFIG_X86_IO_APIC
1462 setup_ioapic_dest();
1463 #endif
1464 #ifndef CONFIG_HOTPLUG_CPU
1465 /*
1466 * Disable executability of the SMP trampoline:
1467 */
1468 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1469 #endif
1472 void __init smp_intr_init(void)
1474 int irq, seridx;
1476 /*
1477 * IRQ0 must be given a fixed assignment and initialized,
1478 * because it's used before the IO-APIC is set up.
1479 */
1480 irq_vector[0] = FIRST_HIPRIORITY_VECTOR;
1481 vector_irq[FIRST_HIPRIORITY_VECTOR] = 0;
1483 /*
1484 * Also ensure serial interrupts are high priority. We do not
1485 * want them to be blocked by unacknowledged guest-bound interrupts.
1486 */
1487 for (seridx = 0; seridx < 2; seridx++) {
1488 if ((irq = serial_irq(seridx)) < 0)
1489 continue;
1490 irq_vector[irq] = FIRST_HIPRIORITY_VECTOR + seridx + 1;
1491 vector_irq[FIRST_HIPRIORITY_VECTOR + seridx + 1] = irq;
1494 /* IPI for event checking. */
1495 set_intr_gate(EVENT_CHECK_VECTOR, event_check_interrupt);
1497 /* IPI for invalidation */
1498 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1500 /* IPI for generic function call */
1501 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);