ia64/xen-unstable

view xen/arch/x86/apic.c @ 19650:6705898f768d

x86: eliminate hard-coded NR_IRQS

... splitting it into global nr_irqs (determined at boot time) and
per- domain nr_pirqs (derived from nr_irqs and a possibly command line
specified value, which probably should later become a per-domain
config setting).

This has the (desirable imo) side effect of reducing the size of
struct hvm_irq_dpci from requiring an order-3 page to order-2 (on
x86-64), which nevertheless still is too large.

However, there is now a variable size bit array on the stack in
pt_irq_time_out() - while for the moment this probably is okay, it
certainly doesn't look nice. However, replacing this with a static
(pre-)allocation also seems less than ideal, because that would
require at least min(d->nr_pirqs, NR_VECTORS) bit arrays of
d->nr_pirqs bits, since this bit array is used outside of the
serialized code region in that function, and keeping the domain's
event lock acquired across pirq_guest_eoi() doesn't look like a good
idea either.

The IRQ- and vector-indexed arrays hanging off struct hvm_irq_dpci
could in fact be changed further to dynamically use the smaller of the
two ranges for indexing, since there are other assumptions about a
one-to-one relationship between IRQs and vectors here and elsewhere.

Additionally, it seems to me that struct hvm_mirq_dpci_mapping's
digl_list and gmsi fields could really be overlayed, which would yield
significant savings since this structure gets always instanciated in
form of d->nr_pirqs (as per the above could also be the smaller of
this and NR_VECTORS) dimensioned arrays.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed May 27 10:38:51 2009 +0100 (2009-05-27)
parents 085d22289e1b
children
line source
1 /*
2 * based on linux-2.6.17.13/arch/i386/kernel/apic.c
3 *
4 * Local APIC handling, local APIC timers
5 *
6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
10 * thanks to Eric Gilmore
11 * and Rolf G. Tews
12 * for testing these extensively.
13 * Maciej W. Rozycki : Various updates and fixes.
14 * Mikael Pettersson : Power Management for UP-APIC.
15 * Pavel Machek and
16 * Mikael Pettersson : PM converted to driver model.
17 */
19 #include <xen/config.h>
20 #include <xen/perfc.h>
21 #include <xen/errno.h>
22 #include <xen/init.h>
23 #include <xen/mm.h>
24 #include <xen/sched.h>
25 #include <xen/irq.h>
26 #include <xen/delay.h>
27 #include <xen/smp.h>
28 #include <xen/softirq.h>
29 #include <asm/mc146818rtc.h>
30 #include <asm/msr.h>
31 #include <asm/atomic.h>
32 #include <asm/mpspec.h>
33 #include <asm/flushtlb.h>
34 #include <asm/hardirq.h>
35 #include <asm/apic.h>
36 #include <asm/io_apic.h>
37 #include <mach_apic.h>
38 #include <io_ports.h>
40 /*
41 * Knob to control our willingness to enable the local APIC.
42 */
43 static int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
45 /*
46 * Debug level
47 */
48 int apic_verbosity;
50 int x2apic_enabled __read_mostly = 0;
53 static void apic_pm_activate(void);
55 int modern_apic(void)
56 {
57 unsigned int lvr, version;
58 /* AMD systems use old APIC versions, so check the CPU */
59 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
60 boot_cpu_data.x86 >= 0xf)
61 return 1;
62 lvr = apic_read(APIC_LVR);
63 version = GET_APIC_VERSION(lvr);
64 return version >= 0x14;
65 }
67 /*
68 * 'what should we do if we get a hw irq event on an illegal vector'.
69 * each architecture has to answer this themselves.
70 */
71 void ack_bad_irq(unsigned int irq)
72 {
73 printk("unexpected IRQ trap at vector %02x\n", irq);
74 /*
75 * Currently unexpected vectors happen only on SMP and APIC.
76 * We _must_ ack these because every local APIC has only N
77 * irq slots per priority level, and a 'hanging, unacked' IRQ
78 * holds up an irq slot - in excessive cases (when multiple
79 * unexpected vectors occur) that might lock up the APIC
80 * completely.
81 * But only ack when the APIC is enabled -AK
82 */
83 if (cpu_has_apic)
84 ack_APIC_irq();
85 }
87 void __init apic_intr_init(void)
88 {
89 #ifdef CONFIG_SMP
90 smp_intr_init();
91 #endif
92 /* self generated IPI for local APIC timer */
93 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
95 /* IPI vectors for APIC spurious and error interrupts */
96 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
97 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
99 /* Performance Counters Interrupt */
100 set_intr_gate(PMU_APIC_VECTOR, pmu_apic_interrupt);
102 /* CMCI Correctable Machine Check Interrupt */
103 set_intr_gate(CMCI_APIC_VECTOR, cmci_interrupt);
105 /* thermal monitor LVT interrupt, for P4 and latest Intel CPU*/
106 #ifdef CONFIG_X86_MCE_THERMAL
107 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
108 #endif
109 }
111 /* Using APIC to generate smp_local_timer_interrupt? */
112 int using_apic_timer = 0;
114 static int enabled_via_apicbase;
116 void enable_NMI_through_LVT0 (void * dummy)
117 {
118 unsigned int v, ver;
120 ver = apic_read(APIC_LVR);
121 ver = GET_APIC_VERSION(ver);
122 v = APIC_DM_NMI; /* unmask and set to NMI */
123 if (!APIC_INTEGRATED(ver)) /* 82489DX */
124 v |= APIC_LVT_LEVEL_TRIGGER;
125 apic_write_around(APIC_LVT0, v);
126 }
128 int get_physical_broadcast(void)
129 {
130 if (modern_apic())
131 return 0xff;
132 else
133 return 0xf;
134 }
136 int get_maxlvt(void)
137 {
138 unsigned int v, ver, maxlvt;
140 v = apic_read(APIC_LVR);
141 ver = GET_APIC_VERSION(v);
142 /* 82489DXs do not report # of LVT entries. */
143 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
144 return maxlvt;
145 }
147 void clear_local_APIC(void)
148 {
149 int maxlvt;
150 unsigned long v;
152 maxlvt = get_maxlvt();
154 /*
155 * Masking an LVT entry on a P6 can trigger a local APIC error
156 * if the vector is zero. Mask LVTERR first to prevent this.
157 */
158 if (maxlvt >= 3) {
159 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
160 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
161 }
162 /*
163 * Careful: we have to set masks only first to deassert
164 * any level-triggered sources.
165 */
166 v = apic_read(APIC_LVTT);
167 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
168 v = apic_read(APIC_LVT0);
169 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
170 v = apic_read(APIC_LVT1);
171 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
172 if (maxlvt >= 4) {
173 v = apic_read(APIC_LVTPC);
174 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
175 }
177 /* lets not touch this if we didn't frob it */
178 #ifdef CONFIG_X86_MCE_THERMAL
179 if (maxlvt >= 5) {
180 v = apic_read(APIC_LVTTHMR);
181 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
182 }
183 #endif
185 if (maxlvt >= 6) {
186 v = apic_read(APIC_CMCI);
187 apic_write_around(APIC_CMCI, v | APIC_LVT_MASKED);
188 }
189 /*
190 * Clean APIC state for other OSs:
191 */
192 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
193 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
194 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
195 if (maxlvt >= 3)
196 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
197 if (maxlvt >= 4)
198 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
200 #ifdef CONFIG_X86_MCE_THERMAL
201 if (maxlvt >= 5)
202 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
203 #endif
204 if (maxlvt >= 6)
205 apic_write_around(APIC_CMCI, APIC_LVT_MASKED);
207 v = GET_APIC_VERSION(apic_read(APIC_LVR));
208 if (APIC_INTEGRATED(v)) { /* !82489DX */
209 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
210 apic_write(APIC_ESR, 0);
211 apic_read(APIC_ESR);
212 }
213 }
215 void __init connect_bsp_APIC(void)
216 {
217 if (pic_mode) {
218 /*
219 * Do not trust the local APIC being empty at bootup.
220 */
221 clear_local_APIC();
222 /*
223 * PIC mode, enable APIC mode in the IMCR, i.e.
224 * connect BSP's local APIC to INT and NMI lines.
225 */
226 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
227 "enabling APIC mode.\n");
228 outb(0x70, 0x22);
229 outb(0x01, 0x23);
230 }
231 enable_apic_mode();
232 }
234 void disconnect_bsp_APIC(int virt_wire_setup)
235 {
236 if (pic_mode) {
237 /*
238 * Put the board back into PIC mode (has an effect
239 * only on certain older boards). Note that APIC
240 * interrupts, including IPIs, won't work beyond
241 * this point! The only exception are INIT IPIs.
242 */
243 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
244 "entering PIC mode.\n");
245 outb(0x70, 0x22);
246 outb(0x00, 0x23);
247 }
248 else {
249 /* Go back to Virtual Wire compatibility mode */
250 unsigned long value;
252 /* For the spurious interrupt use vector F, and enable it */
253 value = apic_read(APIC_SPIV);
254 value &= ~APIC_VECTOR_MASK;
255 value |= APIC_SPIV_APIC_ENABLED;
256 value |= 0xf;
257 apic_write_around(APIC_SPIV, value);
259 if (!virt_wire_setup) {
260 /* For LVT0 make it edge triggered, active high, external and enabled */
261 value = apic_read(APIC_LVT0);
262 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
263 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
264 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
265 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
266 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
267 apic_write_around(APIC_LVT0, value);
268 }
269 else {
270 /* Disable LVT0 */
271 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
272 }
274 /* For LVT1 make it edge triggered, active high, nmi and enabled */
275 value = apic_read(APIC_LVT1);
276 value &= ~(
277 APIC_MODE_MASK | APIC_SEND_PENDING |
278 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
279 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
280 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
281 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
282 apic_write_around(APIC_LVT1, value);
283 }
284 }
286 void disable_local_APIC(void)
287 {
288 unsigned long value;
290 clear_local_APIC();
292 /*
293 * Disable APIC (implies clearing of registers
294 * for 82489DX!).
295 */
296 value = apic_read(APIC_SPIV);
297 value &= ~APIC_SPIV_APIC_ENABLED;
298 apic_write_around(APIC_SPIV, value);
300 if (enabled_via_apicbase) {
301 unsigned int l, h;
302 rdmsr(MSR_IA32_APICBASE, l, h);
303 l &= ~MSR_IA32_APICBASE_ENABLE;
304 wrmsr(MSR_IA32_APICBASE, l, h);
305 }
306 }
308 /*
309 * This is to verify that we're looking at a real local APIC.
310 * Check these against your board if the CPUs aren't getting
311 * started for no apparent reason.
312 */
313 int __init verify_local_APIC(void)
314 {
315 unsigned int reg0, reg1;
317 /*
318 * The version register is read-only in a real APIC.
319 */
320 reg0 = apic_read(APIC_LVR);
321 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
323 /* We don't try writing LVR in x2APIC mode since that incurs #GP. */
324 if ( !x2apic_enabled )
325 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
326 reg1 = apic_read(APIC_LVR);
327 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
329 /*
330 * The two version reads above should print the same
331 * numbers. If the second one is different, then we
332 * poke at a non-APIC.
333 */
334 if (reg1 != reg0)
335 return 0;
337 /*
338 * Check if the version looks reasonably.
339 */
340 reg1 = GET_APIC_VERSION(reg0);
341 if (reg1 == 0x00 || reg1 == 0xff)
342 return 0;
343 reg1 = get_maxlvt();
344 if (reg1 < 0x02 || reg1 == 0xff)
345 return 0;
347 /*
348 * The ID register is read/write in a real APIC.
349 */
350 reg0 = apic_read(APIC_ID);
351 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
353 /*
354 * The next two are just to see if we have sane values.
355 * They're only really relevant if we're in Virtual Wire
356 * compatibility mode, but most boxes are anymore.
357 */
358 reg0 = apic_read(APIC_LVT0);
359 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
360 reg1 = apic_read(APIC_LVT1);
361 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
363 return 1;
364 }
366 void __init sync_Arb_IDs(void)
367 {
368 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1
369 And not needed on AMD */
370 if (modern_apic())
371 return;
372 /*
373 * Wait for idle.
374 */
375 apic_wait_icr_idle();
377 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
378 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
379 | APIC_DM_INIT);
380 }
382 extern void __error_in_apic_c (void);
384 /*
385 * An initial setup of the virtual wire mode.
386 */
387 void __init init_bsp_APIC(void)
388 {
389 unsigned long value, ver;
391 /*
392 * Don't do the setup now if we have a SMP BIOS as the
393 * through-I/O-APIC virtual wire mode might be active.
394 */
395 if (smp_found_config || !cpu_has_apic)
396 return;
398 value = apic_read(APIC_LVR);
399 ver = GET_APIC_VERSION(value);
401 /*
402 * Do not trust the local APIC being empty at bootup.
403 */
404 clear_local_APIC();
406 /*
407 * Enable APIC.
408 */
409 value = apic_read(APIC_SPIV);
410 value &= ~APIC_VECTOR_MASK;
411 value |= APIC_SPIV_APIC_ENABLED;
413 /* This bit is reserved on P4/Xeon and should be cleared */
414 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
415 value &= ~APIC_SPIV_FOCUS_DISABLED;
416 else
417 value |= APIC_SPIV_FOCUS_DISABLED;
418 value |= SPURIOUS_APIC_VECTOR;
419 apic_write_around(APIC_SPIV, value);
421 /*
422 * Set up the virtual wire mode.
423 */
424 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
425 value = APIC_DM_NMI;
426 if (!APIC_INTEGRATED(ver)) /* 82489DX */
427 value |= APIC_LVT_LEVEL_TRIGGER;
428 apic_write_around(APIC_LVT1, value);
429 }
431 void __devinit setup_local_APIC(void)
432 {
433 unsigned long oldvalue, value, ver, maxlvt;
434 int i, j;
436 /* Pound the ESR really hard over the head with a big hammer - mbligh */
437 if (esr_disable) {
438 apic_write(APIC_ESR, 0);
439 apic_write(APIC_ESR, 0);
440 apic_write(APIC_ESR, 0);
441 apic_write(APIC_ESR, 0);
442 }
444 value = apic_read(APIC_LVR);
445 ver = GET_APIC_VERSION(value);
447 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
448 __error_in_apic_c();
450 /*
451 * Double-check whether this APIC is really registered.
452 */
453 if (!apic_id_registered())
454 BUG();
456 /*
457 * Intel recommends to set DFR, LDR and TPR before enabling
458 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
459 * document number 292116). So here it goes...
460 */
461 init_apic_ldr();
463 /*
464 * Set Task Priority to 'accept all'. We never change this
465 * later on.
466 */
467 value = apic_read(APIC_TASKPRI);
468 value &= ~APIC_TPRI_MASK;
469 apic_write_around(APIC_TASKPRI, value);
471 /*
472 * After a crash, we no longer service the interrupts and a pending
473 * interrupt from previous kernel might still have ISR bit set.
474 *
475 * Most probably by now CPU has serviced that pending interrupt and
476 * it might not have done the ack_APIC_irq() because it thought,
477 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
478 * does not clear the ISR bit and cpu thinks it has already serivced
479 * the interrupt. Hence a vector might get locked. It was noticed
480 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
481 */
482 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
483 value = apic_read(APIC_ISR + i*0x10);
484 for (j = 31; j >= 0; j--) {
485 if (value & (1<<j))
486 ack_APIC_irq();
487 }
488 }
490 /*
491 * Now that we are all set up, enable the APIC
492 */
493 value = apic_read(APIC_SPIV);
494 value &= ~APIC_VECTOR_MASK;
495 /*
496 * Enable APIC
497 */
498 value |= APIC_SPIV_APIC_ENABLED;
500 /*
501 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
502 * certain networking cards. If high frequency interrupts are
503 * happening on a particular IOAPIC pin, plus the IOAPIC routing
504 * entry is masked/unmasked at a high rate as well then sooner or
505 * later IOAPIC line gets 'stuck', no more interrupts are received
506 * from the device. If focus CPU is disabled then the hang goes
507 * away, oh well :-(
508 *
509 * [ This bug can be reproduced easily with a level-triggered
510 * PCI Ne2000 networking cards and PII/PIII processors, dual
511 * BX chipset. ]
512 */
513 /*
514 * Actually disabling the focus CPU check just makes the hang less
515 * frequent as it makes the interrupt distributon model be more
516 * like LRU than MRU (the short-term load is more even across CPUs).
517 * See also the comment in end_level_ioapic_irq(). --macro
518 */
519 #if 1
520 /* Enable focus processor (bit==0) */
521 value &= ~APIC_SPIV_FOCUS_DISABLED;
522 #else
523 /* Disable focus processor (bit==1) */
524 value |= APIC_SPIV_FOCUS_DISABLED;
525 #endif
526 /*
527 * Set spurious IRQ vector
528 */
529 value |= SPURIOUS_APIC_VECTOR;
530 apic_write_around(APIC_SPIV, value);
532 /*
533 * Set up LVT0, LVT1:
534 *
535 * set up through-local-APIC on the BP's LINT0. This is not
536 * strictly necessery in pure symmetric-IO mode, but sometimes
537 * we delegate interrupts to the 8259A.
538 */
539 /*
540 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
541 */
542 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
543 if (!smp_processor_id() && (pic_mode || !value)) {
544 value = APIC_DM_EXTINT;
545 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
546 smp_processor_id());
547 } else {
548 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
549 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
550 smp_processor_id());
551 }
552 apic_write_around(APIC_LVT0, value);
554 /*
555 * only the BP should see the LINT1 NMI signal, obviously.
556 */
557 if (!smp_processor_id())
558 value = APIC_DM_NMI;
559 else
560 value = APIC_DM_NMI | APIC_LVT_MASKED;
561 if (!APIC_INTEGRATED(ver)) /* 82489DX */
562 value |= APIC_LVT_LEVEL_TRIGGER;
563 apic_write_around(APIC_LVT1, value);
565 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
566 maxlvt = get_maxlvt();
567 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
568 apic_write(APIC_ESR, 0);
569 oldvalue = apic_read(APIC_ESR);
571 value = ERROR_APIC_VECTOR; // enables sending errors
572 apic_write_around(APIC_LVTERR, value);
573 /*
574 * spec says clear errors after enabling vector.
575 */
576 if (maxlvt > 3)
577 apic_write(APIC_ESR, 0);
578 value = apic_read(APIC_ESR);
579 if (value != oldvalue)
580 apic_printk(APIC_VERBOSE, "ESR value before enabling "
581 "vector: 0x%08lx after: 0x%08lx\n",
582 oldvalue, value);
583 } else {
584 if (esr_disable)
585 /*
586 * Something untraceble is creating bad interrupts on
587 * secondary quads ... for the moment, just leave the
588 * ESR disabled - we can't do anything useful with the
589 * errors anyway - mbligh
590 */
591 printk("Leaving ESR disabled.\n");
592 else
593 printk("No ESR for 82489DX.\n");
594 }
596 if (nmi_watchdog == NMI_LOCAL_APIC)
597 setup_apic_nmi_watchdog();
598 apic_pm_activate();
599 }
601 static struct {
602 int active;
603 /* r/w apic fields */
604 unsigned int apic_id;
605 unsigned int apic_taskpri;
606 unsigned int apic_ldr;
607 unsigned int apic_dfr;
608 unsigned int apic_spiv;
609 unsigned int apic_lvtt;
610 unsigned int apic_lvtpc;
611 unsigned int apic_lvtcmci;
612 unsigned int apic_lvt0;
613 unsigned int apic_lvt1;
614 unsigned int apic_lvterr;
615 unsigned int apic_tmict;
616 unsigned int apic_tdcr;
617 unsigned int apic_thmr;
618 } apic_pm_state;
620 int lapic_suspend(void)
621 {
622 unsigned long flags;
623 int maxlvt = get_maxlvt();
624 if (!apic_pm_state.active)
625 return 0;
627 apic_pm_state.apic_id = apic_read(APIC_ID);
628 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
629 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
630 if ( !x2apic_enabled )
631 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
632 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
633 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
634 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
636 if (maxlvt >= 6) {
637 apic_pm_state.apic_lvtcmci = apic_read(APIC_CMCI);
638 }
640 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
641 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
642 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
643 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
644 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
645 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
647 local_irq_save(flags);
648 disable_local_APIC();
649 local_irq_restore(flags);
650 return 0;
651 }
653 int lapic_resume(void)
654 {
655 unsigned int l, h;
656 unsigned long flags;
657 int maxlvt = get_maxlvt();
659 if (!apic_pm_state.active)
660 return 0;
662 local_irq_save(flags);
664 /*
665 * Make sure the APICBASE points to the right address
666 *
667 * FIXME! This will be wrong if we ever support suspend on
668 * SMP! We'll need to do this as part of the CPU restore!
669 */
670 if ( !x2apic_enabled )
671 {
672 rdmsr(MSR_IA32_APICBASE, l, h);
673 l &= ~MSR_IA32_APICBASE_BASE;
674 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
675 wrmsr(MSR_IA32_APICBASE, l, h);
676 }
677 else
678 enable_x2apic();
680 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
681 apic_write(APIC_ID, apic_pm_state.apic_id);
682 if ( !x2apic_enabled )
683 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
684 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
685 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
686 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
687 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
688 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
689 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
691 if (maxlvt >= 6) {
692 apic_write(APIC_CMCI, apic_pm_state.apic_lvtcmci);
693 }
695 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
696 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
697 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
698 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
699 apic_write(APIC_ESR, 0);
700 apic_read(APIC_ESR);
701 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
702 apic_write(APIC_ESR, 0);
703 apic_read(APIC_ESR);
704 local_irq_restore(flags);
705 return 0;
706 }
709 /*
710 * If Linux enabled the LAPIC against the BIOS default
711 * disable it down before re-entering the BIOS on shutdown.
712 * Otherwise the BIOS may get confused and not power-off.
713 * Additionally clear all LVT entries before disable_local_APIC
714 * for the case where Linux didn't enable the LAPIC.
715 */
716 void lapic_shutdown(void)
717 {
718 unsigned long flags;
720 if (!cpu_has_apic)
721 return;
723 local_irq_save(flags);
724 clear_local_APIC();
726 if (enabled_via_apicbase)
727 disable_local_APIC();
729 local_irq_restore(flags);
730 }
732 static void apic_pm_activate(void)
733 {
734 apic_pm_state.active = 1;
735 }
737 /*
738 * Detect and enable local APICs on non-SMP boards.
739 * Original code written by Keir Fraser.
740 */
742 static void __init lapic_disable(char *str)
743 {
744 enable_local_apic = -1;
745 setup_clear_cpu_cap(X86_FEATURE_APIC);
746 }
747 custom_param("nolapic", lapic_disable);
749 static void __init lapic_enable(char *str)
750 {
751 enable_local_apic = 1;
752 }
753 custom_param("lapic", lapic_enable);
755 static void __init apic_set_verbosity(char *str)
756 {
757 if (strcmp("debug", str) == 0)
758 apic_verbosity = APIC_DEBUG;
759 else if (strcmp("verbose", str) == 0)
760 apic_verbosity = APIC_VERBOSE;
761 else
762 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
763 " use apic_verbosity=verbose or apic_verbosity=debug", str);
764 }
765 custom_param("apic_verbosity", apic_set_verbosity);
767 static int __init detect_init_APIC (void)
768 {
769 u32 h, l, features;
771 /* Disabled by kernel option? */
772 if (enable_local_apic < 0)
773 return -1;
775 switch (boot_cpu_data.x86_vendor) {
776 case X86_VENDOR_AMD:
777 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
778 (boot_cpu_data.x86 >= 15 && boot_cpu_data.x86 <= 17))
779 break;
780 goto no_apic;
781 case X86_VENDOR_INTEL:
782 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
783 (boot_cpu_data.x86 == 5 && cpu_has_apic))
784 break;
785 goto no_apic;
786 default:
787 goto no_apic;
788 }
790 if (!cpu_has_apic) {
791 /*
792 * Over-ride BIOS and try to enable the local
793 * APIC only if "lapic" specified.
794 */
795 if (enable_local_apic <= 0) {
796 printk("Local APIC disabled by BIOS -- "
797 "you can enable it with \"lapic\"\n");
798 return -1;
799 }
800 /*
801 * Some BIOSes disable the local APIC in the
802 * APIC_BASE MSR. This can only be done in
803 * software for Intel P6 or later and AMD K7
804 * (Model > 1) or later.
805 */
806 rdmsr(MSR_IA32_APICBASE, l, h);
807 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
808 printk("Local APIC disabled by BIOS -- reenabling.\n");
809 l &= ~MSR_IA32_APICBASE_BASE;
810 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
811 wrmsr(MSR_IA32_APICBASE, l, h);
812 enabled_via_apicbase = 1;
813 }
814 }
815 /*
816 * The APIC feature bit should now be enabled
817 * in `cpuid'
818 */
819 features = cpuid_edx(1);
820 if (!(features & (1 << X86_FEATURE_APIC))) {
821 printk("Could not enable APIC!\n");
822 return -1;
823 }
825 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
826 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
828 /* The BIOS may have set up the APIC at some other address */
829 rdmsr(MSR_IA32_APICBASE, l, h);
830 if (l & MSR_IA32_APICBASE_ENABLE)
831 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
833 if (nmi_watchdog != NMI_NONE)
834 nmi_watchdog = NMI_LOCAL_APIC;
836 printk("Found and enabled local APIC!\n");
838 apic_pm_activate();
840 return 0;
842 no_apic:
843 printk("No local APIC present or hardware disabled\n");
844 return -1;
845 }
847 void enable_x2apic(void)
848 {
849 u32 lo, hi;
851 rdmsr(MSR_IA32_APICBASE, lo, hi);
852 if ( !(lo & MSR_IA32_APICBASE_EXTD) )
853 {
854 lo |= MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD;
855 wrmsr(MSR_IA32_APICBASE, lo, 0);
856 printk("x2APIC mode enabled.\n");
857 }
858 else
859 printk("x2APIC mode enabled by BIOS.\n");
861 x2apic_enabled = 1;
862 }
864 void __init init_apic_mappings(void)
865 {
866 unsigned long apic_phys;
868 if ( x2apic_enabled )
869 goto __next;
870 /*
871 * If no local APIC can be found then set up a fake all
872 * zeroes page to simulate the local APIC and another
873 * one for the IO-APIC.
874 */
875 if (!smp_found_config && detect_init_APIC()) {
876 apic_phys = __pa(alloc_xenheap_page());
877 clear_page(__va(apic_phys));
878 } else
879 apic_phys = mp_lapic_addr;
881 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
882 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
883 apic_phys);
885 __next:
886 /*
887 * Fetch the APIC ID of the BSP in case we have a
888 * default configuration (or the MP table is broken).
889 */
890 if (boot_cpu_physical_apicid == -1U)
891 boot_cpu_physical_apicid = get_apic_id();
893 init_ioapic_mappings();
894 }
896 /*****************************************************************************
897 * APIC calibration
898 *
899 * The APIC is programmed in bus cycles.
900 * Timeout values should specified in real time units.
901 * The "cheapest" time source is the cyclecounter.
902 *
903 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
904 *
905 * The calibration is currently a bit shoddy since it requires the external
906 * timer chip to generate periodic timer interupts.
907 *****************************************************************************/
909 /* used for system time scaling */
910 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
911 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
912 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
914 /*
915 * The timer chip is already set up at HZ interrupts per second here,
916 * but we do not accept timer interrupts yet. We only allow the BP
917 * to calibrate.
918 */
919 static unsigned int __init get_8254_timer_count(void)
920 {
921 /*extern spinlock_t i8253_lock;*/
922 /*unsigned long flags;*/
924 unsigned int count;
926 /*spin_lock_irqsave(&i8253_lock, flags);*/
928 outb_p(0x00, PIT_MODE);
929 count = inb_p(PIT_CH0);
930 count |= inb_p(PIT_CH0) << 8;
932 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
934 return count;
935 }
937 /* next tick in 8254 can be caught by catching timer wraparound */
938 static void __init wait_8254_wraparound(void)
939 {
940 unsigned int curr_count, prev_count;
942 curr_count = get_8254_timer_count();
943 do {
944 prev_count = curr_count;
945 curr_count = get_8254_timer_count();
947 /* workaround for broken Mercury/Neptune */
948 if (prev_count >= curr_count + 0x100)
949 curr_count = get_8254_timer_count();
951 } while (prev_count >= curr_count);
952 }
954 /*
955 * Default initialization for 8254 timers. If we use other timers like HPET,
956 * we override this later
957 */
958 void (*wait_timer_tick)(void) __initdata = wait_8254_wraparound;
960 /*
961 * This function sets up the local APIC timer, with a timeout of
962 * 'clocks' APIC bus clock. During calibration we actually call
963 * this function twice on the boot CPU, once with a bogus timeout
964 * value, second time for real. The other (noncalibrating) CPUs
965 * call this function only once, with the real, calibrated value.
966 *
967 * We do reads before writes even if unnecessary, to get around the
968 * P5 APIC double write bug.
969 */
971 #define APIC_DIVISOR 1
973 void __setup_APIC_LVTT(unsigned int clocks)
974 {
975 unsigned int lvtt_value, tmp_value, ver;
977 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
978 /* NB. Xen uses local APIC timer in one-shot mode. */
979 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
980 if (!APIC_INTEGRATED(ver))
981 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
982 apic_write_around(APIC_LVTT, lvtt_value);
984 tmp_value = apic_read(APIC_TDCR);
985 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
987 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
988 }
990 static void __devinit setup_APIC_timer(unsigned int clocks)
991 {
992 unsigned long flags;
993 local_irq_save(flags);
994 __setup_APIC_LVTT(clocks);
995 local_irq_restore(flags);
996 }
998 /*
999 * In this function we calibrate APIC bus clocks to the external
1000 * timer. Unfortunately we cannot use jiffies and the timer irq
1001 * to calibrate, since some later bootup code depends on getting
1002 * the first irq? Ugh.
1004 * We want to do the calibration only once since we
1005 * want to have local timer irqs syncron. CPUs connected
1006 * by the same APIC bus have the very same bus frequency.
1007 * And we want to have irqs off anyways, no accidental
1008 * APIC irq that way.
1009 */
1011 int __init calibrate_APIC_clock(void)
1013 unsigned long long t1 = 0, t2 = 0;
1014 long tt1, tt2;
1015 long result;
1016 int i;
1017 const int LOOPS = HZ/10;
1019 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
1021 /*
1022 * Put whatever arbitrary (but long enough) timeout
1023 * value into the APIC clock, we just want to get the
1024 * counter running for calibration.
1025 */
1026 __setup_APIC_LVTT(1000000000);
1028 /*
1029 * The timer chip counts down to zero. Let's wait
1030 * for a wraparound to start exact measurement:
1031 * (the current tick might have been already half done)
1032 */
1033 wait_timer_tick();
1035 /*
1036 * We wrapped around just now. Let's start:
1037 */
1038 if (cpu_has_tsc)
1039 rdtscll(t1);
1040 tt1 = apic_read(APIC_TMCCT);
1042 /*
1043 * Let's wait LOOPS wraprounds:
1044 */
1045 for (i = 0; i < LOOPS; i++)
1046 wait_timer_tick();
1048 tt2 = apic_read(APIC_TMCCT);
1049 if (cpu_has_tsc)
1050 rdtscll(t2);
1052 /*
1053 * The APIC bus clock counter is 32 bits only, it
1054 * might have overflown, but note that we use signed
1055 * longs, thus no extra care needed.
1057 * underflown to be exact, as the timer counts down ;)
1058 */
1060 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
1062 if (cpu_has_tsc)
1063 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
1064 "%ld.%04ld MHz.\n",
1065 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
1066 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
1068 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
1069 "%ld.%04ld MHz.\n",
1070 result/(1000000/HZ),
1071 result%(1000000/HZ));
1073 /* set up multipliers for accurate timer code */
1074 bus_freq = result*HZ;
1075 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
1076 bus_scale = (1000*262144)/bus_cycle;
1078 apic_printk(APIC_VERBOSE, "..... bus_scale = 0x%08X\n", bus_scale);
1079 /* reset APIC to zero timeout value */
1080 __setup_APIC_LVTT(0);
1082 return result;
1085 u32 get_apic_bus_cycle(void)
1087 return bus_cycle;
1090 static unsigned int calibration_result;
1092 void __init setup_boot_APIC_clock(void)
1094 unsigned long flags;
1095 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n");
1096 using_apic_timer = 1;
1098 local_irq_save(flags);
1100 calibration_result = calibrate_APIC_clock();
1101 /*
1102 * Now set up the timer for real.
1103 */
1104 setup_APIC_timer(calibration_result);
1106 local_irq_restore(flags);
1109 void __devinit setup_secondary_APIC_clock(void)
1111 setup_APIC_timer(calibration_result);
1114 void disable_APIC_timer(void)
1116 if (using_apic_timer) {
1117 unsigned long v;
1119 v = apic_read(APIC_LVTT);
1120 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
1124 void enable_APIC_timer(void)
1126 if (using_apic_timer) {
1127 unsigned long v;
1129 v = apic_read(APIC_LVTT);
1130 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
1134 #undef APIC_DIVISOR
1136 /*
1137 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
1138 * returns 1 on success
1139 * returns 0 if the timeout value is too small or in the past.
1140 */
1141 int reprogram_timer(s_time_t timeout)
1143 s_time_t now;
1144 s_time_t expire;
1145 u64 apic_tmict;
1147 /*
1148 * If we don't have local APIC then we just poll the timer list off the
1149 * PIT interrupt.
1150 */
1151 if ( !cpu_has_apic )
1152 return 1;
1154 /*
1155 * We use this value because we don't trust zero (we think it may just
1156 * cause an immediate interrupt). At least this is guaranteed to hold it
1157 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
1158 */
1159 if ( timeout == 0 )
1161 apic_tmict = 0xffffffff;
1162 goto reprogram;
1165 now = NOW();
1166 expire = timeout - now; /* value from now */
1168 if ( expire <= 0 )
1170 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
1171 smp_processor_id(), (u32)(now>>32),
1172 (u32)now, (u32)(timeout>>32),(u32)timeout);
1173 return 0;
1176 /* conversion to bus units */
1177 apic_tmict = (((u64)bus_scale) * expire)>>18;
1179 if ( apic_tmict >= 0xffffffff )
1181 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
1182 apic_tmict = 0xffffffff;
1185 if ( apic_tmict == 0 )
1187 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
1188 return 0;
1191 reprogram:
1192 /* Program the timer. */
1193 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
1195 return 1;
1198 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs * regs)
1200 ack_APIC_irq();
1201 perfc_incr(apic_timer);
1202 raise_softirq(TIMER_SOFTIRQ);
1205 /*
1206 * This interrupt should _never_ happen with our APIC/SMP architecture
1207 */
1208 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs)
1210 unsigned long v;
1212 irq_enter();
1213 /*
1214 * Check if this really is a spurious interrupt and ACK it
1215 * if it is a vectored one. Just in case...
1216 * Spurious interrupts should not be ACKed.
1217 */
1218 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1219 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1220 ack_APIC_irq();
1222 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1223 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
1224 smp_processor_id());
1225 irq_exit();
1228 /*
1229 * This interrupt should never happen with our APIC/SMP architecture
1230 */
1232 fastcall void smp_error_interrupt(struct cpu_user_regs *regs)
1234 unsigned long v, v1;
1236 irq_enter();
1237 /* First tickle the hardware, only then report what went on. -- REW */
1238 v = apic_read(APIC_ESR);
1239 apic_write(APIC_ESR, 0);
1240 v1 = apic_read(APIC_ESR);
1241 ack_APIC_irq();
1242 atomic_inc(&irq_err_count);
1244 /* Here is what the APIC error bits mean:
1245 0: Send CS error
1246 1: Receive CS error
1247 2: Send accept error
1248 3: Receive accept error
1249 4: Reserved
1250 5: Send illegal vector
1251 6: Received illegal vector
1252 7: Illegal register address
1253 */
1254 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1255 smp_processor_id(), v , v1);
1256 irq_exit();
1259 /*
1260 * This interrupt handles performance counters interrupt
1261 */
1263 fastcall void smp_pmu_apic_interrupt(struct cpu_user_regs *regs)
1265 ack_APIC_irq();
1266 hvm_do_pmu_interrupt(regs);
1269 /*
1270 * This initializes the IO-APIC and APIC hardware if this is
1271 * a UP kernel.
1272 */
1273 int __init APIC_init_uniprocessor (void)
1275 if (enable_local_apic < 0)
1276 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1278 if (!smp_found_config && !cpu_has_apic) {
1279 skip_ioapic_setup = 1;
1280 return -1;
1283 /*
1284 * Complain if the BIOS pretends there is one.
1285 */
1286 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1287 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1288 boot_cpu_physical_apicid);
1289 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1290 skip_ioapic_setup = 1;
1291 return -1;
1294 verify_local_APIC();
1296 connect_bsp_APIC();
1298 /*
1299 * Hack: In case of kdump, after a crash, kernel might be booting
1300 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1301 * might be zero if read from MP tables. Get it from LAPIC.
1302 */
1303 #ifdef CONFIG_CRASH_DUMP
1304 boot_cpu_physical_apicid = get_apic_id();
1305 #endif
1306 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
1308 setup_local_APIC();
1310 if (nmi_watchdog == NMI_LOCAL_APIC)
1311 check_nmi_watchdog();
1312 #ifdef CONFIG_X86_IO_APIC
1313 if (smp_found_config)
1314 if (!skip_ioapic_setup && nr_ioapics)
1315 setup_IO_APIC();
1316 #endif
1317 setup_boot_APIC_clock();
1319 return 0;