ia64/xen-unstable

view xen/arch/x86/io_apic.c @ 18467:65dc37be0443

x86: Remove MSI boot parameter -- now always on.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Sep 10 10:47:46 2008 +0100 (2008-09-10)
parents 89d05940cc1c
children 31f09a5e24cf
line source
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
23 #include <xen/config.h>
24 #include <xen/lib.h>
25 #include <xen/init.h>
26 #include <xen/irq.h>
27 #include <xen/delay.h>
28 #include <xen/sched.h>
29 #include <xen/acpi.h>
30 #include <xen/pci.h>
31 #include <xen/pci_regs.h>
32 #include <xen/keyhandler.h>
33 #include <asm/io.h>
34 #include <asm/mc146818rtc.h>
35 #include <asm/smp.h>
36 #include <asm/desc.h>
37 #include <asm/msi.h>
38 #include <mach_apic.h>
39 #include <io_ports.h>
40 #include <public/physdev.h>
42 /* Different to Linux: our implementation can be simpler. */
43 #define make_8259A_irq(irq) (io_apic_irqs &= ~(1<<(irq)))
45 int (*ioapic_renumber_irq)(int ioapic, int irq);
46 atomic_t irq_mis_count;
48 int domain_irq_to_vector(struct domain *d, int irq)
49 {
50 return d->arch.pirq_vector[irq];
51 }
53 int domain_vector_to_irq(struct domain *d, int vector)
54 {
55 return d->arch.vector_pirq[vector];
56 }
58 /* Where if anywhere is the i8259 connect in external int mode */
59 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
61 static DEFINE_SPINLOCK(ioapic_lock);
62 static DEFINE_SPINLOCK(vector_lock);
64 int skip_ioapic_setup;
66 #ifndef sis_apic_bug
67 /*
68 * Is the SiS APIC rmw bug present?
69 * -1 = don't know, 0 = no, 1 = yes
70 */
71 int sis_apic_bug = -1;
72 #endif
74 /*
75 * # of IRQ routing registers
76 */
77 int nr_ioapic_registers[MAX_IO_APICS];
79 int disable_timer_pin_1 __initdata;
81 /*
82 * Rough estimation of how many shared IRQs there are, can
83 * be changed anytime.
84 */
85 #define MAX_PLUS_SHARED_IRQS NR_IRQS
86 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
88 /*
89 * This is performance-critical, we want to do it O(1)
90 *
91 * the indexing order of this array favors 1:1 mappings
92 * between pins and IRQs.
93 */
95 static struct irq_pin_list {
96 int apic, pin, next;
97 } irq_2_pin[PIN_MAP_SIZE];
98 static int irq_2_pin_free_entry = NR_IRQS;
100 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
102 /*
103 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
104 * shared ISA-space IRQs, so we have to support them. We are super
105 * fast in the common case, and fast for shared ISA-space IRQs.
106 */
107 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
108 {
109 struct irq_pin_list *entry = irq_2_pin + irq;
111 while (entry->next) {
112 BUG_ON((entry->apic == apic) && (entry->pin == pin));
113 entry = irq_2_pin + entry->next;
114 }
116 BUG_ON((entry->apic == apic) && (entry->pin == pin));
118 if (entry->pin != -1) {
119 if (irq_2_pin_free_entry >= PIN_MAP_SIZE)
120 panic("io_apic.c: whoops");
121 entry->next = irq_2_pin_free_entry;
122 entry = irq_2_pin + entry->next;
123 irq_2_pin_free_entry = entry->next;
124 entry->next = 0;
125 }
126 entry->apic = apic;
127 entry->pin = pin;
128 }
130 static void remove_pin_at_irq(unsigned int irq, int apic, int pin)
131 {
132 struct irq_pin_list *entry, *prev;
134 for (entry = &irq_2_pin[irq]; ; entry = &irq_2_pin[entry->next]) {
135 if ((entry->apic == apic) && (entry->pin == pin))
136 break;
137 if (!entry->next)
138 BUG();
139 }
141 entry->pin = entry->apic = -1;
143 if (entry != &irq_2_pin[irq]) {
144 /* Removed entry is not at head of list. */
145 prev = &irq_2_pin[irq];
146 while (&irq_2_pin[prev->next] != entry)
147 prev = &irq_2_pin[prev->next];
148 prev->next = entry->next;
149 entry->next = irq_2_pin_free_entry;
150 irq_2_pin_free_entry = entry - irq_2_pin;
151 } else if (entry->next != 0) {
152 /* Removed entry is at head of multi-item list. */
153 prev = entry;
154 entry = &irq_2_pin[entry->next];
155 *prev = *entry;
156 entry->pin = entry->apic = -1;
157 entry->next = irq_2_pin_free_entry;
158 irq_2_pin_free_entry = entry - irq_2_pin;
159 }
160 }
162 /*
163 * Reroute an IRQ to a different pin.
164 */
165 static void __init replace_pin_at_irq(unsigned int irq,
166 int oldapic, int oldpin,
167 int newapic, int newpin)
168 {
169 struct irq_pin_list *entry = irq_2_pin + irq;
171 while (1) {
172 if (entry->apic == oldapic && entry->pin == oldpin) {
173 entry->apic = newapic;
174 entry->pin = newpin;
175 }
176 if (!entry->next)
177 break;
178 entry = irq_2_pin + entry->next;
179 }
180 }
182 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
183 {
184 struct irq_pin_list *entry = irq_2_pin + irq;
185 unsigned int pin, reg;
187 for (;;) {
188 pin = entry->pin;
189 if (pin == -1)
190 break;
191 reg = io_apic_read(entry->apic, 0x10 + pin*2);
192 reg &= ~disable;
193 reg |= enable;
194 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
195 if (!entry->next)
196 break;
197 entry = irq_2_pin + entry->next;
198 }
199 }
201 /* mask = 1 */
202 static void __mask_IO_APIC_irq (unsigned int irq)
203 {
204 __modify_IO_APIC_irq(irq, 0x00010000, 0);
205 }
207 /* mask = 0 */
208 static void __unmask_IO_APIC_irq (unsigned int irq)
209 {
210 __modify_IO_APIC_irq(irq, 0, 0x00010000);
211 }
213 /* trigger = 0 */
214 static void __edge_IO_APIC_irq (unsigned int irq)
215 {
216 __modify_IO_APIC_irq(irq, 0, 0x00008000);
217 }
219 /* trigger = 1 */
220 static void __level_IO_APIC_irq (unsigned int irq)
221 {
222 __modify_IO_APIC_irq(irq, 0x00008000, 0);
223 }
225 static void mask_IO_APIC_irq (unsigned int irq)
226 {
227 unsigned long flags;
229 spin_lock_irqsave(&ioapic_lock, flags);
230 __mask_IO_APIC_irq(irq);
231 spin_unlock_irqrestore(&ioapic_lock, flags);
232 }
234 static void unmask_IO_APIC_irq (unsigned int irq)
235 {
236 unsigned long flags;
238 spin_lock_irqsave(&ioapic_lock, flags);
239 __unmask_IO_APIC_irq(irq);
240 spin_unlock_irqrestore(&ioapic_lock, flags);
241 }
243 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
244 {
245 struct IO_APIC_route_entry entry;
246 unsigned long flags;
248 /* Check delivery_mode to be sure we're not clearing an SMI pin */
249 spin_lock_irqsave(&ioapic_lock, flags);
250 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
251 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
252 spin_unlock_irqrestore(&ioapic_lock, flags);
253 if (entry.delivery_mode == dest_SMI)
254 return;
256 /*
257 * Disable it in the IO-APIC irq-routing table:
258 */
259 memset(&entry, 0, sizeof(entry));
260 entry.mask = 1;
261 spin_lock_irqsave(&ioapic_lock, flags);
262 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
263 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
264 spin_unlock_irqrestore(&ioapic_lock, flags);
265 }
267 static void clear_IO_APIC (void)
268 {
269 int apic, pin;
271 for (apic = 0; apic < nr_ioapics; apic++)
272 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
273 clear_IO_APIC_pin(apic, pin);
274 }
276 #ifdef CONFIG_SMP
277 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
278 {
279 unsigned long flags;
280 int pin;
281 struct irq_pin_list *entry = irq_2_pin + irq;
282 unsigned int apicid_value;
284 cpus_and(cpumask, cpumask, cpu_online_map);
285 if (cpus_empty(cpumask))
286 cpumask = TARGET_CPUS;
288 apicid_value = cpu_mask_to_apicid(cpumask);
289 /* Prepare to do the io_apic_write */
290 apicid_value = apicid_value << 24;
291 spin_lock_irqsave(&ioapic_lock, flags);
292 for (;;) {
293 pin = entry->pin;
294 if (pin == -1)
295 break;
296 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
297 if (!entry->next)
298 break;
299 entry = irq_2_pin + entry->next;
300 }
301 set_irq_info(irq, cpumask);
302 spin_unlock_irqrestore(&ioapic_lock, flags);
303 }
304 #endif /* CONFIG_SMP */
306 /*
307 * Find the IRQ entry number of a certain pin.
308 */
309 static int find_irq_entry(int apic, int pin, int type)
310 {
311 int i;
313 for (i = 0; i < mp_irq_entries; i++)
314 if (mp_irqs[i].mpc_irqtype == type &&
315 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
316 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
317 mp_irqs[i].mpc_dstirq == pin)
318 return i;
320 return -1;
321 }
323 /*
324 * Find the pin to which IRQ[irq] (ISA) is connected
325 */
326 static int __init find_isa_irq_pin(int irq, int type)
327 {
328 int i;
330 for (i = 0; i < mp_irq_entries; i++) {
331 int lbus = mp_irqs[i].mpc_srcbus;
333 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
334 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
335 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
336 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
337 ) &&
338 (mp_irqs[i].mpc_irqtype == type) &&
339 (mp_irqs[i].mpc_srcbusirq == irq))
341 return mp_irqs[i].mpc_dstirq;
342 }
343 return -1;
344 }
346 static int __init find_isa_irq_apic(int irq, int type)
347 {
348 int i;
350 for (i = 0; i < mp_irq_entries; i++) {
351 int lbus = mp_irqs[i].mpc_srcbus;
353 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
354 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
355 mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
356 mp_bus_id_to_type[lbus] == MP_BUS_NEC98
357 ) &&
358 (mp_irqs[i].mpc_irqtype == type) &&
359 (mp_irqs[i].mpc_srcbusirq == irq))
360 break;
361 }
362 if (i < mp_irq_entries) {
363 int apic;
364 for(apic = 0; apic < nr_ioapics; apic++) {
365 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
366 return apic;
367 }
368 }
370 return -1;
371 }
373 /*
374 * Find a specific PCI IRQ entry.
375 * Not an __init, possibly needed by modules
376 */
377 static int pin_2_irq(int idx, int apic, int pin);
379 /*
380 * This function currently is only a helper for the i386 smp boot process where
381 * we need to reprogram the ioredtbls to cater for the cpus which have come online
382 * so mask in all cases should simply be TARGET_CPUS
383 */
384 #ifdef CONFIG_SMP
385 void /*__init*/ setup_ioapic_dest(void)
386 {
387 int pin, ioapic, irq, irq_entry;
389 if (skip_ioapic_setup == 1)
390 return;
392 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
393 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
394 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
395 if (irq_entry == -1)
396 continue;
397 irq = pin_2_irq(irq_entry, ioapic, pin);
398 set_ioapic_affinity_irq(irq, TARGET_CPUS);
399 }
401 }
402 }
403 #endif
405 /*
406 * EISA Edge/Level control register, ELCR
407 */
408 static int EISA_ELCR(unsigned int irq)
409 {
410 if (irq < 16) {
411 unsigned int port = 0x4d0 + (irq >> 3);
412 return (inb(port) >> (irq & 7)) & 1;
413 }
414 apic_printk(APIC_VERBOSE, KERN_INFO
415 "Broken MPtable reports ISA irq %d\n", irq);
416 return 0;
417 }
419 /* EISA interrupts are always polarity zero and can be edge or level
420 * trigger depending on the ELCR value. If an interrupt is listed as
421 * EISA conforming in the MP table, that means its trigger type must
422 * be read in from the ELCR */
424 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
425 #define default_EISA_polarity(idx) (0)
427 /* ISA interrupts are always polarity zero edge triggered,
428 * when listed as conforming in the MP table. */
430 #define default_ISA_trigger(idx) (0)
431 #define default_ISA_polarity(idx) (0)
433 /* PCI interrupts are always polarity one level triggered,
434 * when listed as conforming in the MP table. */
436 #define default_PCI_trigger(idx) (1)
437 #define default_PCI_polarity(idx) (1)
439 /* MCA interrupts are always polarity zero level triggered,
440 * when listed as conforming in the MP table. */
442 #define default_MCA_trigger(idx) (1)
443 #define default_MCA_polarity(idx) (0)
445 /* NEC98 interrupts are always polarity zero edge triggered,
446 * when listed as conforming in the MP table. */
448 #define default_NEC98_trigger(idx) (0)
449 #define default_NEC98_polarity(idx) (0)
451 static int __init MPBIOS_polarity(int idx)
452 {
453 int bus = mp_irqs[idx].mpc_srcbus;
454 int polarity;
456 /*
457 * Determine IRQ line polarity (high active or low active):
458 */
459 switch (mp_irqs[idx].mpc_irqflag & 3)
460 {
461 case 0: /* conforms, ie. bus-type dependent polarity */
462 {
463 switch (mp_bus_id_to_type[bus])
464 {
465 case MP_BUS_ISA: /* ISA pin */
466 {
467 polarity = default_ISA_polarity(idx);
468 break;
469 }
470 case MP_BUS_EISA: /* EISA pin */
471 {
472 polarity = default_EISA_polarity(idx);
473 break;
474 }
475 case MP_BUS_PCI: /* PCI pin */
476 {
477 polarity = default_PCI_polarity(idx);
478 break;
479 }
480 case MP_BUS_MCA: /* MCA pin */
481 {
482 polarity = default_MCA_polarity(idx);
483 break;
484 }
485 case MP_BUS_NEC98: /* NEC 98 pin */
486 {
487 polarity = default_NEC98_polarity(idx);
488 break;
489 }
490 default:
491 {
492 printk(KERN_WARNING "broken BIOS!!\n");
493 polarity = 1;
494 break;
495 }
496 }
497 break;
498 }
499 case 1: /* high active */
500 {
501 polarity = 0;
502 break;
503 }
504 case 2: /* reserved */
505 {
506 printk(KERN_WARNING "broken BIOS!!\n");
507 polarity = 1;
508 break;
509 }
510 case 3: /* low active */
511 {
512 polarity = 1;
513 break;
514 }
515 default: /* invalid */
516 {
517 printk(KERN_WARNING "broken BIOS!!\n");
518 polarity = 1;
519 break;
520 }
521 }
522 return polarity;
523 }
525 static int MPBIOS_trigger(int idx)
526 {
527 int bus = mp_irqs[idx].mpc_srcbus;
528 int trigger;
530 /*
531 * Determine IRQ trigger mode (edge or level sensitive):
532 */
533 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
534 {
535 case 0: /* conforms, ie. bus-type dependent */
536 {
537 switch (mp_bus_id_to_type[bus])
538 {
539 case MP_BUS_ISA: /* ISA pin */
540 {
541 trigger = default_ISA_trigger(idx);
542 break;
543 }
544 case MP_BUS_EISA: /* EISA pin */
545 {
546 trigger = default_EISA_trigger(idx);
547 break;
548 }
549 case MP_BUS_PCI: /* PCI pin */
550 {
551 trigger = default_PCI_trigger(idx);
552 break;
553 }
554 case MP_BUS_MCA: /* MCA pin */
555 {
556 trigger = default_MCA_trigger(idx);
557 break;
558 }
559 case MP_BUS_NEC98: /* NEC 98 pin */
560 {
561 trigger = default_NEC98_trigger(idx);
562 break;
563 }
564 default:
565 {
566 printk(KERN_WARNING "broken BIOS!!\n");
567 trigger = 1;
568 break;
569 }
570 }
571 break;
572 }
573 case 1: /* edge */
574 {
575 trigger = 0;
576 break;
577 }
578 case 2: /* reserved */
579 {
580 printk(KERN_WARNING "broken BIOS!!\n");
581 trigger = 1;
582 break;
583 }
584 case 3: /* level */
585 {
586 trigger = 1;
587 break;
588 }
589 default: /* invalid */
590 {
591 printk(KERN_WARNING "broken BIOS!!\n");
592 trigger = 0;
593 break;
594 }
595 }
596 return trigger;
597 }
599 static inline int irq_polarity(int idx)
600 {
601 return MPBIOS_polarity(idx);
602 }
604 static inline int irq_trigger(int idx)
605 {
606 return MPBIOS_trigger(idx);
607 }
609 static int pin_2_irq(int idx, int apic, int pin)
610 {
611 int irq, i;
612 int bus = mp_irqs[idx].mpc_srcbus;
614 /*
615 * Debugging check, we are in big trouble if this message pops up!
616 */
617 if (mp_irqs[idx].mpc_dstirq != pin)
618 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
620 switch (mp_bus_id_to_type[bus])
621 {
622 case MP_BUS_ISA: /* ISA pin */
623 case MP_BUS_EISA:
624 case MP_BUS_MCA:
625 case MP_BUS_NEC98:
626 {
627 irq = mp_irqs[idx].mpc_srcbusirq;
628 break;
629 }
630 case MP_BUS_PCI: /* PCI pin */
631 {
632 /*
633 * PCI IRQs are mapped in order
634 */
635 i = irq = 0;
636 while (i < apic)
637 irq += nr_ioapic_registers[i++];
638 irq += pin;
640 /*
641 * For MPS mode, so far only needed by ES7000 platform
642 */
643 if (ioapic_renumber_irq)
644 irq = ioapic_renumber_irq(apic, irq);
646 break;
647 }
648 default:
649 {
650 printk(KERN_ERR "unknown bus type %d.\n",bus);
651 irq = 0;
652 break;
653 }
654 }
656 return irq;
657 }
659 static inline int IO_APIC_irq_trigger(int irq)
660 {
661 int apic, idx, pin;
663 for (apic = 0; apic < nr_ioapics; apic++) {
664 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
665 idx = find_irq_entry(apic,pin,mp_INT);
666 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
667 return irq_trigger(idx);
668 }
669 }
670 /*
671 * nonexistent IRQs are edge default
672 */
673 return 0;
674 }
676 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
677 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly;
679 int assign_irq_vector(int irq)
680 {
681 static unsigned current_vector = FIRST_DYNAMIC_VECTOR, offset = 0;
682 unsigned vector;
684 BUG_ON(irq >= NR_IRQ_VECTORS);
685 spin_lock(&vector_lock);
687 if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0) {
688 spin_unlock(&vector_lock);
689 return IO_APIC_VECTOR(irq);
690 }
692 next:
693 current_vector += 8;
695 /* Skip the hypercall vector. */
696 if (current_vector == HYPERCALL_VECTOR)
697 goto next;
699 /* Skip the Linux/BSD fast-trap vector. */
700 if (current_vector == 0x80)
701 goto next;
703 if (current_vector > LAST_DYNAMIC_VECTOR) {
704 offset++;
705 if (!(offset%8)) {
706 spin_unlock(&vector_lock);
707 return -ENOSPC;
708 }
709 current_vector = FIRST_DYNAMIC_VECTOR + offset;
710 }
712 vector = current_vector;
713 vector_irq[vector] = irq;
714 if (irq != AUTO_ASSIGN)
715 IO_APIC_VECTOR(irq) = vector;
717 spin_unlock(&vector_lock);
719 return vector;
720 }
722 static struct hw_interrupt_type ioapic_level_type;
723 static struct hw_interrupt_type ioapic_edge_type;
724 struct hw_interrupt_type pci_msi_type;
726 #define IOAPIC_AUTO -1
727 #define IOAPIC_EDGE 0
728 #define IOAPIC_LEVEL 1
730 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
731 {
732 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
733 trigger == IOAPIC_LEVEL)
734 irq_desc[vector].handler = &ioapic_level_type;
735 else
736 irq_desc[vector].handler = &ioapic_edge_type;
737 }
739 static void __init setup_IO_APIC_irqs(void)
740 {
741 struct IO_APIC_route_entry entry;
742 int apic, pin, idx, irq, first_notcon = 1, vector;
743 unsigned long flags;
745 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
747 for (apic = 0; apic < nr_ioapics; apic++) {
748 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
750 /*
751 * add it to the IO-APIC irq-routing table:
752 */
753 memset(&entry,0,sizeof(entry));
755 entry.delivery_mode = INT_DELIVERY_MODE;
756 entry.dest_mode = INT_DEST_MODE;
757 entry.mask = 0; /* enable IRQ */
758 entry.dest.logical.logical_dest =
759 cpu_mask_to_apicid(TARGET_CPUS);
761 idx = find_irq_entry(apic,pin,mp_INT);
762 if (idx == -1) {
763 if (first_notcon) {
764 apic_printk(APIC_VERBOSE, KERN_DEBUG
765 " IO-APIC (apicid-pin) %d-%d",
766 mp_ioapics[apic].mpc_apicid,
767 pin);
768 first_notcon = 0;
769 } else
770 apic_printk(APIC_VERBOSE, ", %d-%d",
771 mp_ioapics[apic].mpc_apicid, pin);
772 continue;
773 }
775 entry.trigger = irq_trigger(idx);
776 entry.polarity = irq_polarity(idx);
778 if (irq_trigger(idx)) {
779 entry.trigger = 1;
780 entry.mask = 1;
781 }
783 irq = pin_2_irq(idx, apic, pin);
784 /*
785 * skip adding the timer int on secondary nodes, which causes
786 * a small but painful rift in the time-space continuum
787 */
788 if (multi_timer_check(apic, irq))
789 continue;
790 else
791 add_pin_to_irq(irq, apic, pin);
793 if (!apic && !IO_APIC_IRQ(irq))
794 continue;
796 if (IO_APIC_IRQ(irq)) {
797 vector = assign_irq_vector(irq);
798 entry.vector = vector;
799 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
801 if (!apic && (irq < 16))
802 disable_8259A_irq(irq);
803 }
804 spin_lock_irqsave(&ioapic_lock, flags);
805 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
806 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
807 set_native_irq_info(entry.vector, TARGET_CPUS);
808 spin_unlock_irqrestore(&ioapic_lock, flags);
809 }
810 }
812 if (!first_notcon)
813 apic_printk(APIC_VERBOSE, " not connected.\n");
814 }
816 /*
817 * Set up the 8259A-master output pin:
818 */
819 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
820 {
821 struct IO_APIC_route_entry entry;
822 unsigned long flags;
824 memset(&entry,0,sizeof(entry));
826 disable_8259A_irq(0);
828 /* mask LVT0 */
829 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
831 /*
832 * We use logical delivery to get the timer IRQ
833 * to the first CPU.
834 */
835 entry.dest_mode = INT_DEST_MODE;
836 entry.mask = 0; /* unmask IRQ now */
837 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
838 entry.delivery_mode = INT_DELIVERY_MODE;
839 entry.polarity = 0;
840 entry.trigger = 0;
841 entry.vector = vector;
843 /*
844 * The timer IRQ doesn't have to know that behind the
845 * scene we have a 8259A-master in AEOI mode ...
846 */
847 irq_desc[IO_APIC_VECTOR(0)].handler = &ioapic_edge_type;
849 /*
850 * Add it to the IO-APIC irq-routing table:
851 */
852 spin_lock_irqsave(&ioapic_lock, flags);
853 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
854 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
855 spin_unlock_irqrestore(&ioapic_lock, flags);
857 enable_8259A_irq(0);
858 }
860 static inline void UNEXPECTED_IO_APIC(void)
861 {
862 }
864 void /*__init*/ __print_IO_APIC(void)
865 {
866 int apic, i;
867 union IO_APIC_reg_00 reg_00;
868 union IO_APIC_reg_01 reg_01;
869 union IO_APIC_reg_02 reg_02;
870 union IO_APIC_reg_03 reg_03;
871 unsigned long flags;
873 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
874 for (i = 0; i < nr_ioapics; i++)
875 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
876 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
878 /*
879 * We are a bit conservative about what we expect. We have to
880 * know about every hardware change ASAP.
881 */
882 printk(KERN_INFO "testing the IO APIC.......................\n");
884 for (apic = 0; apic < nr_ioapics; apic++) {
886 spin_lock_irqsave(&ioapic_lock, flags);
887 reg_00.raw = io_apic_read(apic, 0);
888 reg_01.raw = io_apic_read(apic, 1);
889 if (reg_01.bits.version >= 0x10)
890 reg_02.raw = io_apic_read(apic, 2);
891 if (reg_01.bits.version >= 0x20)
892 reg_03.raw = io_apic_read(apic, 3);
893 spin_unlock_irqrestore(&ioapic_lock, flags);
895 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
896 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
897 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
898 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
899 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
900 if (reg_00.bits.ID >= get_physical_broadcast())
901 UNEXPECTED_IO_APIC();
902 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
903 UNEXPECTED_IO_APIC();
905 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
906 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
907 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
908 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
909 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
910 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
911 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
912 (reg_01.bits.entries != 0x2E) &&
913 (reg_01.bits.entries != 0x3F)
914 )
915 UNEXPECTED_IO_APIC();
917 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
918 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
919 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
920 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
921 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
922 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
923 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
924 )
925 UNEXPECTED_IO_APIC();
926 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
927 UNEXPECTED_IO_APIC();
929 /*
930 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
931 * but the value of reg_02 is read as the previous read register
932 * value, so ignore it if reg_02 == reg_01.
933 */
934 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
935 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
936 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
937 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
938 UNEXPECTED_IO_APIC();
939 }
941 /*
942 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
943 * or reg_03, but the value of reg_0[23] is read as the previous read
944 * register value, so ignore it if reg_03 == reg_0[12].
945 */
946 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
947 reg_03.raw != reg_01.raw) {
948 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
949 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
950 if (reg_03.bits.__reserved_1)
951 UNEXPECTED_IO_APIC();
952 }
954 printk(KERN_DEBUG ".... IRQ redirection table:\n");
956 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
957 " Stat Dest Deli Vect: \n");
959 for (i = 0; i <= reg_01.bits.entries; i++) {
960 struct IO_APIC_route_entry entry;
962 spin_lock_irqsave(&ioapic_lock, flags);
963 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
964 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
965 spin_unlock_irqrestore(&ioapic_lock, flags);
967 printk(KERN_DEBUG " %02x %03X %02X ",
968 i,
969 entry.dest.logical.logical_dest,
970 entry.dest.physical.physical_dest
971 );
973 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
974 entry.mask,
975 entry.trigger,
976 entry.irr,
977 entry.polarity,
978 entry.delivery_status,
979 entry.dest_mode,
980 entry.delivery_mode,
981 entry.vector
982 );
983 }
984 }
985 printk(KERN_INFO "Using vector-based indexing\n");
986 printk(KERN_DEBUG "IRQ to pin mappings:\n");
987 for (i = 0; i < NR_IRQS; i++) {
988 struct irq_pin_list *entry = irq_2_pin + i;
989 if (entry->pin < 0)
990 continue;
991 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
992 for (;;) {
993 printk("-> %d:%d", entry->apic, entry->pin);
994 if (!entry->next)
995 break;
996 entry = irq_2_pin + entry->next;
997 }
998 printk("\n");
999 }
1001 printk(KERN_INFO ".................................... done.\n");
1003 return;
1006 void print_IO_APIC(void)
1008 if (apic_verbosity != APIC_QUIET)
1009 __print_IO_APIC();
1012 void print_IO_APIC_keyhandler(unsigned char key)
1014 __print_IO_APIC();
1017 static void __init enable_IO_APIC(void)
1019 union IO_APIC_reg_01 reg_01;
1020 int i8259_apic, i8259_pin;
1021 int i, apic;
1022 unsigned long flags;
1024 for (i = 0; i < PIN_MAP_SIZE; i++) {
1025 irq_2_pin[i].pin = -1;
1026 irq_2_pin[i].next = 0;
1029 /* Initialise dynamic irq_2_pin free list. */
1030 for (i = NR_IRQS; i < PIN_MAP_SIZE; i++)
1031 irq_2_pin[i].next = i + 1;
1033 /*
1034 * The number of IO-APIC IRQ registers (== #pins):
1035 */
1036 for (apic = 0; apic < nr_ioapics; apic++) {
1037 spin_lock_irqsave(&ioapic_lock, flags);
1038 reg_01.raw = io_apic_read(apic, 1);
1039 spin_unlock_irqrestore(&ioapic_lock, flags);
1040 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1042 for(apic = 0; apic < nr_ioapics; apic++) {
1043 int pin;
1044 /* See if any of the pins is in ExtINT mode */
1045 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1046 struct IO_APIC_route_entry entry;
1047 spin_lock_irqsave(&ioapic_lock, flags);
1048 *(((int *)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1049 *(((int *)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1050 spin_unlock_irqrestore(&ioapic_lock, flags);
1053 /* If the interrupt line is enabled and in ExtInt mode
1054 * I have found the pin where the i8259 is connected.
1055 */
1056 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1057 ioapic_i8259.apic = apic;
1058 ioapic_i8259.pin = pin;
1059 goto found_i8259;
1063 found_i8259:
1064 /* Look to see what if the MP table has reported the ExtINT */
1065 /* If we could not find the appropriate pin by looking at the ioapic
1066 * the i8259 probably is not connected the ioapic but give the
1067 * mptable a chance anyway.
1068 */
1069 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1070 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1071 /* Trust the MP table if nothing is setup in the hardware */
1072 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1073 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1074 ioapic_i8259.pin = i8259_pin;
1075 ioapic_i8259.apic = i8259_apic;
1077 /* Complain if the MP table and the hardware disagree */
1078 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1079 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1081 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1084 /*
1085 * Do not trust the IO-APIC being empty at bootup
1086 */
1087 clear_IO_APIC();
1090 /*
1091 * Not an __init, needed by the reboot code
1092 */
1093 void disable_IO_APIC(void)
1095 /*
1096 * Clear the IO-APIC before rebooting:
1097 */
1098 clear_IO_APIC();
1100 /*
1101 * If the i8259 is routed through an IOAPIC
1102 * Put that IOAPIC in virtual wire mode
1103 * so legacy interrupts can be delivered.
1104 */
1105 if (ioapic_i8259.pin != -1) {
1106 struct IO_APIC_route_entry entry;
1107 unsigned long flags;
1109 memset(&entry, 0, sizeof(entry));
1110 entry.mask = 0; /* Enabled */
1111 entry.trigger = 0; /* Edge */
1112 entry.irr = 0;
1113 entry.polarity = 0; /* High */
1114 entry.delivery_status = 0;
1115 entry.dest_mode = 0; /* Physical */
1116 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1117 entry.vector = 0;
1118 entry.dest.physical.physical_dest =
1119 get_apic_id();
1121 /*
1122 * Add it to the IO-APIC irq-routing table:
1123 */
1124 spin_lock_irqsave(&ioapic_lock, flags);
1125 io_apic_write(ioapic_i8259.apic, 0x11+2*ioapic_i8259.pin,
1126 *(((int *)&entry)+1));
1127 io_apic_write(ioapic_i8259.apic, 0x10+2*ioapic_i8259.pin,
1128 *(((int *)&entry)+0));
1129 spin_unlock_irqrestore(&ioapic_lock, flags);
1131 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1134 /*
1135 * function to set the IO-APIC physical IDs based on the
1136 * values stored in the MPC table.
1138 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1139 */
1141 #ifndef CONFIG_X86_NUMAQ
1142 static void __init setup_ioapic_ids_from_mpc(void)
1144 union IO_APIC_reg_00 reg_00;
1145 physid_mask_t phys_id_present_map;
1146 int apic;
1147 int i;
1148 unsigned char old_id;
1149 unsigned long flags;
1151 /*
1152 * Don't check I/O APIC IDs for xAPIC systems. They have
1153 * no meaning without the serial APIC bus.
1154 */
1155 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1156 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1157 return;
1159 /*
1160 * This is broken; anything with a real cpu count has to
1161 * circumvent this idiocy regardless.
1162 */
1163 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1165 /*
1166 * Set the IOAPIC ID to the value stored in the MPC table.
1167 */
1168 for (apic = 0; apic < nr_ioapics; apic++) {
1170 /* Read the register 0 value */
1171 spin_lock_irqsave(&ioapic_lock, flags);
1172 reg_00.raw = io_apic_read(apic, 0);
1173 spin_unlock_irqrestore(&ioapic_lock, flags);
1175 old_id = mp_ioapics[apic].mpc_apicid;
1177 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1178 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1179 apic, mp_ioapics[apic].mpc_apicid);
1180 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1181 reg_00.bits.ID);
1182 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1185 /*
1186 * Sanity check, is the ID really free? Every APIC in a
1187 * system must have a unique ID or we get lots of nice
1188 * 'stuck on smp_invalidate_needed IPI wait' messages.
1189 */
1190 if (check_apicid_used(phys_id_present_map,
1191 mp_ioapics[apic].mpc_apicid)) {
1192 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1193 apic, mp_ioapics[apic].mpc_apicid);
1194 for (i = 0; i < get_physical_broadcast(); i++)
1195 if (!physid_isset(i, phys_id_present_map))
1196 break;
1197 if (i >= get_physical_broadcast())
1198 panic("Max APIC ID exceeded!\n");
1199 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1200 i);
1201 physid_set(i, phys_id_present_map);
1202 mp_ioapics[apic].mpc_apicid = i;
1203 } else {
1204 physid_mask_t tmp;
1205 tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1206 apic_printk(APIC_VERBOSE, "Setting %d in the "
1207 "phys_id_present_map\n",
1208 mp_ioapics[apic].mpc_apicid);
1209 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1213 /*
1214 * We need to adjust the IRQ routing table
1215 * if the ID changed.
1216 */
1217 if (old_id != mp_ioapics[apic].mpc_apicid)
1218 for (i = 0; i < mp_irq_entries; i++)
1219 if (mp_irqs[i].mpc_dstapic == old_id)
1220 mp_irqs[i].mpc_dstapic
1221 = mp_ioapics[apic].mpc_apicid;
1223 /*
1224 * Read the right value from the MPC table and
1225 * write it into the ID register.
1226 */
1227 apic_printk(APIC_VERBOSE, KERN_INFO
1228 "...changing IO-APIC physical APIC ID to %d ...",
1229 mp_ioapics[apic].mpc_apicid);
1231 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1232 spin_lock_irqsave(&ioapic_lock, flags);
1233 io_apic_write(apic, 0, reg_00.raw);
1234 spin_unlock_irqrestore(&ioapic_lock, flags);
1236 /*
1237 * Sanity check
1238 */
1239 spin_lock_irqsave(&ioapic_lock, flags);
1240 reg_00.raw = io_apic_read(apic, 0);
1241 spin_unlock_irqrestore(&ioapic_lock, flags);
1242 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1243 printk("could not set ID!\n");
1244 else
1245 apic_printk(APIC_VERBOSE, " ok.\n");
1248 #else
1249 static void __init setup_ioapic_ids_from_mpc(void) { }
1250 #endif
1252 /*
1253 * There is a nasty bug in some older SMP boards, their mptable lies
1254 * about the timer IRQ. We do the following to work around the situation:
1256 * - timer IRQ defaults to IO-APIC IRQ
1257 * - if this function detects that timer IRQs are defunct, then we fall
1258 * back to ISA timer IRQs
1259 */
1260 static int __init timer_irq_works(void)
1262 extern unsigned long pit0_ticks;
1263 unsigned long t1;
1265 t1 = pit0_ticks;
1266 mb();
1268 local_irq_enable();
1269 /* Let ten ticks pass... */
1270 mdelay((10 * 1000) / HZ);
1272 /*
1273 * Expect a few ticks at least, to be sure some possible
1274 * glue logic does not lock up after one or two first
1275 * ticks in a non-ExtINT mode. Also the local APIC
1276 * might have cached one ExtINT interrupt. Finally, at
1277 * least one tick may be lost due to delays.
1278 */
1279 mb();
1280 if (pit0_ticks - t1 > 4)
1281 return 1;
1283 return 0;
1286 /*
1287 * In the SMP+IOAPIC case it might happen that there are an unspecified
1288 * number of pending IRQ events unhandled. These cases are very rare,
1289 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1290 * better to do it this way as thus we do not have to be aware of
1291 * 'pending' interrupts in the IRQ path, except at this point.
1292 */
1293 /*
1294 * Edge triggered needs to resend any interrupt
1295 * that was delayed but this is now handled in the device
1296 * independent code.
1297 */
1299 /*
1300 * Starting up a edge-triggered IO-APIC interrupt is
1301 * nasty - we need to make sure that we get the edge.
1302 * If it is already asserted for some reason, we need
1303 * return 1 to indicate that is was pending.
1305 * This is not complete - we should be able to fake
1306 * an edge even if it isn't on the 8259A...
1307 */
1308 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1310 int was_pending = 0;
1311 unsigned long flags;
1313 spin_lock_irqsave(&ioapic_lock, flags);
1314 if (irq < 16) {
1315 disable_8259A_irq(irq);
1316 if (i8259A_irq_pending(irq))
1317 was_pending = 1;
1319 __unmask_IO_APIC_irq(irq);
1320 spin_unlock_irqrestore(&ioapic_lock, flags);
1322 return was_pending;
1325 /*
1326 * Once we have recorded IRQ_PENDING already, we can mask the
1327 * interrupt for real. This prevents IRQ storms from unhandled
1328 * devices.
1329 */
1330 static void ack_edge_ioapic_irq(unsigned int irq)
1332 if ((irq_desc[IO_APIC_VECTOR(irq)].status & (IRQ_PENDING | IRQ_DISABLED))
1333 == (IRQ_PENDING | IRQ_DISABLED))
1334 mask_IO_APIC_irq(irq);
1335 ack_APIC_irq();
1338 /*
1339 * Level triggered interrupts can just be masked,
1340 * and shutting down and starting up the interrupt
1341 * is the same as enabling and disabling them -- except
1342 * with a startup need to return a "was pending" value.
1344 * Level triggered interrupts are special because we
1345 * do not touch any IO-APIC register while handling
1346 * them. We ack the APIC in the end-IRQ handler, not
1347 * in the start-IRQ-handler. Protection against reentrance
1348 * from the same interrupt is still provided, both by the
1349 * generic IRQ layer and by the fact that an unacked local
1350 * APIC does not accept IRQs.
1351 */
1352 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1354 unmask_IO_APIC_irq(irq);
1356 return 0; /* don't check for pending */
1359 int ioapic_ack_new = 1;
1360 static void setup_ioapic_ack(char *s)
1362 if ( !strcmp(s, "old") )
1363 ioapic_ack_new = 0;
1364 else if ( !strcmp(s, "new") )
1365 ioapic_ack_new = 1;
1366 else
1367 printk("Unknown ioapic_ack value specified: '%s'\n", s);
1369 custom_param("ioapic_ack", setup_ioapic_ack);
1371 static void mask_and_ack_level_ioapic_irq (unsigned int irq)
1373 unsigned long v;
1374 int i;
1376 if ( ioapic_ack_new )
1377 return;
1379 mask_IO_APIC_irq(irq);
1381 /*
1382 * It appears there is an erratum which affects at least version 0x11
1383 * of I/O APIC (that's the 82093AA and cores integrated into various
1384 * chipsets). Under certain conditions a level-triggered interrupt is
1385 * erroneously delivered as edge-triggered one but the respective IRR
1386 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1387 * message but it will never arrive and further interrupts are blocked
1388 * from the source. The exact reason is so far unknown, but the
1389 * phenomenon was observed when two consecutive interrupt requests
1390 * from a given source get delivered to the same CPU and the source is
1391 * temporarily disabled in between.
1393 * A workaround is to simulate an EOI message manually. We achieve it
1394 * by setting the trigger mode to edge and then to level when the edge
1395 * trigger mode gets detected in the TMR of a local APIC for a
1396 * level-triggered interrupt. We mask the source for the time of the
1397 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1398 * The idea is from Manfred Spraul. --macro
1399 */
1400 i = IO_APIC_VECTOR(irq);
1402 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1404 ack_APIC_irq();
1406 if (!(v & (1 << (i & 0x1f)))) {
1407 atomic_inc(&irq_mis_count);
1408 spin_lock(&ioapic_lock);
1409 __edge_IO_APIC_irq(irq);
1410 __level_IO_APIC_irq(irq);
1411 spin_unlock(&ioapic_lock);
1415 static void end_level_ioapic_irq (unsigned int irq)
1417 unsigned long v;
1418 int i;
1420 if ( !ioapic_ack_new )
1422 if ( !(irq_desc[IO_APIC_VECTOR(irq)].status & IRQ_DISABLED) )
1423 unmask_IO_APIC_irq(irq);
1424 return;
1427 /*
1428 * It appears there is an erratum which affects at least version 0x11
1429 * of I/O APIC (that's the 82093AA and cores integrated into various
1430 * chipsets). Under certain conditions a level-triggered interrupt is
1431 * erroneously delivered as edge-triggered one but the respective IRR
1432 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1433 * message but it will never arrive and further interrupts are blocked
1434 * from the source. The exact reason is so far unknown, but the
1435 * phenomenon was observed when two consecutive interrupt requests
1436 * from a given source get delivered to the same CPU and the source is
1437 * temporarily disabled in between.
1439 * A workaround is to simulate an EOI message manually. We achieve it
1440 * by setting the trigger mode to edge and then to level when the edge
1441 * trigger mode gets detected in the TMR of a local APIC for a
1442 * level-triggered interrupt. We mask the source for the time of the
1443 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1444 * The idea is from Manfred Spraul. --macro
1445 */
1446 i = IO_APIC_VECTOR(irq);
1448 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1450 ack_APIC_irq();
1452 if (!(v & (1 << (i & 0x1f)))) {
1453 atomic_inc(&irq_mis_count);
1454 spin_lock(&ioapic_lock);
1455 __mask_IO_APIC_irq(irq);
1456 __edge_IO_APIC_irq(irq);
1457 __level_IO_APIC_irq(irq);
1458 if ( !(irq_desc[IO_APIC_VECTOR(irq)].status & IRQ_DISABLED) )
1459 __unmask_IO_APIC_irq(irq);
1460 spin_unlock(&ioapic_lock);
1464 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1466 int irq = vector_to_irq(vector);
1467 return startup_edge_ioapic_irq(irq);
1470 static void ack_edge_ioapic_vector(unsigned int vector)
1472 int irq = vector_to_irq(vector);
1473 ack_edge_ioapic_irq(irq);
1476 static unsigned int startup_level_ioapic_vector(unsigned int vector)
1478 int irq = vector_to_irq(vector);
1479 return startup_level_ioapic_irq (irq);
1482 static void mask_and_ack_level_ioapic_vector(unsigned int vector)
1484 int irq = vector_to_irq(vector);
1485 mask_and_ack_level_ioapic_irq(irq);
1488 static void end_level_ioapic_vector(unsigned int vector)
1490 int irq = vector_to_irq(vector);
1491 end_level_ioapic_irq(irq);
1494 static void mask_IO_APIC_vector(unsigned int vector)
1496 int irq = vector_to_irq(vector);
1497 mask_IO_APIC_irq(irq);
1500 static void unmask_IO_APIC_vector(unsigned int vector)
1502 int irq = vector_to_irq(vector);
1503 unmask_IO_APIC_irq(irq);
1506 static void set_ioapic_affinity_vector(
1507 unsigned int vector, cpumask_t cpu_mask)
1509 int irq = vector_to_irq(vector);
1511 set_native_irq_info(vector, cpu_mask);
1512 set_ioapic_affinity_irq(irq, cpu_mask);
1515 static void disable_edge_ioapic_vector(unsigned int vector)
1519 static void end_edge_ioapic_vector(unsigned int vector)
1523 /*
1524 * Level and edge triggered IO-APIC interrupts need different handling,
1525 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1526 * handled with the level-triggered descriptor, but that one has slightly
1527 * more overhead. Level-triggered interrupts cannot be handled with the
1528 * edge-triggered handler, without risking IRQ storms and other ugly
1529 * races.
1530 */
1531 static struct hw_interrupt_type ioapic_edge_type = {
1532 .typename = "IO-APIC-edge",
1533 .startup = startup_edge_ioapic_vector,
1534 .shutdown = disable_edge_ioapic_vector,
1535 .enable = unmask_IO_APIC_vector,
1536 .disable = disable_edge_ioapic_vector,
1537 .ack = ack_edge_ioapic_vector,
1538 .end = end_edge_ioapic_vector,
1539 .set_affinity = set_ioapic_affinity_vector,
1540 };
1542 static struct hw_interrupt_type ioapic_level_type = {
1543 .typename = "IO-APIC-level",
1544 .startup = startup_level_ioapic_vector,
1545 .shutdown = mask_IO_APIC_vector,
1546 .enable = unmask_IO_APIC_vector,
1547 .disable = mask_IO_APIC_vector,
1548 .ack = mask_and_ack_level_ioapic_vector,
1549 .end = end_level_ioapic_vector,
1550 .set_affinity = set_ioapic_affinity_vector,
1551 };
1553 static void mask_msi_vector(unsigned int vector)
1555 mask_msi_irq(vector);
1558 static void unmask_msi_vector(unsigned int vector)
1560 unmask_msi_irq(vector);
1563 static unsigned int startup_msi_vector(unsigned int vector)
1565 dprintk(XENLOG_INFO, "startup msi vector %x\n", vector);
1566 unmask_msi_irq(vector);
1567 return 0;
1570 static void ack_msi_vector(unsigned int vector)
1572 ack_APIC_irq();
1575 static void end_msi_vector(unsigned int vector)
1579 static void shutdown_msi_vector(unsigned int vector)
1581 dprintk(XENLOG_INFO, "shutdown msi vector %x\n", vector);
1582 mask_msi_irq(vector);
1585 static void set_msi_affinity_vector(unsigned int vector, cpumask_t cpu_mask)
1587 set_native_irq_info(vector, cpu_mask);
1588 set_msi_irq_affinity(vector, cpu_mask);
1591 /*
1592 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
1593 * which implement the MSI or MSI-X Capability Structure.
1594 */
1595 struct hw_interrupt_type pci_msi_type = {
1596 .typename = "PCI-MSI",
1597 .startup = startup_msi_vector,
1598 .shutdown = shutdown_msi_vector,
1599 .enable = unmask_msi_vector,
1600 .disable = mask_msi_vector,
1601 .ack = ack_msi_vector,
1602 .end = end_msi_vector,
1603 .set_affinity = set_msi_affinity_vector,
1604 };
1606 static inline void init_IO_APIC_traps(void)
1608 int irq;
1609 /* Xen: This is way simpler than the Linux implementation. */
1610 for (irq = 0; irq < 16 ; irq++)
1611 if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq))
1612 make_8259A_irq(irq);
1615 static void enable_lapic_vector(unsigned int vector)
1617 unsigned long v;
1619 v = apic_read(APIC_LVT0);
1620 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1623 static void disable_lapic_vector(unsigned int vector)
1625 unsigned long v;
1627 v = apic_read(APIC_LVT0);
1628 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1631 static void ack_lapic_vector(unsigned int vector)
1633 ack_APIC_irq();
1636 static void end_lapic_vector(unsigned int vector) { /* nothing */ }
1638 static struct hw_interrupt_type lapic_irq_type = {
1639 .typename = "local-APIC-edge",
1640 .startup = NULL, /* startup_irq() not used for IRQ0 */
1641 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1642 .enable = enable_lapic_vector,
1643 .disable = disable_lapic_vector,
1644 .ack = ack_lapic_vector,
1645 .end = end_lapic_vector
1646 };
1648 /*
1649 * This looks a bit hackish but it's about the only one way of sending
1650 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1651 * not support the ExtINT mode, unfortunately. We need to send these
1652 * cycles as some i82489DX-based boards have glue logic that keeps the
1653 * 8259A interrupt line asserted until INTA. --macro
1654 */
1655 static inline void unlock_ExtINT_logic(void)
1657 int apic, pin, i;
1658 struct IO_APIC_route_entry entry0, entry1;
1659 unsigned char save_control, save_freq_select;
1660 unsigned long flags;
1662 pin = find_isa_irq_pin(8, mp_INT);
1663 apic = find_isa_irq_apic(8, mp_INT);
1664 if (pin == -1)
1665 return;
1667 spin_lock_irqsave(&ioapic_lock, flags);
1668 *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1669 *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1670 spin_unlock_irqrestore(&ioapic_lock, flags);
1671 clear_IO_APIC_pin(apic, pin);
1673 memset(&entry1, 0, sizeof(entry1));
1675 entry1.dest_mode = 0; /* physical delivery */
1676 entry1.mask = 0; /* unmask IRQ now */
1677 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1678 entry1.delivery_mode = dest_ExtINT;
1679 entry1.polarity = entry0.polarity;
1680 entry1.trigger = 0;
1681 entry1.vector = 0;
1683 spin_lock_irqsave(&ioapic_lock, flags);
1684 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1685 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1686 spin_unlock_irqrestore(&ioapic_lock, flags);
1688 save_control = CMOS_READ(RTC_CONTROL);
1689 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1690 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1691 RTC_FREQ_SELECT);
1692 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1694 i = 100;
1695 while (i-- > 0) {
1696 mdelay(10);
1697 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1698 i -= 10;
1701 CMOS_WRITE(save_control, RTC_CONTROL);
1702 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1703 clear_IO_APIC_pin(apic, pin);
1705 spin_lock_irqsave(&ioapic_lock, flags);
1706 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1707 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1708 spin_unlock_irqrestore(&ioapic_lock, flags);
1711 int timer_uses_ioapic_pin_0;
1713 /*
1714 * This code may look a bit paranoid, but it's supposed to cooperate with
1715 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1716 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1717 * fanatically on his truly buggy board.
1718 */
1719 static inline void check_timer(void)
1721 int apic1, pin1, apic2, pin2;
1722 int vector;
1724 /*
1725 * get/set the timer IRQ vector:
1726 */
1727 disable_8259A_irq(0);
1728 vector = assign_irq_vector(0);
1730 irq_desc[IO_APIC_VECTOR(0)].action = irq_desc[LEGACY_VECTOR(0)].action;
1731 irq_desc[IO_APIC_VECTOR(0)].depth = 0;
1732 irq_desc[IO_APIC_VECTOR(0)].status &= ~IRQ_DISABLED;
1734 /*
1735 * Subtle, code in do_timer_interrupt() expects an AEOI
1736 * mode for the 8259A whenever interrupts are routed
1737 * through I/O APICs. Also IRQ0 has to be enabled in
1738 * the 8259A which implies the virtual wire has to be
1739 * disabled in the local APIC.
1740 */
1741 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1742 init_8259A(1);
1743 /* XEN: Ripped out the legacy missed-tick logic, so below is not needed. */
1744 /*timer_ack = 1;*/
1745 /*enable_8259A_irq(0);*/
1747 pin1 = find_isa_irq_pin(0, mp_INT);
1748 apic1 = find_isa_irq_apic(0, mp_INT);
1749 pin2 = ioapic_i8259.pin;
1750 apic2 = ioapic_i8259.apic;
1752 if (pin1 == 0)
1753 timer_uses_ioapic_pin_0 = 1;
1755 printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1756 vector, apic1, pin1, apic2, pin2);
1758 if (pin1 != -1) {
1759 /*
1760 * Ok, does IRQ0 through the IOAPIC work?
1761 */
1762 unmask_IO_APIC_irq(0);
1763 if (timer_irq_works()) {
1764 if (disable_timer_pin_1 > 0)
1765 clear_IO_APIC_pin(apic1, pin1);
1766 return;
1768 clear_IO_APIC_pin(apic1, pin1);
1769 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
1770 "IO-APIC\n");
1773 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1774 if (pin2 != -1) {
1775 printk("\n..... (found pin %d) ...", pin2);
1776 /*
1777 * legacy devices should be connected to IO APIC #0
1778 */
1779 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1780 if (timer_irq_works()) {
1781 printk("works.\n");
1782 if (pin1 != -1)
1783 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1784 else
1785 add_pin_to_irq(0, apic2, pin2);
1786 return;
1788 /*
1789 * Cleanup, just in case ...
1790 */
1791 clear_IO_APIC_pin(apic2, pin2);
1793 printk(" failed.\n");
1795 if (nmi_watchdog == NMI_IO_APIC) {
1796 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1797 nmi_watchdog = 0;
1800 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1802 disable_8259A_irq(0);
1803 irq_desc[vector].handler = &lapic_irq_type;
1804 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1805 enable_8259A_irq(0);
1807 if (timer_irq_works()) {
1808 printk(" works.\n");
1809 return;
1811 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1812 printk(" failed.\n");
1814 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1816 /*timer_ack = 0;*/
1817 init_8259A(0);
1818 make_8259A_irq(0);
1819 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1821 unlock_ExtINT_logic();
1823 if (timer_irq_works()) {
1824 printk(" works.\n");
1825 return;
1827 printk(" failed :(.\n");
1828 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
1829 "report. Then try booting with the 'noapic' option");
1832 /*
1834 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1835 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1836 * Linux doesn't really care, as it's not actually used
1837 * for any interrupt handling anyway.
1838 */
1839 #define PIC_IRQS (1 << PIC_CASCADE_IR)
1841 void __init setup_IO_APIC(void)
1843 enable_IO_APIC();
1845 if (acpi_ioapic)
1846 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1847 else
1848 io_apic_irqs = ~PIC_IRQS;
1850 printk("ENABLING IO-APIC IRQs\n");
1851 printk(" -> Using %s ACK method\n", ioapic_ack_new ? "new" : "old");
1853 /*
1854 * Set up IO-APIC IRQ routing.
1855 */
1856 if (!acpi_ioapic)
1857 setup_ioapic_ids_from_mpc();
1858 sync_Arb_IDs();
1859 setup_IO_APIC_irqs();
1860 init_IO_APIC_traps();
1861 check_timer();
1862 print_IO_APIC();
1864 register_keyhandler('z', print_IO_APIC_keyhandler, "print ioapic info");
1867 struct IO_APIC_route_entry *ioapic_pm_state=NULL;
1869 void ioapic_pm_state_alloc(void)
1871 int i, nr_entry = 0;
1873 if (ioapic_pm_state != NULL)
1874 return;
1876 for (i = 0; i < nr_ioapics; i++)
1877 nr_entry += nr_ioapic_registers[i];
1879 ioapic_pm_state = _xmalloc(sizeof(struct IO_APIC_route_entry)*nr_entry,
1880 sizeof(struct IO_APIC_route_entry));
1883 int ioapic_suspend(void)
1885 struct IO_APIC_route_entry *entry;
1886 unsigned long flags;
1887 int apic,i;
1889 ioapic_pm_state_alloc();
1891 if (ioapic_pm_state == NULL) {
1892 printk("Cannot suspend ioapic due to lack of memory\n");
1893 return 1;
1896 entry = ioapic_pm_state;
1898 spin_lock_irqsave(&ioapic_lock, flags);
1899 for (apic = 0; apic < nr_ioapics; apic++) {
1900 for (i = 0; i < nr_ioapic_registers[apic]; i ++, entry ++ ) {
1901 *(((int *)entry) + 1) = io_apic_read(apic, 0x11 + 2 * i);
1902 *(((int *)entry) + 0) = io_apic_read(apic, 0x10 + 2 * i);
1905 spin_unlock_irqrestore(&ioapic_lock, flags);
1907 return 0;
1910 int ioapic_resume(void)
1912 struct IO_APIC_route_entry *entry;
1913 unsigned long flags;
1914 union IO_APIC_reg_00 reg_00;
1915 int i,apic;
1917 if (ioapic_pm_state == NULL){
1918 printk("Cannot resume ioapic due to lack of memory\n");
1919 return 1;
1922 entry = ioapic_pm_state;
1924 spin_lock_irqsave(&ioapic_lock, flags);
1925 for (apic = 0; apic < nr_ioapics; apic++){
1926 reg_00.raw = io_apic_read(apic, 0);
1927 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid) {
1928 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1929 io_apic_write(apic, 0, reg_00.raw);
1931 for (i = 0; i < nr_ioapic_registers[apic]; i++, entry++) {
1932 io_apic_write(apic, 0x11+2*i, *(((int *)entry)+1));
1933 io_apic_write(apic, 0x10+2*i, *(((int *)entry)+0));
1936 spin_unlock_irqrestore(&ioapic_lock, flags);
1938 return 0;
1941 /* --------------------------------------------------------------------------
1942 ACPI-based IOAPIC Configuration
1943 -------------------------------------------------------------------------- */
1945 #ifdef CONFIG_ACPI_BOOT
1947 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1949 union IO_APIC_reg_00 reg_00;
1950 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
1951 physid_mask_t tmp;
1952 unsigned long flags;
1953 int i = 0;
1955 /*
1956 * The P4 platform supports up to 256 APIC IDs on two separate APIC
1957 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1958 * supports up to 16 on one shared APIC bus.
1960 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1961 * advantage of new APIC bus architecture.
1962 */
1964 if (physids_empty(apic_id_map))
1965 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
1967 spin_lock_irqsave(&ioapic_lock, flags);
1968 reg_00.raw = io_apic_read(ioapic, 0);
1969 spin_unlock_irqrestore(&ioapic_lock, flags);
1971 if (apic_id >= get_physical_broadcast()) {
1972 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1973 "%d\n", ioapic, apic_id, reg_00.bits.ID);
1974 apic_id = reg_00.bits.ID;
1977 /*
1978 * Every APIC in a system must have a unique ID or we get lots of nice
1979 * 'stuck on smp_invalidate_needed IPI wait' messages.
1980 */
1981 if (check_apicid_used(apic_id_map, apic_id)) {
1983 for (i = 0; i < get_physical_broadcast(); i++) {
1984 if (!check_apicid_used(apic_id_map, i))
1985 break;
1988 if (i == get_physical_broadcast())
1989 panic("Max apic_id exceeded!\n");
1991 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1992 "trying %d\n", ioapic, apic_id, i);
1994 apic_id = i;
1997 tmp = apicid_to_cpu_present(apic_id);
1998 physids_or(apic_id_map, apic_id_map, tmp);
2000 if (reg_00.bits.ID != apic_id) {
2001 reg_00.bits.ID = apic_id;
2003 spin_lock_irqsave(&ioapic_lock, flags);
2004 io_apic_write(ioapic, 0, reg_00.raw);
2005 reg_00.raw = io_apic_read(ioapic, 0);
2006 spin_unlock_irqrestore(&ioapic_lock, flags);
2008 /* Sanity check */
2009 if (reg_00.bits.ID != apic_id) {
2010 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2011 return -1;
2015 apic_printk(APIC_VERBOSE, KERN_INFO
2016 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2018 return apic_id;
2022 int __init io_apic_get_version (int ioapic)
2024 union IO_APIC_reg_01 reg_01;
2025 unsigned long flags;
2027 spin_lock_irqsave(&ioapic_lock, flags);
2028 reg_01.raw = io_apic_read(ioapic, 1);
2029 spin_unlock_irqrestore(&ioapic_lock, flags);
2031 return reg_01.bits.version;
2035 int __init io_apic_get_redir_entries (int ioapic)
2037 union IO_APIC_reg_01 reg_01;
2038 unsigned long flags;
2040 spin_lock_irqsave(&ioapic_lock, flags);
2041 reg_01.raw = io_apic_read(ioapic, 1);
2042 spin_unlock_irqrestore(&ioapic_lock, flags);
2044 return reg_01.bits.entries;
2048 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2050 struct IO_APIC_route_entry entry;
2051 unsigned long flags;
2053 if (!IO_APIC_IRQ(irq)) {
2054 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2055 ioapic);
2056 return -EINVAL;
2059 /*
2060 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2061 * Note that we mask (disable) IRQs now -- these get enabled when the
2062 * corresponding device driver registers for this IRQ.
2063 */
2065 memset(&entry,0,sizeof(entry));
2067 entry.delivery_mode = INT_DELIVERY_MODE;
2068 entry.dest_mode = INT_DEST_MODE;
2069 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2070 entry.trigger = edge_level;
2071 entry.polarity = active_high_low;
2072 entry.mask = 1;
2074 /*
2075 * IRQs < 16 are already in the irq_2_pin[] map
2076 */
2077 if (irq >= 16)
2078 add_pin_to_irq(irq, ioapic, pin);
2080 entry.vector = assign_irq_vector(irq);
2082 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2083 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2084 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2085 edge_level, active_high_low);
2087 ioapic_register_intr(irq, entry.vector, edge_level);
2089 if (!ioapic && (irq < 16))
2090 disable_8259A_irq(irq);
2092 spin_lock_irqsave(&ioapic_lock, flags);
2093 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2094 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2095 set_native_irq_info(entry.vector, TARGET_CPUS);
2096 spin_unlock_irqrestore(&ioapic_lock, flags);
2098 return 0;
2101 #endif /*CONFIG_ACPI_BOOT*/
2103 static int ioapic_physbase_to_id(unsigned long physbase)
2105 int apic;
2106 for ( apic = 0; apic < nr_ioapics; apic++ )
2107 if ( mp_ioapics[apic].mpc_apicaddr == physbase )
2108 return apic;
2109 return -EINVAL;
2112 int ioapic_guest_read(unsigned long physbase, unsigned int reg, u32 *pval)
2114 int apic;
2115 unsigned long flags;
2117 if ( (apic = ioapic_physbase_to_id(physbase)) < 0 )
2118 return apic;
2120 spin_lock_irqsave(&ioapic_lock, flags);
2121 *pval = io_apic_read(apic, reg);
2122 spin_unlock_irqrestore(&ioapic_lock, flags);
2124 return 0;
2127 #define WARN_BOGUS_WRITE(f, a...) \
2128 dprintk(XENLOG_INFO, "\n%s: " \
2129 "apic=%d, pin=%d, old_irq=%d, new_irq=%d\n" \
2130 "%s: old_entry=%08x, new_entry=%08x\n" \
2131 "%s: " f, __FUNCTION__, apic, pin, old_irq, new_irq, \
2132 __FUNCTION__, *(u32 *)&old_rte, *(u32 *)&new_rte, \
2133 __FUNCTION__ , ##a )
2135 int ioapic_guest_write(unsigned long physbase, unsigned int reg, u32 val)
2137 int apic, pin, old_irq = -1, new_irq = -1;
2138 struct IO_APIC_route_entry old_rte = { 0 }, new_rte = { 0 };
2139 unsigned long flags;
2141 if ( (apic = ioapic_physbase_to_id(physbase)) < 0 )
2142 return apic;
2144 /* Only write to the first half of a route entry. */
2145 if ( (reg < 0x10) || (reg & 1) )
2146 return 0;
2148 pin = (reg - 0x10) >> 1;
2150 /* Write first half from guest; second half is target info. */
2151 *(u32 *)&new_rte = val;
2152 new_rte.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2154 /*
2155 * What about weird destination types?
2156 * SMI: Ignore? Ought to be set up by the BIOS.
2157 * NMI: Ignore? Watchdog functionality is Xen's concern.
2158 * INIT: Definitely ignore: probably a guest OS bug.
2159 * ExtINT: Ignore? Linux only asserts this at start of day.
2160 * For now, print a message and return an error. We can fix up on demand.
2161 */
2162 if ( new_rte.delivery_mode > dest_LowestPrio )
2164 printk("ERROR: Attempt to write weird IOAPIC destination mode!\n");
2165 printk(" APIC=%d/%d, lo-reg=%x\n", apic, pin, val);
2166 return -EINVAL;
2169 /*
2170 * The guest does not know physical APIC arrangement (flat vs. cluster).
2171 * Apply genapic conventions for this platform.
2172 */
2173 new_rte.delivery_mode = INT_DELIVERY_MODE;
2174 new_rte.dest_mode = INT_DEST_MODE;
2176 spin_lock_irqsave(&ioapic_lock, flags);
2178 /* Read first (interesting) half of current routing entry. */
2179 *(u32 *)&old_rte = io_apic_read(apic, 0x10 + 2 * pin);
2181 /* No change to the first half of the routing entry? Bail quietly. */
2182 if ( *(u32 *)&old_rte == *(u32 *)&new_rte )
2184 spin_unlock_irqrestore(&ioapic_lock, flags);
2185 return 0;
2188 /* Special delivery modes (SMI,NMI,INIT,ExtInt) should have no vector. */
2189 if ( (old_rte.delivery_mode > dest_LowestPrio) && (old_rte.vector != 0) )
2191 WARN_BOGUS_WRITE("Special delivery mode %d with non-zero vector "
2192 "%02x\n", old_rte.delivery_mode, old_rte.vector);
2193 /* Nobble the vector here as it does not relate to a valid irq. */
2194 old_rte.vector = 0;
2197 if ( old_rte.vector >= FIRST_DYNAMIC_VECTOR )
2198 old_irq = vector_irq[old_rte.vector];
2199 if ( new_rte.vector >= FIRST_DYNAMIC_VECTOR )
2200 new_irq = vector_irq[new_rte.vector];
2202 if ( (old_irq != new_irq) && (old_irq != -1) && IO_APIC_IRQ(old_irq) )
2204 if ( irq_desc[IO_APIC_VECTOR(old_irq)].action )
2206 WARN_BOGUS_WRITE("Attempt to remove IO-APIC pin of in-use IRQ!\n");
2207 spin_unlock_irqrestore(&ioapic_lock, flags);
2208 return 0;
2211 remove_pin_at_irq(old_irq, apic, pin);
2214 if ( (new_irq != -1) && IO_APIC_IRQ(new_irq) )
2216 if ( irq_desc[IO_APIC_VECTOR(new_irq)].action )
2218 WARN_BOGUS_WRITE("Attempt to %s IO-APIC pin for in-use IRQ!\n",
2219 (old_irq != new_irq) ? "add" : "modify");
2220 spin_unlock_irqrestore(&ioapic_lock, flags);
2221 return 0;
2224 /* Set the correct irq-handling type. */
2225 irq_desc[IO_APIC_VECTOR(new_irq)].handler = new_rte.trigger ?
2226 &ioapic_level_type: &ioapic_edge_type;
2228 if ( old_irq != new_irq )
2229 add_pin_to_irq(new_irq, apic, pin);
2231 /* Mask iff level triggered. */
2232 new_rte.mask = new_rte.trigger;
2234 else if ( !new_rte.mask )
2236 /* This pin leads nowhere but the guest has not masked it. */
2237 WARN_BOGUS_WRITE("Installing bogus unmasked IO-APIC entry!\n");
2238 new_rte.mask = 1;
2242 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&new_rte) + 0));
2243 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&new_rte) + 1));
2245 spin_unlock_irqrestore(&ioapic_lock, flags);
2247 return 0;
2250 void dump_ioapic_irq_info(void)
2252 struct irq_pin_list *entry;
2253 struct IO_APIC_route_entry rte;
2254 unsigned int irq, pin, printed = 0;
2255 unsigned long flags;
2257 for ( irq = 0; irq < NR_IRQS; irq++ )
2259 entry = &irq_2_pin[irq];
2260 if ( entry->pin == -1 )
2261 continue;
2263 if ( !printed++ )
2264 printk("IO-APIC interrupt information:\n");
2266 printk(" IRQ%3d Vec%3d:\n", irq, irq_to_vector(irq));
2268 for ( ; ; )
2270 pin = entry->pin;
2272 printk(" Apic 0x%02x, Pin %2d: ", entry->apic, pin);
2274 spin_lock_irqsave(&ioapic_lock, flags);
2275 *(((int *)&rte) + 0) = io_apic_read(entry->apic, 0x10 + 2 * pin);
2276 *(((int *)&rte) + 1) = io_apic_read(entry->apic, 0x11 + 2 * pin);
2277 spin_unlock_irqrestore(&ioapic_lock, flags);
2279 printk("vector=%u, delivery_mode=%u, dest_mode=%s, "
2280 "delivery_status=%d, polarity=%d, irr=%d, "
2281 "trigger=%s, mask=%d\n",
2282 rte.vector, rte.delivery_mode,
2283 rte.dest_mode ? "logical" : "physical",
2284 rte.delivery_status, rte.polarity, rte.irr,
2285 rte.trigger ? "level" : "edge", rte.mask);
2287 if ( entry->next == 0 )
2288 break;
2289 entry = &irq_2_pin[entry->next];