ia64/xen-unstable

view xen/arch/x86/hvm/mtrr.c @ 16876:6269a3ce7b83

x86, hvm: MTRR can't cover all the memery ranges
MTRR can't cover all the memery ranges, due to guest E820 is changed
by CS:16728 with current method.
Signed-off-by: Disheng Su <disheng.su@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jan 24 14:40:35 2008 +0000 (2008-01-24)
parents 5a451d2c36bc
children 24e3a0ce63f8
line source
1 /*
2 * mtrr.c: MTRR/PAT virtualization
3 *
4 * Copyright (c) 2007, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 */
20 #include <public/hvm/e820.h>
21 #include <xen/types.h>
22 #include <asm/e820.h>
23 #include <asm/paging.h>
24 #include <asm/p2m.h>
25 #include <xen/domain_page.h>
26 #include <asm/mtrr.h>
27 #include <asm/hvm/support.h>
28 #include <asm/hvm/cacheattr.h>
30 /* Xen holds the native MTRR MSRs */
31 extern struct mtrr_state mtrr_state;
33 static uint64_t phys_base_msr_mask;
34 static uint64_t phys_mask_msr_mask;
35 static uint32_t size_or_mask;
36 static uint32_t size_and_mask;
38 static void init_pat_entry_tbl(uint64_t pat);
39 static void init_mtrr_epat_tbl(void);
40 static uint8_t get_mtrr_type(struct mtrr_state *m, paddr_t pa);
41 /* get page attribute fields (PAn) from PAT MSR */
42 #define pat_cr_2_paf(pat_cr,n) ((((uint64_t)pat_cr) >> ((n)<<3)) & 0xff)
43 /* pat entry to PTE flags (PAT, PCD, PWT bits) */
44 static uint8_t pat_entry_2_pte_flags[8] = {
45 0, _PAGE_PWT,
46 _PAGE_PCD, _PAGE_PCD | _PAGE_PWT,
47 _PAGE_PAT, _PAGE_PAT | _PAGE_PWT,
48 _PAGE_PAT | _PAGE_PCD, _PAGE_PAT | _PAGE_PCD | _PAGE_PWT };
50 /* effective mm type lookup table, according to MTRR and PAT */
51 static uint8_t mm_type_tbl[MTRR_NUM_TYPES][PAT_TYPE_NUMS] = {
52 /********PAT(UC,WC,RS,RS,WT,WP,WB,UC-)*/
53 /* RS means reserved type(2,3), and type is hardcoded here */
54 /*MTRR(UC):(UC,WC,RS,RS,UC,UC,UC,UC)*/
55 {0, 1, 2, 2, 0, 0, 0, 0},
56 /*MTRR(WC):(UC,WC,RS,RS,UC,UC,WC,WC)*/
57 {0, 1, 2, 2, 0, 0, 1, 1},
58 /*MTRR(RS):(RS,RS,RS,RS,RS,RS,RS,RS)*/
59 {2, 2, 2, 2, 2, 2, 2, 2},
60 /*MTRR(RS):(RS,RS,RS,RS,RS,RS,RS,RS)*/
61 {2, 2, 2, 2, 2, 2, 2, 2},
62 /*MTRR(WT):(UC,WC,RS,RS,WT,WP,WT,UC)*/
63 {0, 1, 2, 2, 4, 5, 4, 0},
64 /*MTRR(WP):(UC,WC,RS,RS,WT,WP,WP,WC)*/
65 {0, 1, 2, 2, 4, 5, 5, 1},
66 /*MTRR(WB):(UC,WC,RS,RS,WT,WP,WB,UC)*/
67 {0, 1, 2, 2, 4, 5, 6, 0}
68 };
70 /* reverse lookup table, to find a pat type according to MTRR and effective
71 * memory type. This table is dynamically generated
72 */
73 static uint8_t mtrr_epat_tbl[MTRR_NUM_TYPES][MEMORY_NUM_TYPES];
75 /* lookup table for PAT entry of a given PAT value in host pat */
76 static uint8_t pat_entry_tbl[PAT_TYPE_NUMS];
78 static void get_mtrr_range(uint64_t base_msr, uint64_t mask_msr,
79 uint64_t *base, uint64_t *end)
80 {
81 uint32_t mask_lo = (uint32_t)mask_msr;
82 uint32_t mask_hi = (uint32_t)(mask_msr >> 32);
83 uint32_t base_lo = (uint32_t)base_msr;
84 uint32_t base_hi = (uint32_t)(base_msr >> 32);
85 uint32_t size;
87 if ( (mask_lo & 0x800) == 0 )
88 {
89 /* Invalid (i.e. free) range */
90 *base = 0;
91 *end = 0;
92 return;
93 }
95 /* Work out the shifted address mask. */
96 mask_lo = (size_or_mask | (mask_hi << (32 - PAGE_SHIFT)) |
97 (mask_lo >> PAGE_SHIFT));
99 /* This works correctly if size is a power of two (a contiguous range). */
100 size = -mask_lo;
101 *base = base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
102 *end = *base + size - 1;
103 }
105 bool_t is_var_mtrr_overlapped(struct mtrr_state *m)
106 {
107 int32_t seg, i;
108 uint64_t phys_base, phys_mask, phys_base_pre, phys_mask_pre;
109 uint64_t base_pre, end_pre, base, end;
110 uint8_t num_var_ranges = (uint8_t)m->mtrr_cap;
112 for ( i = 0; i < num_var_ranges; i++ )
113 {
114 phys_base_pre = ((uint64_t*)m->var_ranges)[i*2];
115 phys_mask_pre = ((uint64_t*)m->var_ranges)[i*2 + 1];
117 get_mtrr_range(phys_base_pre, phys_mask_pre,
118 &base_pre, &end_pre);
120 for ( seg = i + 1; seg < num_var_ranges; seg ++ )
121 {
122 phys_base = ((uint64_t*)m->var_ranges)[seg*2];
123 phys_mask = ((uint64_t*)m->var_ranges)[seg*2 + 1];
125 get_mtrr_range(phys_base, phys_mask,
126 &base, &end);
128 if ( ((base_pre != end_pre) && (base != end))
129 || ((base >= base_pre) && (base <= end_pre))
130 || ((end >= base_pre) && (end <= end_pre))
131 || ((base_pre >= base) && (base_pre <= end))
132 || ((end_pre >= base) && (end_pre <= end)) )
133 {
134 /* MTRR is overlapped. */
135 return 1;
136 }
137 }
138 }
139 return 0;
140 }
142 /* reserved mtrr for guest OS */
143 #define RESERVED_MTRR 2
144 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
145 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
146 bool_t mtrr_var_range_msr_set(struct mtrr_state *m, uint32_t msr,
147 uint64_t msr_content);
148 bool_t mtrr_def_type_msr_set(struct mtrr_state *m, uint64_t msr_content);
149 bool_t mtrr_fix_range_msr_set(struct mtrr_state *m, uint32_t row,
150 uint64_t msr_content);
151 static void set_var_mtrr(uint32_t reg, struct mtrr_state *m,
152 uint32_t base, uint32_t size,
153 uint32_t type)
154 {
155 struct mtrr_var_range *vr;
157 vr = &m->var_ranges[reg];
159 if ( size == 0 )
160 {
161 /* The invalid bit is kept in the mask, so we simply clear the
162 * relevant mask register to disable a range.
163 */
164 mtrr_var_range_msr_set(m, MTRRphysMask_MSR(reg), 0);
165 }
166 else
167 {
168 vr->base_lo = base << PAGE_SHIFT | type;
169 vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
170 vr->mask_lo = -size << PAGE_SHIFT | 0x800;
171 vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
173 mtrr_var_range_msr_set(m, MTRRphysBase_MSR(reg), *(uint64_t *)vr);
174 mtrr_var_range_msr_set(m, MTRRphysMask_MSR(reg),
175 *((uint64_t *)vr + 1));
176 }
177 }
178 /* From Intel Vol. III Section 10.11.4, the Range Size and Base Alignment has
179 * some kind of requirement:
180 * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum).
181 * 2. The base address must be 2^N aligned, where the N here is equal to
182 * the N in previous requirement. So a 8K range must be 8K aligned not 4K aligned.
183 */
184 static uint32_t range_to_mtrr(uint32_t reg, struct mtrr_state *m,
185 uint32_t range_startk, uint32_t range_sizek,
186 uint8_t type)
187 {
188 if ( !range_sizek || (reg >= ((m->mtrr_cap & 0xff) - RESERVED_MTRR)) )
189 {
190 gdprintk(XENLOG_WARNING,
191 "Failed to init var mtrr msr[%d]"
192 "range_size:%x, total available MSR:%d\n",
193 reg, range_sizek,
194 (uint32_t)((m->mtrr_cap & 0xff) - RESERVED_MTRR));
195 return reg;
196 }
198 while ( range_sizek )
199 {
200 uint32_t max_align, align, sizek;
202 max_align = (range_startk == 0) ? 32 : ffs(range_startk);
203 align = min_t(uint32_t, fls(range_sizek), max_align);
204 sizek = 1 << (align - 1);
206 set_var_mtrr(reg++, m, range_startk, sizek, type);
208 range_startk += sizek;
209 range_sizek -= sizek;
211 if ( reg >= ((m->mtrr_cap & 0xff) - RESERVED_MTRR) )
212 {
213 gdprintk(XENLOG_WARNING,
214 "Failed to init var mtrr msr[%d],"
215 "total available MSR:%d\n",
216 reg, (uint32_t)((m->mtrr_cap & 0xff) - RESERVED_MTRR));
217 break;
218 }
219 }
221 return reg;
222 }
224 static void setup_fixed_mtrrs(struct vcpu *v)
225 {
226 uint64_t content;
227 int32_t i;
228 struct mtrr_state *m = &v->arch.hvm_vcpu.mtrr;
230 /* 1. Map (0~A0000) as WB */
231 content = 0x0606060606060606ull;
232 mtrr_fix_range_msr_set(m, 0, content);
233 mtrr_fix_range_msr_set(m, 1, content);
234 /* 2. Map VRAM(A0000~C0000) as WC */
235 content = 0x0101010101010101;
236 mtrr_fix_range_msr_set(m, 2, content);
237 /* 3. Map (C0000~100000) as UC */
238 for ( i = 3; i < 11; i++)
239 mtrr_fix_range_msr_set(m, i, 0);
240 }
242 static void setup_var_mtrrs(struct vcpu *v)
243 {
244 p2m_type_t p2m;
245 uint64_t e820_mfn;
246 int8_t *p = NULL;
247 uint8_t nr = 0;
248 int32_t i;
249 uint32_t reg = 0;
250 uint64_t size = 0;
251 uint64_t addr = 0;
252 struct e820entry *e820_table;
254 e820_mfn = mfn_x(gfn_to_mfn(v->domain,
255 HVM_E820_PAGE >> PAGE_SHIFT, &p2m));
257 p = (int8_t *)map_domain_page(e820_mfn);
259 nr = *(uint8_t*)(p + HVM_E820_NR_OFFSET);
260 e820_table = (struct e820entry*)(p + HVM_E820_OFFSET);
261 /* search E820 table, set MTRR for RAM */
262 for ( i = 0; i < nr; i++)
263 {
264 if ( (e820_table[i].addr >= 0x100000) &&
265 (e820_table[i].type == E820_RAM) )
266 {
267 if ( e820_table[i].addr == 0x100000 )
268 {
269 size = e820_table[i].size + 0x100000 + PAGE_SIZE * 4;
270 addr = 0;
271 }
272 else
273 {
274 /* Larger than 4G */
275 size = e820_table[i].size;
276 addr = e820_table[i].addr;
277 }
279 reg = range_to_mtrr(reg, &v->arch.hvm_vcpu.mtrr,
280 addr >> PAGE_SHIFT, size >> PAGE_SHIFT,
281 MTRR_TYPE_WRBACK);
282 }
283 }
284 }
286 void init_mtrr_in_hyper(struct vcpu *v)
287 {
288 /* TODO:MTRR should be initialized in BIOS or other places.
289 * workaround to do it in here
290 */
291 if ( v->arch.hvm_vcpu.mtrr.is_initialized )
292 return;
294 setup_fixed_mtrrs(v);
295 setup_var_mtrrs(v);
296 /* enable mtrr */
297 mtrr_def_type_msr_set(&v->arch.hvm_vcpu.mtrr, 0xc00);
299 v->arch.hvm_vcpu.mtrr.is_initialized = 1;
300 }
302 static int32_t reset_mtrr(struct mtrr_state *m)
303 {
304 m->var_ranges = xmalloc_array(struct mtrr_var_range, MTRR_VCNT);
305 if ( m->var_ranges == NULL )
306 return -ENOMEM;
307 memset(m->var_ranges, 0, MTRR_VCNT * sizeof(struct mtrr_var_range));
308 memset(m->fixed_ranges, 0, sizeof(m->fixed_ranges));
309 m->enabled = 0;
310 m->def_type = 0;/*mtrr is disabled*/
311 m->mtrr_cap = (0x5<<8)|MTRR_VCNT;/*wc,fix enabled, and vcnt=8*/
312 m->overlapped = 0;
313 return 0;
314 }
316 /* init global variables for MTRR and PAT */
317 void global_init_mtrr_pat(void)
318 {
319 extern uint64_t host_pat;
320 uint32_t phys_addr;
322 init_mtrr_epat_tbl();
323 init_pat_entry_tbl(host_pat);
324 /* Get max physical address, set some global variable */
325 if ( cpuid_eax(0x80000000) < 0x80000008 )
326 phys_addr = 36;
327 else
328 phys_addr = cpuid_eax(0x80000008);
330 phys_base_msr_mask = ~((((uint64_t)1) << phys_addr) - 1) | 0xf00UL;
331 phys_mask_msr_mask = ~((((uint64_t)1) << phys_addr) - 1) | 0x7ffUL;
333 size_or_mask = ~((1 << (phys_addr - PAGE_SHIFT)) - 1);
334 size_and_mask = ~size_or_mask & 0xfff00000;
335 }
337 static void init_pat_entry_tbl(uint64_t pat)
338 {
339 int32_t i, j;
341 memset(&pat_entry_tbl, INVALID_MEM_TYPE,
342 PAT_TYPE_NUMS * sizeof(pat_entry_tbl[0]));
344 for ( i = 0; i < PAT_TYPE_NUMS; i++ )
345 {
346 for ( j = 0; j < PAT_TYPE_NUMS; j++ )
347 {
348 if ( pat_cr_2_paf(pat, j) == i )
349 {
350 pat_entry_tbl[i] = j;
351 break;
352 }
353 }
354 }
355 }
357 uint8_t pat_type_2_pte_flags(uint8_t pat_type)
358 {
359 int32_t pat_entry = pat_entry_tbl[pat_type];
361 /* INVALID_MEM_TYPE, means doesn't find the pat_entry in host pat for
362 * a given pat_type. If host pat covers all the pat types,
363 * it can't happen.
364 */
365 if ( likely(pat_entry != INVALID_MEM_TYPE) )
366 return pat_entry_2_pte_flags[pat_entry];
368 return pat_entry_2_pte_flags[pat_entry_tbl[PAT_TYPE_UNCACHABLE]];
369 }
371 int32_t reset_vmsr(struct mtrr_state *m, uint64_t *pat_ptr)
372 {
373 int32_t rc;
375 rc = reset_mtrr(m);
376 if ( rc != 0 )
377 return rc;
379 *pat_ptr = ((uint64_t)PAT_TYPE_WRBACK) | /* PAT0: WB */
380 ((uint64_t)PAT_TYPE_WRTHROUGH << 8) | /* PAT1: WT */
381 ((uint64_t)PAT_TYPE_UC_MINUS << 16) | /* PAT2: UC- */
382 ((uint64_t)PAT_TYPE_UNCACHABLE << 24) | /* PAT3: UC */
383 ((uint64_t)PAT_TYPE_WRBACK << 32) | /* PAT4: WB */
384 ((uint64_t)PAT_TYPE_WRTHROUGH << 40) | /* PAT5: WT */
385 ((uint64_t)PAT_TYPE_UC_MINUS << 48) | /* PAT6: UC- */
386 ((uint64_t)PAT_TYPE_UNCACHABLE << 56); /* PAT7: UC */
388 return 0;
389 }
391 /*
392 * Get MTRR memory type for physical address pa.
393 */
394 static uint8_t get_mtrr_type(struct mtrr_state *m, paddr_t pa)
395 {
396 int32_t addr, seg, index;
397 uint8_t overlap_mtrr = 0;
398 uint8_t overlap_mtrr_pos = 0;
399 uint64_t phys_base;
400 uint64_t phys_mask;
401 uint8_t num_var_ranges = m->mtrr_cap & 0xff;
403 if ( unlikely(!(m->enabled & 0x2)) )
404 return MTRR_TYPE_UNCACHABLE;
406 if ( (pa < 0x100000) && (m->enabled & 1) )
407 {
408 /* Fixed range MTRR takes effective */
409 addr = (uint32_t) pa;
410 if ( addr < 0x80000 )
411 {
412 seg = (addr >> 16);
413 return m->fixed_ranges[seg];
414 }
415 else if ( addr < 0xc0000 )
416 {
417 seg = (addr - 0x80000) >> 14;
418 index = (seg >> 3) + 1;
419 seg &= 7; /* select 0-7 segments */
420 return m->fixed_ranges[index*8 + seg];
421 }
422 else
423 {
424 /* 0xC0000 --- 0x100000 */
425 seg = (addr - 0xc0000) >> 12;
426 index = (seg >> 3) + 3;
427 seg &= 7; /* select 0-7 segments */
428 return m->fixed_ranges[index*8 + seg];
429 }
430 }
432 /* Match with variable MTRRs. */
433 for ( seg = 0; seg < num_var_ranges; seg++ )
434 {
435 phys_base = ((uint64_t*)m->var_ranges)[seg*2];
436 phys_mask = ((uint64_t*)m->var_ranges)[seg*2 + 1];
437 if ( phys_mask & (1 << MTRR_PHYSMASK_VALID_BIT) )
438 {
439 if ( ((uint64_t) pa & phys_mask) >> MTRR_PHYSMASK_SHIFT ==
440 (phys_base & phys_mask) >> MTRR_PHYSMASK_SHIFT )
441 {
442 if ( unlikely(m->overlapped) )
443 {
444 overlap_mtrr |= 1 << (phys_base & MTRR_PHYSBASE_TYPE_MASK);
445 overlap_mtrr_pos = phys_base & MTRR_PHYSBASE_TYPE_MASK;
446 }
447 else
448 {
449 /* If no overlap, return the found one */
450 return (phys_base & MTRR_PHYSBASE_TYPE_MASK);
451 }
452 }
453 }
454 }
456 /* Overlapped or not found. */
457 if ( unlikely(overlap_mtrr == 0) )
458 return m->def_type;
460 if ( likely(!(overlap_mtrr & ~( ((uint8_t)1) << overlap_mtrr_pos ))) )
461 /* Covers both one variable memory range matches and
462 * two or more identical match.
463 */
464 return overlap_mtrr_pos;
466 if ( overlap_mtrr & 0x1 )
467 /* Two or more match, one is UC. */
468 return MTRR_TYPE_UNCACHABLE;
470 if ( !(overlap_mtrr & 0xaf) )
471 /* Two or more match, WT and WB. */
472 return MTRR_TYPE_WRTHROUGH;
474 /* Behaviour is undefined, but return the last overlapped type. */
475 return overlap_mtrr_pos;
476 }
478 /*
479 * return the memory type from PAT.
480 * NOTE: valid only when paging is enabled.
481 * Only 4K page PTE is supported now.
482 */
483 static uint8_t page_pat_type(uint64_t pat_cr, uint32_t pte_flags)
484 {
485 int32_t pat_entry;
487 /* PCD/PWT -> bit 1/0 of PAT entry */
488 pat_entry = ( pte_flags >> 3 ) & 0x3;
489 /* PAT bits as bit 2 of PAT entry */
490 if ( pte_flags & _PAGE_PAT )
491 pat_entry |= 4;
493 return (uint8_t)pat_cr_2_paf(pat_cr, pat_entry);
494 }
496 /*
497 * Effective memory type for leaf page.
498 */
499 static uint8_t effective_mm_type(struct mtrr_state *m,
500 uint64_t pat,
501 paddr_t gpa,
502 uint32_t pte_flags)
503 {
504 uint8_t mtrr_mtype, pat_value, effective;
506 mtrr_mtype = get_mtrr_type(m, gpa);
508 pat_value = page_pat_type(pat, pte_flags);
510 effective = mm_type_tbl[mtrr_mtype][pat_value];
512 return effective;
513 }
515 static void init_mtrr_epat_tbl(void)
516 {
517 int32_t i, j;
518 /* set default value to an invalid type, just for checking conflict */
519 memset(&mtrr_epat_tbl, INVALID_MEM_TYPE, sizeof(mtrr_epat_tbl));
521 for ( i = 0; i < MTRR_NUM_TYPES; i++ )
522 {
523 for ( j = 0; j < PAT_TYPE_NUMS; j++ )
524 {
525 int32_t tmp = mm_type_tbl[i][j];
526 if ( (tmp >= 0) && (tmp < MEMORY_NUM_TYPES) )
527 mtrr_epat_tbl[i][tmp] = j;
528 }
529 }
530 }
532 uint32_t get_pat_flags(struct vcpu *v,
533 uint32_t gl1e_flags,
534 paddr_t gpaddr,
535 paddr_t spaddr)
536 {
537 uint8_t guest_eff_mm_type;
538 uint8_t shadow_mtrr_type;
539 uint8_t pat_entry_value;
540 uint64_t pat = v->arch.hvm_vcpu.pat_cr;
541 struct mtrr_state *g = &v->arch.hvm_vcpu.mtrr;
543 /* 1. Get the effective memory type of guest physical address,
544 * with the pair of guest MTRR and PAT
545 */
546 guest_eff_mm_type = effective_mm_type(g, pat, gpaddr, gl1e_flags);
547 /* 2. Get the memory type of host physical address, with MTRR */
548 shadow_mtrr_type = get_mtrr_type(&mtrr_state, spaddr);
550 /* 3. Find the memory type in PAT, with host MTRR memory type
551 * and guest effective memory type.
552 */
553 pat_entry_value = mtrr_epat_tbl[shadow_mtrr_type][guest_eff_mm_type];
554 /* If conflit occurs(e.g host MTRR is UC, guest memory type is
555 * WB),set UC as effective memory. Here, returning PAT_TYPE_UNCACHABLE will
556 * always set effective memory as UC.
557 */
558 if ( pat_entry_value == INVALID_MEM_TYPE )
559 {
560 gdprintk(XENLOG_WARNING,
561 "Conflict occurs for a given guest l1e flags:%x "
562 "at %"PRIx64" (the effective mm type:%d), "
563 "because the host mtrr type is:%d\n",
564 gl1e_flags, (uint64_t)gpaddr, guest_eff_mm_type,
565 shadow_mtrr_type);
566 pat_entry_value = PAT_TYPE_UNCACHABLE;
567 }
568 /* 4. Get the pte flags */
569 return pat_type_2_pte_flags(pat_entry_value);
570 }
572 /* Helper funtions for seting mtrr/pat */
573 bool_t pat_msr_set(uint64_t *pat, uint64_t msr_content)
574 {
575 uint8_t *value = (uint8_t*)&msr_content;
576 int32_t i;
578 if ( *pat != msr_content )
579 {
580 for ( i = 0; i < 8; i++ )
581 if ( unlikely(!(value[i] == 0 || value[i] == 1 ||
582 value[i] == 4 || value[i] == 5 ||
583 value[i] == 6 || value[i] == 7)) )
584 return 0;
586 *pat = msr_content;
587 }
589 return 1;
590 }
592 bool_t mtrr_def_type_msr_set(struct mtrr_state *m, uint64_t msr_content)
593 {
594 uint8_t def_type = msr_content & 0xff;
595 uint8_t enabled = (msr_content >> 10) & 0x3;
597 if ( unlikely(!(def_type == 0 || def_type == 1 || def_type == 4 ||
598 def_type == 5 || def_type == 6)) )
599 {
600 HVM_DBG_LOG(DBG_LEVEL_MSR, "invalid MTRR def type:%x\n", def_type);
601 return 0;
602 }
604 if ( unlikely(msr_content && (msr_content & ~0xcffUL)) )
605 {
606 HVM_DBG_LOG(DBG_LEVEL_MSR, "invalid msr content:%"PRIx64"\n",
607 msr_content);
608 return 0;
609 }
611 m->enabled = enabled;
612 m->def_type = def_type;
614 return 1;
615 }
617 bool_t mtrr_fix_range_msr_set(struct mtrr_state *m, uint32_t row,
618 uint64_t msr_content)
619 {
620 uint64_t *fixed_range_base = (uint64_t *)m->fixed_ranges;
622 if ( fixed_range_base[row] != msr_content )
623 {
624 uint8_t *range = (uint8_t*)&msr_content;
625 int32_t i, type;
627 for ( i = 0; i < 8; i++ )
628 {
629 type = range[i];
630 if ( unlikely(!(type == 0 || type == 1 ||
631 type == 4 || type == 5 || type == 6)) )
632 return 0;
633 }
635 fixed_range_base[row] = msr_content;
636 }
638 return 1;
639 }
641 bool_t mtrr_var_range_msr_set(struct mtrr_state *m, uint32_t msr,
642 uint64_t msr_content)
643 {
644 uint32_t index;
645 uint64_t msr_mask;
646 uint64_t *var_range_base = (uint64_t*)m->var_ranges;
648 index = msr - MSR_IA32_MTRR_PHYSBASE0;
650 if ( var_range_base[index] != msr_content )
651 {
652 uint32_t type = msr_content & 0xff;
654 msr_mask = (index & 1) ? phys_mask_msr_mask : phys_base_msr_mask;
656 if ( unlikely(!(type == 0 || type == 1 ||
657 type == 4 || type == 5 || type == 6)) )
658 return 0;
660 if ( unlikely(msr_content && (msr_content & msr_mask)) )
661 {
662 HVM_DBG_LOG(DBG_LEVEL_MSR, "invalid msr content:%"PRIx64"\n",
663 msr_content);
664 return 0;
665 }
667 var_range_base[index] = msr_content;
668 }
670 m->overlapped = is_var_mtrr_overlapped(m);
672 return 1;
673 }
675 bool_t mtrr_pat_not_equal(struct vcpu *vd, struct vcpu *vs)
676 {
677 struct mtrr_state *md = &vd->arch.hvm_vcpu.mtrr;
678 struct mtrr_state *ms = &vs->arch.hvm_vcpu.mtrr;
679 int32_t res;
680 uint8_t num_var_ranges = (uint8_t)md->mtrr_cap;
682 /* Test fixed ranges. */
683 res = memcmp(md->fixed_ranges, ms->fixed_ranges,
684 NUM_FIXED_RANGES*sizeof(mtrr_type));
685 if ( res )
686 return 1;
688 /* Test var ranges. */
689 res = memcmp(md->var_ranges, ms->var_ranges,
690 num_var_ranges*sizeof(struct mtrr_var_range));
691 if ( res )
692 return 1;
694 /* Test default type MSR. */
695 if ( (md->def_type != ms->def_type)
696 && (md->enabled != ms->enabled) )
697 return 1;
699 /* Test PAT. */
700 if ( vd->arch.hvm_vcpu.pat_cr != vs->arch.hvm_vcpu.pat_cr )
701 return 1;
703 return 0;
704 }
706 void hvm_init_cacheattr_region_list(
707 struct domain *d)
708 {
709 INIT_LIST_HEAD(&d->arch.hvm_domain.pinned_cacheattr_ranges);
710 }
712 void hvm_destroy_cacheattr_region_list(
713 struct domain *d)
714 {
715 struct list_head *head = &d->arch.hvm_domain.pinned_cacheattr_ranges;
716 struct hvm_mem_pinned_cacheattr_range *range;
718 while ( !list_empty(head) )
719 {
720 range = list_entry(head->next,
721 struct hvm_mem_pinned_cacheattr_range,
722 list);
723 list_del(&range->list);
724 xfree(range);
725 }
726 }
728 int32_t hvm_get_mem_pinned_cacheattr(
729 struct domain *d,
730 uint64_t guest_fn,
731 uint32_t *type)
732 {
733 struct hvm_mem_pinned_cacheattr_range *range;
735 *type = 0;
737 if ( !is_hvm_domain(d) )
738 return 0;
740 list_for_each_entry_rcu ( range,
741 &d->arch.hvm_domain.pinned_cacheattr_ranges,
742 list )
743 {
744 if ( (guest_fn >= range->start) && (guest_fn <= range->end) )
745 {
746 *type = range->type;
747 return 1;
748 }
749 }
751 return 0;
752 }
754 int32_t hvm_set_mem_pinned_cacheattr(
755 struct domain *d,
756 uint64_t gfn_start,
757 uint64_t gfn_end,
758 uint32_t type)
759 {
760 struct hvm_mem_pinned_cacheattr_range *range;
762 if ( !((type == PAT_TYPE_UNCACHABLE) ||
763 (type == PAT_TYPE_WRCOMB) ||
764 (type == PAT_TYPE_WRTHROUGH) ||
765 (type == PAT_TYPE_WRPROT) ||
766 (type == PAT_TYPE_WRBACK) ||
767 (type == PAT_TYPE_UC_MINUS)) ||
768 !is_hvm_domain(d) )
769 return -EINVAL;
771 range = xmalloc(struct hvm_mem_pinned_cacheattr_range);
772 if ( range == NULL )
773 return -ENOMEM;
775 memset(range, 0, sizeof(*range));
777 range->start = gfn_start;
778 range->end = gfn_end;
779 range->type = type;
781 list_add_rcu(&range->list, &d->arch.hvm_domain.pinned_cacheattr_ranges);
783 return 0;
784 }
786 static int hvm_save_mtrr_msr(struct domain *d, hvm_domain_context_t *h)
787 {
788 int i;
789 struct vcpu *v;
790 struct hvm_hw_mtrr hw_mtrr;
791 struct mtrr_state *mtrr_state;
792 /* save mtrr&pat */
793 for_each_vcpu(d, v)
794 {
795 mtrr_state = &v->arch.hvm_vcpu.mtrr;
797 hw_mtrr.msr_pat_cr = v->arch.hvm_vcpu.pat_cr;
799 hw_mtrr.msr_mtrr_def_type = mtrr_state->def_type
800 | (mtrr_state->enabled << 10);
801 hw_mtrr.msr_mtrr_cap = mtrr_state->mtrr_cap;
803 for ( i = 0; i < MTRR_VCNT; i++ )
804 {
805 /* save physbase */
806 hw_mtrr.msr_mtrr_var[i*2] =
807 ((uint64_t*)mtrr_state->var_ranges)[i*2];
808 /* save physmask */
809 hw_mtrr.msr_mtrr_var[i*2+1] =
810 ((uint64_t*)mtrr_state->var_ranges)[i*2+1];
811 }
813 for ( i = 0; i < NUM_FIXED_MSR; i++ )
814 hw_mtrr.msr_mtrr_fixed[i] =
815 ((uint64_t*)mtrr_state->fixed_ranges)[i];
817 if ( hvm_save_entry(MTRR, v->vcpu_id, h, &hw_mtrr) != 0 )
818 return 1;
819 }
820 return 0;
821 }
823 static int hvm_load_mtrr_msr(struct domain *d, hvm_domain_context_t *h)
824 {
825 int vcpuid, i;
826 struct vcpu *v;
827 struct mtrr_state *mtrr_state;
828 struct hvm_hw_mtrr hw_mtrr;
830 vcpuid = hvm_load_instance(h);
831 if ( vcpuid > MAX_VIRT_CPUS || (v = d->vcpu[vcpuid]) == NULL )
832 {
833 gdprintk(XENLOG_ERR, "HVM restore: domain has no vcpu %u\n", vcpuid);
834 return -EINVAL;
835 }
837 if ( hvm_load_entry(MTRR, h, &hw_mtrr) != 0 )
838 return -EINVAL;
840 mtrr_state = &v->arch.hvm_vcpu.mtrr;
842 pat_msr_set(&v->arch.hvm_vcpu.pat_cr, hw_mtrr.msr_pat_cr);
844 mtrr_state->mtrr_cap = hw_mtrr.msr_mtrr_cap;
846 for ( i = 0; i < NUM_FIXED_MSR; i++ )
847 mtrr_fix_range_msr_set(mtrr_state, i, hw_mtrr.msr_mtrr_fixed[i]);
849 for ( i = 0; i < MTRR_VCNT; i++ )
850 {
851 mtrr_var_range_msr_set(mtrr_state,
852 MTRRphysBase_MSR(i), hw_mtrr.msr_mtrr_var[i*2]);
853 mtrr_var_range_msr_set(mtrr_state,
854 MTRRphysMask_MSR(i), hw_mtrr.msr_mtrr_var[i*2+1]);
855 }
857 mtrr_def_type_msr_set(mtrr_state, hw_mtrr.msr_mtrr_def_type);
859 v->arch.hvm_vcpu.mtrr.is_initialized = 1;
860 return 0;
861 }
863 HVM_REGISTER_SAVE_RESTORE(MTRR, hvm_save_mtrr_msr, hvm_load_mtrr_msr,
864 1, HVMSR_PER_VCPU);