ia64/xen-unstable

view xen/arch/ia64/linux-xen/setup.c @ 5987:5f1ed597f107

Ensure percpu data area not used before the TR is set.
author fred@xuni-t01.sc.intel.com
date Tue Aug 23 18:43:18 2005 -0800 (2005-08-23)
parents 1ec2225aa8c6
children 9312a3e8a6f8
line source
1 /*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, Rohit Seth <rohit.seth@intel.com>
8 * Copyright (C) 1999 VA Linux Systems
9 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
10 *
11 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
12 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
13 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
14 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
15 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
16 * 01/07/99 S.Eranian added the support for command line argument
17 * 06/24/99 W.Drummond added boot_cpu_data.
18 */
19 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
23 #include <linux/acpi.h>
24 #include <linux/bootmem.h>
25 #include <linux/console.h>
26 #include <linux/delay.h>
27 #include <linux/kernel.h>
28 #include <linux/reboot.h>
29 #include <linux/sched.h>
30 #include <linux/seq_file.h>
31 #include <linux/string.h>
32 #include <linux/threads.h>
33 #include <linux/tty.h>
34 #include <linux/serial.h>
35 #include <linux/serial_core.h>
36 #include <linux/efi.h>
37 #include <linux/initrd.h>
39 #include <asm/ia32.h>
40 #include <asm/machvec.h>
41 #include <asm/mca.h>
42 #include <asm/meminit.h>
43 #include <asm/page.h>
44 #include <asm/patch.h>
45 #include <asm/pgtable.h>
46 #include <asm/processor.h>
47 #include <asm/sal.h>
48 #include <asm/sections.h>
49 #include <asm/serial.h>
50 #include <asm/setup.h>
51 #include <asm/smp.h>
52 #include <asm/system.h>
53 #include <asm/unistd.h>
54 #include <asm/vmx.h>
55 #include <asm/io.h>
57 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
58 # error "struct cpuinfo_ia64 too big!"
59 #endif
61 #ifdef CONFIG_SMP
62 unsigned long __per_cpu_offset[NR_CPUS];
63 EXPORT_SYMBOL(__per_cpu_offset);
64 #endif
66 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
67 DEFINE_PER_CPU(cpu_kr_ia64_t, cpu_kr);
68 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
69 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
70 unsigned long ia64_cycles_per_usec;
71 struct ia64_boot_param *ia64_boot_param;
72 struct screen_info screen_info;
74 unsigned long ia64_max_cacheline_size;
75 unsigned long ia64_iobase; /* virtual address for I/O accesses */
76 EXPORT_SYMBOL(ia64_iobase);
77 struct io_space io_space[MAX_IO_SPACES];
78 EXPORT_SYMBOL(io_space);
79 unsigned int num_io_spaces;
81 unsigned char aux_device_present = 0xaa; /* XXX remove this when legacy I/O is gone */
83 /*
84 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
85 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
86 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
87 * address of the second buffer must be aligned to (merge_mask+1) in order to be
88 * mergeable). By default, we assume there is no I/O MMU which can merge physically
89 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
90 * page-size of 2^64.
91 */
92 unsigned long ia64_max_iommu_merge_mask = ~0UL;
93 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
95 /*
96 * We use a special marker for the end of memory and it uses the extra (+1) slot
97 */
98 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
99 int num_rsvd_regions;
102 /*
103 * Filter incoming memory segments based on the primitive map created from the boot
104 * parameters. Segments contained in the map are removed from the memory ranges. A
105 * caller-specified function is called with the memory ranges that remain after filtering.
106 * This routine does not assume the incoming segments are sorted.
107 */
108 int
109 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
110 {
111 unsigned long range_start, range_end, prev_start;
112 void (*func)(unsigned long, unsigned long, int);
113 int i;
115 #if IGNORE_PFN0
116 if (start == PAGE_OFFSET) {
117 printk(KERN_WARNING "warning: skipping physical page 0\n");
118 start += PAGE_SIZE;
119 if (start >= end) return 0;
120 }
121 #endif
122 /*
123 * lowest possible address(walker uses virtual)
124 */
125 prev_start = PAGE_OFFSET;
126 func = arg;
128 for (i = 0; i < num_rsvd_regions; ++i) {
129 range_start = max(start, prev_start);
130 range_end = min(end, rsvd_region[i].start);
132 if (range_start < range_end)
133 #ifdef XEN
134 {
135 /* init_boot_pages requires "ps, pe" */
136 printk("Init boot pages: 0x%lx -> 0x%lx.\n",
137 __pa(range_start), __pa(range_end));
138 (*func)(__pa(range_start), __pa(range_end), 0);
139 }
140 #else
141 call_pernode_memory(__pa(range_start), range_end - range_start, func);
142 #endif
144 /* nothing more available in this segment */
145 if (range_end == end) return 0;
147 prev_start = rsvd_region[i].end;
148 }
149 /* end of memory marker allows full processing inside loop body */
150 return 0;
151 }
153 static void
154 sort_regions (struct rsvd_region *rsvd_region, int max)
155 {
156 int j;
158 /* simple bubble sorting */
159 while (max--) {
160 for (j = 0; j < max; ++j) {
161 if (rsvd_region[j].start > rsvd_region[j+1].start) {
162 struct rsvd_region tmp;
163 tmp = rsvd_region[j];
164 rsvd_region[j] = rsvd_region[j + 1];
165 rsvd_region[j + 1] = tmp;
166 }
167 }
168 }
169 }
171 /**
172 * reserve_memory - setup reserved memory areas
173 *
174 * Setup the reserved memory areas set aside for the boot parameters,
175 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
176 * see include/asm-ia64/meminit.h if you need to define more.
177 */
178 void
179 reserve_memory (void)
180 {
181 int n = 0;
183 /*
184 * none of the entries in this table overlap
185 */
186 rsvd_region[n].start = (unsigned long) ia64_boot_param;
187 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
188 n++;
190 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
191 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
192 n++;
194 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
195 rsvd_region[n].end = (rsvd_region[n].start
196 + strlen(__va(ia64_boot_param->command_line)) + 1);
197 n++;
199 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
200 #ifdef XEN
201 /* Reserve xen image/bitmap/xen-heap */
202 rsvd_region[n].end = rsvd_region[n].start + xenheap_size;
203 #else
204 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
205 #endif
206 n++;
208 #ifdef CONFIG_BLK_DEV_INITRD
209 if (ia64_boot_param->initrd_start) {
210 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
211 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
212 n++;
213 }
214 #endif
216 /* end of memory marker */
217 rsvd_region[n].start = ~0UL;
218 rsvd_region[n].end = ~0UL;
219 n++;
221 num_rsvd_regions = n;
223 sort_regions(rsvd_region, num_rsvd_regions);
224 }
226 /**
227 * find_initrd - get initrd parameters from the boot parameter structure
228 *
229 * Grab the initrd start and end from the boot parameter struct given us by
230 * the boot loader.
231 */
232 void
233 find_initrd (void)
234 {
235 #ifdef CONFIG_BLK_DEV_INITRD
236 if (ia64_boot_param->initrd_start) {
237 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
238 initrd_end = initrd_start+ia64_boot_param->initrd_size;
240 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
241 initrd_start, ia64_boot_param->initrd_size);
242 }
243 #endif
244 }
246 static void __init
247 io_port_init (void)
248 {
249 extern unsigned long ia64_iobase;
250 unsigned long phys_iobase;
252 /*
253 * Set `iobase' to the appropriate address in region 6 (uncached access range).
254 *
255 * The EFI memory map is the "preferred" location to get the I/O port space base,
256 * rather the relying on AR.KR0. This should become more clear in future SAL
257 * specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is
258 * found in the memory map.
259 */
260 phys_iobase = efi_get_iobase();
261 if (phys_iobase)
262 /* set AR.KR0 since this is all we use it for anyway */
263 ia64_set_kr(IA64_KR_IO_BASE, phys_iobase);
264 else {
265 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
266 printk(KERN_INFO "No I/O port range found in EFI memory map, falling back "
267 "to AR.KR0\n");
268 printk(KERN_INFO "I/O port base = 0x%lx\n", phys_iobase);
269 }
270 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
272 /* setup legacy IO port space */
273 io_space[0].mmio_base = ia64_iobase;
274 io_space[0].sparse = 1;
275 num_io_spaces = 1;
276 }
278 /**
279 * early_console_setup - setup debugging console
280 *
281 * Consoles started here require little enough setup that we can start using
282 * them very early in the boot process, either right after the machine
283 * vector initialization, or even before if the drivers can detect their hw.
284 *
285 * Returns non-zero if a console couldn't be setup.
286 */
287 static inline int __init
288 early_console_setup (char *cmdline)
289 {
290 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
291 {
292 extern int sn_serial_console_early_setup(void);
293 if (!sn_serial_console_early_setup())
294 return 0;
295 }
296 #endif
297 #ifdef CONFIG_EFI_PCDP
298 if (!efi_setup_pcdp_console(cmdline))
299 return 0;
300 #endif
301 #ifdef CONFIG_SERIAL_8250_CONSOLE
302 if (!early_serial_console_init(cmdline))
303 return 0;
304 #endif
306 return -1;
307 }
309 static inline void
310 mark_bsp_online (void)
311 {
312 #ifdef CONFIG_SMP
313 /* If we register an early console, allow CPU 0 to printk */
314 cpu_set(smp_processor_id(), cpu_online_map);
315 #endif
316 }
318 void __init
319 #ifdef XEN
320 early_setup_arch (char **cmdline_p)
321 #else
322 setup_arch (char **cmdline_p)
323 #endif
324 {
325 unw_init();
327 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
329 *cmdline_p = __va(ia64_boot_param->command_line);
330 #ifdef XEN
331 efi_init();
332 #else
333 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
335 efi_init();
336 io_port_init();
337 #endif
339 #ifdef CONFIG_IA64_GENERIC
340 {
341 const char *mvec_name = strstr (*cmdline_p, "machvec=");
342 char str[64];
344 if (mvec_name) {
345 const char *end;
346 size_t len;
348 mvec_name += 8;
349 end = strchr (mvec_name, ' ');
350 if (end)
351 len = end - mvec_name;
352 else
353 len = strlen (mvec_name);
354 len = min(len, sizeof (str) - 1);
355 strncpy (str, mvec_name, len);
356 str[len] = '\0';
357 mvec_name = str;
358 } else
359 mvec_name = acpi_get_sysname();
360 machvec_init(mvec_name);
361 }
362 #endif
364 #ifdef XEN
365 early_cmdline_parse(cmdline_p);
366 cmdline_parse(*cmdline_p);
367 #undef CONFIG_ACPI_BOOT
368 #endif
369 if (early_console_setup(*cmdline_p) == 0)
370 mark_bsp_online();
372 #ifdef CONFIG_ACPI_BOOT
373 /* Initialize the ACPI boot-time table parser */
374 acpi_table_init();
375 # ifdef CONFIG_ACPI_NUMA
376 acpi_numa_init();
377 # endif
378 #else
379 # ifdef CONFIG_SMP
380 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
381 # endif
382 #endif /* CONFIG_APCI_BOOT */
384 #ifndef XEN
385 find_memory();
386 #else
387 io_port_init();
388 }
390 void __init
391 late_setup_arch (char **cmdline_p)
392 {
393 #undef CONFIG_ACPI_BOOT
394 acpi_table_init();
395 #endif
396 /* process SAL system table: */
397 ia64_sal_init(efi.sal_systab);
399 #ifdef CONFIG_SMP
400 cpu_physical_id(0) = hard_smp_processor_id();
401 #endif
403 #ifdef XEN
404 identify_vmx_feature();
405 #endif
407 cpu_init(); /* initialize the bootstrap CPU */
409 #ifdef CONFIG_ACPI_BOOT
410 acpi_boot_init();
411 #endif
413 #ifdef CONFIG_VT
414 if (!conswitchp) {
415 # if defined(CONFIG_DUMMY_CONSOLE)
416 conswitchp = &dummy_con;
417 # endif
418 # if defined(CONFIG_VGA_CONSOLE)
419 /*
420 * Non-legacy systems may route legacy VGA MMIO range to system
421 * memory. vga_con probes the MMIO hole, so memory looks like
422 * a VGA device to it. The EFI memory map can tell us if it's
423 * memory so we can avoid this problem.
424 */
425 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
426 conswitchp = &vga_con;
427 # endif
428 }
429 #endif
431 /* enable IA-64 Machine Check Abort Handling unless disabled */
432 if (!strstr(saved_command_line, "nomca"))
433 ia64_mca_init();
435 platform_setup(cmdline_p);
436 paging_init();
437 }
439 /*
440 * Display cpu info for all cpu's.
441 */
442 static int
443 show_cpuinfo (struct seq_file *m, void *v)
444 {
445 #ifdef CONFIG_SMP
446 # define lpj c->loops_per_jiffy
447 # define cpunum c->cpu
448 #else
449 # define lpj loops_per_jiffy
450 # define cpunum 0
451 #endif
452 static struct {
453 unsigned long mask;
454 const char *feature_name;
455 } feature_bits[] = {
456 { 1UL << 0, "branchlong" },
457 { 1UL << 1, "spontaneous deferral"},
458 { 1UL << 2, "16-byte atomic ops" }
459 };
460 char family[32], features[128], *cp, sep;
461 struct cpuinfo_ia64 *c = v;
462 unsigned long mask;
463 int i;
465 mask = c->features;
467 switch (c->family) {
468 case 0x07: memcpy(family, "Itanium", 8); break;
469 case 0x1f: memcpy(family, "Itanium 2", 10); break;
470 default: sprintf(family, "%u", c->family); break;
471 }
473 /* build the feature string: */
474 memcpy(features, " standard", 10);
475 cp = features;
476 sep = 0;
477 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
478 if (mask & feature_bits[i].mask) {
479 if (sep)
480 *cp++ = sep;
481 sep = ',';
482 *cp++ = ' ';
483 strcpy(cp, feature_bits[i].feature_name);
484 cp += strlen(feature_bits[i].feature_name);
485 mask &= ~feature_bits[i].mask;
486 }
487 }
488 if (mask) {
489 /* print unknown features as a hex value: */
490 if (sep)
491 *cp++ = sep;
492 sprintf(cp, " 0x%lx", mask);
493 }
495 seq_printf(m,
496 "processor : %d\n"
497 "vendor : %s\n"
498 "arch : IA-64\n"
499 "family : %s\n"
500 "model : %u\n"
501 "revision : %u\n"
502 "archrev : %u\n"
503 "features :%s\n" /* don't change this---it _is_ right! */
504 "cpu number : %lu\n"
505 "cpu regs : %u\n"
506 "cpu MHz : %lu.%06lu\n"
507 "itc MHz : %lu.%06lu\n"
508 "BogoMIPS : %lu.%02lu\n\n",
509 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
510 features, c->ppn, c->number,
511 c->proc_freq / 1000000, c->proc_freq % 1000000,
512 c->itc_freq / 1000000, c->itc_freq % 1000000,
513 lpj*HZ/500000, (lpj*HZ/5000) % 100);
514 return 0;
515 }
517 static void *
518 c_start (struct seq_file *m, loff_t *pos)
519 {
520 #ifdef CONFIG_SMP
521 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
522 ++*pos;
523 #endif
524 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
525 }
527 static void *
528 c_next (struct seq_file *m, void *v, loff_t *pos)
529 {
530 ++*pos;
531 return c_start(m, pos);
532 }
534 static void
535 c_stop (struct seq_file *m, void *v)
536 {
537 }
539 #ifndef XEN
540 struct seq_operations cpuinfo_op = {
541 .start = c_start,
542 .next = c_next,
543 .stop = c_stop,
544 .show = show_cpuinfo
545 };
546 #endif
548 void
549 identify_cpu (struct cpuinfo_ia64 *c)
550 {
551 union {
552 unsigned long bits[5];
553 struct {
554 /* id 0 & 1: */
555 char vendor[16];
557 /* id 2 */
558 u64 ppn; /* processor serial number */
560 /* id 3: */
561 unsigned number : 8;
562 unsigned revision : 8;
563 unsigned model : 8;
564 unsigned family : 8;
565 unsigned archrev : 8;
566 unsigned reserved : 24;
568 /* id 4: */
569 u64 features;
570 } field;
571 } cpuid;
572 pal_vm_info_1_u_t vm1;
573 pal_vm_info_2_u_t vm2;
574 pal_status_t status;
575 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
576 int i;
578 for (i = 0; i < 5; ++i)
579 cpuid.bits[i] = ia64_get_cpuid(i);
581 memcpy(c->vendor, cpuid.field.vendor, 16);
582 #ifdef CONFIG_SMP
583 c->cpu = smp_processor_id();
584 #endif
585 c->ppn = cpuid.field.ppn;
586 c->number = cpuid.field.number;
587 c->revision = cpuid.field.revision;
588 c->model = cpuid.field.model;
589 c->family = cpuid.field.family;
590 c->archrev = cpuid.field.archrev;
591 c->features = cpuid.field.features;
593 status = ia64_pal_vm_summary(&vm1, &vm2);
594 if (status == PAL_STATUS_SUCCESS) {
595 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
596 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
597 }
598 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
599 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
601 #ifdef XEN
602 /* If vmx feature is on, do necessary initialization for vmx */
603 if (vmx_enabled)
604 vmx_init_env();
605 #endif
606 }
608 void
609 setup_per_cpu_areas (void)
610 {
611 /* start_kernel() requires this... */
612 }
614 static void
615 get_max_cacheline_size (void)
616 {
617 unsigned long line_size, max = 1;
618 u64 l, levels, unique_caches;
619 pal_cache_config_info_t cci;
620 s64 status;
622 status = ia64_pal_cache_summary(&levels, &unique_caches);
623 if (status != 0) {
624 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
625 __FUNCTION__, status);
626 max = SMP_CACHE_BYTES;
627 goto out;
628 }
630 for (l = 0; l < levels; ++l) {
631 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
632 &cci);
633 if (status != 0) {
634 printk(KERN_ERR
635 "%s: ia64_pal_cache_config_info(l=%lu) failed (status=%ld)\n",
636 __FUNCTION__, l, status);
637 max = SMP_CACHE_BYTES;
638 }
639 line_size = 1 << cci.pcci_line_size;
640 if (line_size > max)
641 max = line_size;
642 }
643 out:
644 if (max > ia64_max_cacheline_size)
645 ia64_max_cacheline_size = max;
646 }
648 /*
649 * cpu_init() initializes state that is per-CPU. This function acts
650 * as a 'CPU state barrier', nothing should get across.
651 */
652 void
653 cpu_init (void)
654 {
655 extern void __devinit ia64_mmu_init (void *);
656 unsigned long num_phys_stacked;
657 pal_vm_info_2_u_t vmi;
658 unsigned int max_ctx;
659 struct cpuinfo_ia64 *cpu_info;
660 void *cpu_data;
662 cpu_data = per_cpu_init();
664 /*
665 * We set ar.k3 so that assembly code in MCA handler can compute
666 * physical addresses of per cpu variables with a simple:
667 * phys = ar.k3 + &per_cpu_var
668 */
669 ia64_set_kr(IA64_KR_PER_CPU_DATA,
670 ia64_tpa(cpu_data) - (long) __per_cpu_start);
672 get_max_cacheline_size();
674 /*
675 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
676 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
677 * depends on the data returned by identify_cpu(). We break the dependency by
678 * accessing cpu_data() through the canonical per-CPU address.
679 */
680 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
681 identify_cpu(cpu_info);
683 #ifdef CONFIG_MCKINLEY
684 {
685 # define FEATURE_SET 16
686 struct ia64_pal_retval iprv;
688 if (cpu_info->family == 0x1f) {
689 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
690 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
691 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
692 (iprv.v1 | 0x80), FEATURE_SET, 0);
693 }
694 }
695 #endif
697 /* Clear the stack memory reserved for pt_regs: */
698 memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
700 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
702 /*
703 * Initialize default control register to defer all speculative faults. The
704 * kernel MUST NOT depend on a particular setting of these bits (in other words,
705 * the kernel must have recovery code for all speculative accesses). Turn on
706 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
707 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
708 * be fine).
709 */
710 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
711 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
712 atomic_inc(&init_mm.mm_count);
713 current->active_mm = &init_mm;
714 #ifdef XEN
715 if (current->domain->arch.mm)
716 #else
717 if (current->mm)
718 #endif
719 BUG();
721 ia64_mmu_init(ia64_imva(cpu_data));
722 ia64_mca_cpu_init(ia64_imva(cpu_data));
724 #ifdef CONFIG_IA32_SUPPORT
725 ia32_cpu_init();
726 #endif
728 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
729 ia64_set_itc(0);
731 /* disable all local interrupt sources: */
732 ia64_set_itv(1 << 16);
733 ia64_set_lrr0(1 << 16);
734 ia64_set_lrr1(1 << 16);
735 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
736 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
738 /* clear TPR & XTP to enable all interrupt classes: */
739 ia64_setreg(_IA64_REG_CR_TPR, 0);
740 #ifdef CONFIG_SMP
741 normal_xtp();
742 #endif
744 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
745 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
746 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
747 else {
748 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
749 max_ctx = (1U << 15) - 1; /* use architected minimum */
750 }
751 while (max_ctx < ia64_ctx.max_ctx) {
752 unsigned int old = ia64_ctx.max_ctx;
753 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
754 break;
755 }
757 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
758 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
759 "stacked regs\n");
760 num_phys_stacked = 96;
761 }
762 /* size of physical stacked register partition plus 8 bytes: */
763 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
764 platform_cpu_init();
765 }
767 void
768 check_bugs (void)
769 {
770 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
771 (unsigned long) __end___mckinley_e9_bundles);
772 }