ia64/xen-unstable

view tools/ioemu/hw/pass-through.c @ 18404:5d30ca2b2efd

ioemu, passthru: make upper field of 64 bit bar writable.

Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Aug 28 09:58:01 2008 +0100 (2008-08-28)
parents 0cf244daf3c4
children a5bf2535e7bb
line source
1 /*
2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 * Alex Novik <alex@neocleus.com>
19 * Allen Kay <allen.m.kay@intel.com>
20 * Guy Zana <guy@neocleus.com>
21 *
22 * This file implements direct PCI assignment to a HVM guest
23 */
25 #include "vl.h"
26 #include "pass-through.h"
27 #include "pci/header.h"
28 #include "pci/pci.h"
29 #include "pt-msi.h"
31 extern FILE *logfile;
33 struct php_dev {
34 struct pt_dev *pt_dev;
35 uint8_t valid;
36 uint8_t r_bus;
37 uint8_t r_dev;
38 uint8_t r_func;
39 };
40 struct dpci_infos {
42 struct php_dev php_devs[PHP_SLOT_LEN];
44 PCIBus *e_bus;
45 struct pci_access *pci_access;
47 } dpci_infos;
49 /* prototype */
50 static uint32_t pt_common_reg_init(struct pt_dev *ptdev,
51 struct pt_reg_info_tbl *reg, uint32_t real_offset);
52 static uint32_t pt_ptr_reg_init(struct pt_dev *ptdev,
53 struct pt_reg_info_tbl *reg, uint32_t real_offset);
54 static uint32_t pt_status_reg_init(struct pt_dev *ptdev,
55 struct pt_reg_info_tbl *reg, uint32_t real_offset);
56 static uint32_t pt_irqpin_reg_init(struct pt_dev *ptdev,
57 struct pt_reg_info_tbl *reg, uint32_t real_offset);
58 static uint32_t pt_bar_reg_init(struct pt_dev *ptdev,
59 struct pt_reg_info_tbl *reg, uint32_t real_offset);
60 static uint32_t pt_linkctrl2_reg_init(struct pt_dev *ptdev,
61 struct pt_reg_info_tbl *reg, uint32_t real_offset);
62 static uint32_t pt_msgctrl_reg_init(struct pt_dev *ptdev,
63 struct pt_reg_info_tbl *reg, uint32_t real_offset);
64 static uint32_t pt_msgaddr32_reg_init(struct pt_dev *ptdev,
65 struct pt_reg_info_tbl *reg, uint32_t real_offset);
66 static uint32_t pt_msgaddr64_reg_init(struct pt_dev *ptdev,
67 struct pt_reg_info_tbl *reg, uint32_t real_offset);
68 static uint32_t pt_msgdata_reg_init(struct pt_dev *ptdev,
69 struct pt_reg_info_tbl *reg, uint32_t real_offset);
70 static uint32_t pt_msixctrl_reg_init(struct pt_dev *ptdev,
71 struct pt_reg_info_tbl *reg, uint32_t real_offset);
72 static uint8_t pt_reg_grp_size_init(struct pt_dev *ptdev,
73 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset);
74 static uint8_t pt_msi_size_init(struct pt_dev *ptdev,
75 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset);
76 static uint8_t pt_msix_size_init(struct pt_dev *ptdev,
77 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset);
78 static uint8_t pt_vendor_size_init(struct pt_dev *ptdev,
79 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset);
80 static int pt_byte_reg_read(struct pt_dev *ptdev,
81 struct pt_reg_tbl *cfg_entry,
82 uint8_t *valueu, uint8_t valid_mask);
83 static int pt_word_reg_read(struct pt_dev *ptdev,
84 struct pt_reg_tbl *cfg_entry,
85 uint16_t *value, uint16_t valid_mask);
86 static int pt_long_reg_read(struct pt_dev *ptdev,
87 struct pt_reg_tbl *cfg_entry,
88 uint32_t *value, uint32_t valid_mask);
89 static int pt_bar_reg_read(struct pt_dev *ptdev,
90 struct pt_reg_tbl *cfg_entry,
91 uint32_t *value, uint32_t valid_mask);
92 static int pt_byte_reg_write(struct pt_dev *ptdev,
93 struct pt_reg_tbl *cfg_entry,
94 uint8_t *value, uint8_t dev_value, uint8_t valid_mask);
95 static int pt_word_reg_write(struct pt_dev *ptdev,
96 struct pt_reg_tbl *cfg_entry,
97 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
98 static int pt_long_reg_write(struct pt_dev *ptdev,
99 struct pt_reg_tbl *cfg_entry,
100 uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
101 static int pt_cmd_reg_write(struct pt_dev *ptdev,
102 struct pt_reg_tbl *cfg_entry,
103 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
104 static int pt_bar_reg_write(struct pt_dev *ptdev,
105 struct pt_reg_tbl *cfg_entry,
106 uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
107 static int pt_exp_rom_bar_reg_write(struct pt_dev *ptdev,
108 struct pt_reg_tbl *cfg_entry,
109 uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
110 static int pt_pmcsr_reg_write(struct pt_dev *ptdev,
111 struct pt_reg_tbl *cfg_entry,
112 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
113 static int pt_devctrl_reg_write(struct pt_dev *ptdev,
114 struct pt_reg_tbl *cfg_entry,
115 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
116 static int pt_linkctrl_reg_write(struct pt_dev *ptdev,
117 struct pt_reg_tbl *cfg_entry,
118 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
119 static int pt_devctrl2_reg_write(struct pt_dev *ptdev,
120 struct pt_reg_tbl *cfg_entry,
121 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
122 static int pt_linkctrl2_reg_write(struct pt_dev *ptdev,
123 struct pt_reg_tbl *cfg_entry,
124 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
125 static int pt_msgctrl_reg_write(struct pt_dev *ptdev,
126 struct pt_reg_tbl *cfg_entry,
127 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
128 static int pt_msgaddr32_reg_write(struct pt_dev *ptdev,
129 struct pt_reg_tbl *cfg_entry,
130 uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
131 static int pt_msgaddr64_reg_write(struct pt_dev *ptdev,
132 struct pt_reg_tbl *cfg_entry,
133 uint32_t *value, uint32_t dev_value, uint32_t valid_mask);
134 static int pt_msgdata_reg_write(struct pt_dev *ptdev,
135 struct pt_reg_tbl *cfg_entry,
136 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
137 static int pt_msixctrl_reg_write(struct pt_dev *ptdev,
138 struct pt_reg_tbl *cfg_entry,
139 uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
141 /* pt_reg_info_tbl declaration
142 * - only for emulated register (either a part or whole bit).
143 * - for passthrough register that need special behavior (like interacting with
144 * other component), set emu_mask to all 0 and specify r/w func properly.
145 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
146 */
148 /* Header Type0 reg static infomation table */
149 static struct pt_reg_info_tbl pt_emu_reg_header0_tbl[] = {
150 /* Command reg */
151 {
152 .offset = PCI_COMMAND,
153 .size = 2,
154 .init_val = 0x0000,
155 .ro_mask = 0xF880,
156 .emu_mask = 0x0340,
157 .init = pt_common_reg_init,
158 .u.w.read = pt_word_reg_read,
159 .u.w.write = pt_cmd_reg_write,
160 },
161 /* Capabilities Pointer reg */
162 {
163 .offset = PCI_CAPABILITY_LIST,
164 .size = 1,
165 .init_val = 0x00,
166 .ro_mask = 0xFF,
167 .emu_mask = 0xFF,
168 .init = pt_ptr_reg_init,
169 .u.b.read = pt_byte_reg_read,
170 .u.b.write = pt_byte_reg_write,
171 },
172 /* Status reg */
173 /* use emulated Cap Ptr value to initialize,
174 * so need to be declared after Cap Ptr reg
175 */
176 {
177 .offset = PCI_STATUS,
178 .size = 2,
179 .init_val = 0x0000,
180 .ro_mask = 0x06FF,
181 .emu_mask = 0x0010,
182 .init = pt_status_reg_init,
183 .u.w.read = pt_word_reg_read,
184 .u.w.write = pt_word_reg_write,
185 },
186 /* Cache Line Size reg */
187 {
188 .offset = PCI_CACHE_LINE_SIZE,
189 .size = 1,
190 .init_val = 0x00,
191 .ro_mask = 0x00,
192 .emu_mask = 0xFF,
193 .init = pt_common_reg_init,
194 .u.b.read = pt_byte_reg_read,
195 .u.b.write = pt_byte_reg_write,
196 },
197 /* Latency Timer reg */
198 {
199 .offset = PCI_LATENCY_TIMER,
200 .size = 1,
201 .init_val = 0x00,
202 .ro_mask = 0x00,
203 .emu_mask = 0xFF,
204 .init = pt_common_reg_init,
205 .u.b.read = pt_byte_reg_read,
206 .u.b.write = pt_byte_reg_write,
207 },
208 /* Header Type reg */
209 {
210 .offset = PCI_HEADER_TYPE,
211 .size = 1,
212 .init_val = 0x00,
213 .ro_mask = 0xFF,
214 .emu_mask = 0x80,
215 .init = pt_common_reg_init,
216 .u.b.read = pt_byte_reg_read,
217 .u.b.write = pt_byte_reg_write,
218 },
219 /* Interrupt Line reg */
220 {
221 .offset = PCI_INTERRUPT_LINE,
222 .size = 1,
223 .init_val = 0x00,
224 .ro_mask = 0x00,
225 .emu_mask = 0xFF,
226 .init = pt_common_reg_init,
227 .u.b.read = pt_byte_reg_read,
228 .u.b.write = pt_byte_reg_write,
229 },
230 /* Interrupt Pin reg */
231 {
232 .offset = PCI_INTERRUPT_PIN,
233 .size = 1,
234 .init_val = 0x00,
235 .ro_mask = 0xFF,
236 .emu_mask = 0xFF,
237 .init = pt_irqpin_reg_init,
238 .u.b.read = pt_byte_reg_read,
239 .u.b.write = pt_byte_reg_write,
240 },
241 /* BAR 0 reg */
242 /* mask of BAR need to be decided later, depends on IO/MEM type */
243 {
244 .offset = PCI_BASE_ADDRESS_0,
245 .size = 4,
246 .init_val = 0x00000000,
247 .init = pt_bar_reg_init,
248 .u.dw.read = pt_bar_reg_read,
249 .u.dw.write = pt_bar_reg_write,
250 },
251 /* BAR 1 reg */
252 {
253 .offset = PCI_BASE_ADDRESS_1,
254 .size = 4,
255 .init_val = 0x00000000,
256 .init = pt_bar_reg_init,
257 .u.dw.read = pt_bar_reg_read,
258 .u.dw.write = pt_bar_reg_write,
259 },
260 /* BAR 2 reg */
261 {
262 .offset = PCI_BASE_ADDRESS_2,
263 .size = 4,
264 .init_val = 0x00000000,
265 .init = pt_bar_reg_init,
266 .u.dw.read = pt_bar_reg_read,
267 .u.dw.write = pt_bar_reg_write,
268 },
269 /* BAR 3 reg */
270 {
271 .offset = PCI_BASE_ADDRESS_3,
272 .size = 4,
273 .init_val = 0x00000000,
274 .init = pt_bar_reg_init,
275 .u.dw.read = pt_bar_reg_read,
276 .u.dw.write = pt_bar_reg_write,
277 },
278 /* BAR 4 reg */
279 {
280 .offset = PCI_BASE_ADDRESS_4,
281 .size = 4,
282 .init_val = 0x00000000,
283 .init = pt_bar_reg_init,
284 .u.dw.read = pt_bar_reg_read,
285 .u.dw.write = pt_bar_reg_write,
286 },
287 /* BAR 5 reg */
288 {
289 .offset = PCI_BASE_ADDRESS_5,
290 .size = 4,
291 .init_val = 0x00000000,
292 .init = pt_bar_reg_init,
293 .u.dw.read = pt_bar_reg_read,
294 .u.dw.write = pt_bar_reg_write,
295 },
296 /* Expansion ROM BAR reg */
297 {
298 .offset = PCI_ROM_ADDRESS,
299 .size = 4,
300 .init_val = 0x00000000,
301 .ro_mask = 0x000007FE,
302 .emu_mask = 0xFFFFF800,
303 .init = pt_bar_reg_init,
304 .u.dw.read = pt_long_reg_read,
305 .u.dw.write = pt_exp_rom_bar_reg_write,
306 },
307 {
308 .size = 0,
309 },
310 };
312 /* Power Management Capability reg static infomation table */
313 static struct pt_reg_info_tbl pt_emu_reg_pm_tbl[] = {
314 /* Next Pointer reg */
315 {
316 .offset = PCI_CAP_LIST_NEXT,
317 .size = 1,
318 .init_val = 0x00,
319 .ro_mask = 0xFF,
320 .emu_mask = 0xFF,
321 .init = pt_ptr_reg_init,
322 .u.b.read = pt_byte_reg_read,
323 .u.b.write = pt_byte_reg_write,
324 },
325 /* Power Management Capabilities reg */
326 {
327 .offset = PCI_CAP_FLAGS,
328 .size = 2,
329 .init_val = 0x0000,
330 .ro_mask = 0xFFFF,
331 .emu_mask = 0xFFE8,
332 .init = pt_common_reg_init,
333 .u.w.read = pt_word_reg_read,
334 .u.w.write = pt_word_reg_write,
335 },
336 /* PCI Power Management Control/Status reg */
337 {
338 .offset = PCI_PM_CTRL,
339 .size = 2,
340 .init_val = 0x0008,
341 .ro_mask = 0x60FC,
342 .emu_mask = 0xFF0B,
343 .init = pt_common_reg_init,
344 .u.w.read = pt_word_reg_read,
345 .u.w.write = pt_pmcsr_reg_write,
346 },
347 /* Data reg */
348 {
349 .offset = PCI_PM_DATA_REGISTER,
350 .size = 1,
351 .init_val = 0x00,
352 .ro_mask = 0xFF,
353 .emu_mask = 0xFF,
354 .init = pt_common_reg_init,
355 .u.b.read = pt_byte_reg_read,
356 .u.b.write = pt_byte_reg_write,
357 },
358 {
359 .size = 0,
360 },
361 };
363 /* Vital Product Data Capability Structure reg static infomation table */
364 static struct pt_reg_info_tbl pt_emu_reg_vpd_tbl[] = {
365 /* Next Pointer reg */
366 {
367 .offset = PCI_CAP_LIST_NEXT,
368 .size = 1,
369 .init_val = 0x00,
370 .ro_mask = 0xFF,
371 .emu_mask = 0xFF,
372 .init = pt_ptr_reg_init,
373 .u.b.read = pt_byte_reg_read,
374 .u.b.write = pt_byte_reg_write,
375 },
376 {
377 .size = 0,
378 },
379 };
381 /* Vendor Specific Capability Structure reg static infomation table */
382 static struct pt_reg_info_tbl pt_emu_reg_vendor_tbl[] = {
383 /* Next Pointer reg */
384 {
385 .offset = PCI_CAP_LIST_NEXT,
386 .size = 1,
387 .init_val = 0x00,
388 .ro_mask = 0xFF,
389 .emu_mask = 0xFF,
390 .init = pt_ptr_reg_init,
391 .u.b.read = pt_byte_reg_read,
392 .u.b.write = pt_byte_reg_write,
393 },
394 {
395 .size = 0,
396 },
397 };
399 /* PCI Express Capability Structure reg static infomation table */
400 static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = {
401 /* Next Pointer reg */
402 {
403 .offset = PCI_CAP_LIST_NEXT,
404 .size = 1,
405 .init_val = 0x00,
406 .ro_mask = 0xFF,
407 .emu_mask = 0xFF,
408 .init = pt_ptr_reg_init,
409 .u.b.read = pt_byte_reg_read,
410 .u.b.write = pt_byte_reg_write,
411 },
412 /* Device Capabilities reg */
413 {
414 .offset = PCI_EXP_DEVCAP,
415 .size = 4,
416 .init_val = 0x00000000,
417 .ro_mask = 0x1FFCFFFF,
418 .emu_mask = 0x10000000,
419 .init = pt_common_reg_init,
420 .u.dw.read = pt_long_reg_read,
421 .u.dw.write = pt_long_reg_write,
422 },
423 /* Device Control reg */
424 {
425 .offset = PCI_EXP_DEVCTL,
426 .size = 2,
427 .init_val = 0x2810,
428 .ro_mask = 0x0000,
429 .emu_mask = 0xFFFF,
430 .init = pt_common_reg_init,
431 .u.w.read = pt_word_reg_read,
432 .u.w.write = pt_devctrl_reg_write,
433 },
434 /* Link Control reg */
435 {
436 .offset = PCI_EXP_LNKCTL,
437 .size = 2,
438 .init_val = 0x0000,
439 .ro_mask = 0x0000,
440 .emu_mask = 0xFFFF,
441 .init = pt_common_reg_init,
442 .u.w.read = pt_word_reg_read,
443 .u.w.write = pt_linkctrl_reg_write,
444 },
445 /* Device Control 2 reg */
446 {
447 .offset = 0x28,
448 .size = 2,
449 .init_val = 0x0000,
450 .ro_mask = 0x0000,
451 .emu_mask = 0xFFFF,
452 .init = pt_common_reg_init,
453 .u.w.read = pt_word_reg_read,
454 .u.w.write = pt_devctrl2_reg_write,
455 },
456 /* Link Control 2 reg */
457 {
458 .offset = 0x30,
459 .size = 2,
460 .init_val = 0x0000,
461 .ro_mask = 0x0000,
462 .emu_mask = 0xFFFF,
463 .init = pt_linkctrl2_reg_init,
464 .u.w.read = pt_word_reg_read,
465 .u.w.write = pt_linkctrl2_reg_write,
466 },
467 {
468 .size = 0,
469 },
470 };
472 /* MSI Capability Structure reg static infomation table */
473 static struct pt_reg_info_tbl pt_emu_reg_msi_tbl[] = {
474 /* Next Pointer reg */
475 {
476 .offset = PCI_CAP_LIST_NEXT,
477 .size = 1,
478 .init_val = 0x00,
479 .ro_mask = 0xFF,
480 .emu_mask = 0xFF,
481 .init = pt_ptr_reg_init,
482 .u.b.read = pt_byte_reg_read,
483 .u.b.write = pt_byte_reg_write,
484 },
485 /* Message Control reg */
486 {
487 .offset = PCI_MSI_FLAGS, // 2
488 .size = 2,
489 .init_val = 0x0000,
490 .ro_mask = 0x018E,
491 .emu_mask = 0xFFFE,
492 .init = pt_msgctrl_reg_init,
493 .u.w.read = pt_word_reg_read,
494 .u.w.write = pt_msgctrl_reg_write,
495 },
496 /* Message Address reg */
497 {
498 .offset = PCI_MSI_ADDRESS_LO, // 4
499 .size = 4,
500 .init_val = 0x00000000,
501 .ro_mask = 0x00000FF0, /* bit 4~11 is reserved for MSI in x86 */
502 .emu_mask = 0xFFFFFFFF,
503 .init = pt_msgaddr32_reg_init,
504 .u.dw.read = pt_long_reg_read,
505 .u.dw.write = pt_msgaddr32_reg_write,
506 },
507 /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */
508 {
509 .offset = PCI_MSI_ADDRESS_HI, // 8
510 .size = 4,
511 .init_val = 0x00000000,
512 .ro_mask = 0x00000000,
513 .emu_mask = 0xFFFFFFFF,
514 .init = pt_msgaddr64_reg_init,
515 .u.dw.read = pt_long_reg_read,
516 .u.dw.write = pt_msgaddr64_reg_write,
517 },
518 /* Message Data reg (16 bits of data for 32-bit devices) */
519 {
520 .offset = PCI_MSI_DATA_32, // 8
521 .size = 2,
522 .init_val = 0x0000,
523 .ro_mask = 0x3800,
524 .emu_mask = 0xFFFF,
525 .init = pt_msgdata_reg_init,
526 .u.w.read = pt_word_reg_read,
527 .u.w.write = pt_msgdata_reg_write,
528 },
529 /* Message Data reg (16 bits of data for 64-bit devices) */
530 {
531 .offset = PCI_MSI_DATA_64, // 12
532 .size = 2,
533 .init_val = 0x0000,
534 .ro_mask = 0x3800,
535 .emu_mask = 0xFFFF,
536 .init = pt_msgdata_reg_init,
537 .u.w.read = pt_word_reg_read,
538 .u.w.write = pt_msgdata_reg_write,
539 },
540 {
541 .size = 0,
542 },
543 };
545 /* MSI-X Capability Structure reg static infomation table */
546 static struct pt_reg_info_tbl pt_emu_reg_msix_tbl[] = {
547 /* Next Pointer reg */
548 {
549 .offset = PCI_CAP_LIST_NEXT,
550 .size = 1,
551 .init_val = 0x00,
552 .ro_mask = 0xFF,
553 .emu_mask = 0xFF,
554 .init = pt_ptr_reg_init,
555 .u.b.read = pt_byte_reg_read,
556 .u.b.write = pt_byte_reg_write,
557 },
558 /* Message Control reg */
559 {
560 .offset = PCI_MSI_FLAGS, // 2
561 .size = 2,
562 .init_val = 0x0000,
563 .ro_mask = 0x3FFF,
564 .emu_mask = 0x0000,
565 .init = pt_msixctrl_reg_init,
566 .u.w.read = pt_word_reg_read,
567 .u.w.write = pt_msixctrl_reg_write,
568 },
569 {
570 .size = 0,
571 },
572 };
574 /* pt_reg_grp_info_tbl declaration
575 * - only for emulated or zero-hardwired register group.
576 * - for register group with dynamic size, just set grp_size to 0xFF and
577 * specify size_init func properly.
578 * - no need to specify emu_reg_tbl for zero-hardwired type.
579 */
581 /* emul reg group static infomation table */
582 static const struct pt_reg_grp_info_tbl pt_emu_reg_grp_tbl[] = {
583 /* Header Type0 reg group */
584 {
585 .grp_id = 0xFF,
586 .grp_type = GRP_TYPE_EMU,
587 .grp_size = 0x40,
588 .size_init = pt_reg_grp_size_init,
589 .emu_reg_tbl= pt_emu_reg_header0_tbl,
590 },
591 /* PCI PowerManagement Capability reg group */
592 {
593 .grp_id = PCI_CAP_ID_PM,
594 .grp_type = GRP_TYPE_EMU,
595 .grp_size = PCI_PM_SIZEOF,
596 .size_init = pt_reg_grp_size_init,
597 .emu_reg_tbl= pt_emu_reg_pm_tbl,
598 },
599 /* AGP Capability Structure reg group */
600 {
601 .grp_id = PCI_CAP_ID_AGP,
602 .grp_type = GRP_TYPE_HARDWIRED,
603 .grp_size = 0x30,
604 .size_init = pt_reg_grp_size_init,
605 },
606 /* Vital Product Data Capability Structure reg group */
607 {
608 .grp_id = PCI_CAP_ID_VPD,
609 .grp_type = GRP_TYPE_EMU,
610 .grp_size = 0x08,
611 .size_init = pt_reg_grp_size_init,
612 .emu_reg_tbl= pt_emu_reg_vpd_tbl,
613 },
614 /* Slot Identification reg group */
615 {
616 .grp_id = PCI_CAP_ID_SLOTID,
617 .grp_type = GRP_TYPE_HARDWIRED,
618 .grp_size = 0x04,
619 .size_init = pt_reg_grp_size_init,
620 },
621 /* MSI Capability Structure reg group */
622 {
623 .grp_id = PCI_CAP_ID_MSI,
624 .grp_type = GRP_TYPE_EMU,
625 .grp_size = 0xFF,
626 .size_init = pt_msi_size_init,
627 .emu_reg_tbl= pt_emu_reg_msi_tbl,
628 },
629 /* PCI-X Capabilities List Item reg group */
630 {
631 .grp_id = PCI_CAP_ID_PCIX,
632 .grp_type = GRP_TYPE_HARDWIRED,
633 .grp_size = 0x18,
634 .size_init = pt_reg_grp_size_init,
635 },
636 /* Vendor Specific Capability Structure reg group */
637 {
638 .grp_id = PCI_CAP_ID_VNDR,
639 .grp_type = GRP_TYPE_EMU,
640 .grp_size = 0xFF,
641 .size_init = pt_vendor_size_init,
642 .emu_reg_tbl= pt_emu_reg_vendor_tbl,
643 },
644 /* SHPC Capability List Item reg group */
645 {
646 .grp_id = PCI_CAP_ID_HOTPLUG,
647 .grp_type = GRP_TYPE_HARDWIRED,
648 .grp_size = 0x08,
649 .size_init = pt_reg_grp_size_init,
650 },
651 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
652 {
653 .grp_id = PCI_CAP_ID_SSVID,
654 .grp_type = GRP_TYPE_HARDWIRED,
655 .grp_size = 0x08,
656 .size_init = pt_reg_grp_size_init,
657 },
658 /* AGP 8x Capability Structure reg group */
659 {
660 .grp_id = PCI_CAP_ID_AGP3,
661 .grp_type = GRP_TYPE_HARDWIRED,
662 .grp_size = 0x30,
663 .size_init = pt_reg_grp_size_init,
664 },
665 /* PCI Express Capability Structure reg group */
666 {
667 .grp_id = PCI_CAP_ID_EXP,
668 .grp_type = GRP_TYPE_EMU,
669 .grp_size = 0x3C,
670 .size_init = pt_reg_grp_size_init,
671 .emu_reg_tbl= pt_emu_reg_pcie_tbl,
672 },
673 /* MSI-X Capability Structure reg group */
674 {
675 .grp_id = PCI_CAP_ID_MSIX,
676 .grp_type = GRP_TYPE_EMU,
677 .grp_size = 0x0C,
678 .size_init = pt_msix_size_init,
679 .emu_reg_tbl= pt_emu_reg_msix_tbl,
680 },
681 {
682 .grp_size = 0,
683 },
684 };
686 static int token_value(char *token)
687 {
688 return strtol(token, NULL, 16);
689 }
691 static int next_bdf(char **str, int *seg, int *bus, int *dev, int *func)
692 {
693 char *token, *delim = ":.-";
695 if ( !(*str) ||
696 ( !strchr(*str, ':') && !strchr(*str, '.')) )
697 return 0;
699 token = strsep(str, delim);
700 *seg = token_value(token);
702 token = strsep(str, delim);
703 *bus = token_value(token);
705 token = strsep(str, delim);
706 *dev = token_value(token);
708 token = strsep(str, delim);
709 *func = token_value(token);
711 return 1;
712 }
714 /* Insert a new pass-through device into a specific pci slot.
715 * input dom:bus:dev.func@slot, chose free one if slot == 0
716 * return -1: required slot not available
717 * 0: no free hotplug slots, but normal slot should okay
718 * >0: the new hotplug slot
719 */
720 static int __insert_to_pci_slot(int bus, int dev, int func, int slot)
721 {
722 int i, php_slot;
724 /* preferred virt pci slot */
725 if ( slot >= PHP_SLOT_START && slot < PHP_SLOT_END )
726 {
727 php_slot = PCI_TO_PHP_SLOT(slot);
728 if ( !dpci_infos.php_devs[php_slot].valid )
729 {
730 goto found;
731 }
732 else
733 return -1;
734 }
736 if ( slot != 0 )
737 return -1;
739 /* slot == 0, pick up a free one */
740 for ( i = 0; i < PHP_SLOT_LEN; i++ )
741 {
742 if ( !dpci_infos.php_devs[i].valid )
743 {
744 php_slot = i;
745 goto found;
746 }
747 }
749 /* not found */
750 return 0;
752 found:
753 dpci_infos.php_devs[php_slot].valid = 1;
754 dpci_infos.php_devs[php_slot].r_bus = bus;
755 dpci_infos.php_devs[php_slot].r_dev = dev;
756 dpci_infos.php_devs[php_slot].r_func = func;
757 return PHP_TO_PCI_SLOT(php_slot);
758 }
760 /* Insert a new pass-through device into a specific pci slot.
761 * input dom:bus:dev.func@slot
762 */
763 int insert_to_pci_slot(char *bdf_slt)
764 {
765 int seg, bus, dev, func, slot;
766 char *bdf_str, *slt_str, *delim="@";
768 bdf_str = strsep(&bdf_slt, delim);
769 slt_str = bdf_slt;
770 slot = token_value(slt_str);
772 if ( !next_bdf(&bdf_str, &seg, &bus, &dev, &func))
773 {
774 return -1;
775 }
777 return __insert_to_pci_slot(bus, dev, func, slot);
779 }
781 /* Test if a pci slot has a device
782 * 1: present
783 * 0: not present
784 * -1: invalide pci slot input
785 */
786 int test_pci_slot(int slot)
787 {
788 int php_slot;
790 if ( slot < PHP_SLOT_START || slot >= PHP_SLOT_END )
791 return -1;
793 php_slot = PCI_TO_PHP_SLOT(slot);
794 if ( dpci_infos.php_devs[php_slot].valid )
795 return 1;
796 else
797 return 0;
798 }
800 /* find the pci slot for pass-through dev with specified BDF */
801 int bdf_to_slot(char *bdf_str)
802 {
803 int seg, bus, dev, func, i;
805 if ( !next_bdf(&bdf_str, &seg, &bus, &dev, &func))
806 {
807 return -1;
808 }
810 /* locate the virtual pci slot for this VTd device */
811 for ( i = 0; i < PHP_SLOT_LEN; i++ )
812 {
813 if ( dpci_infos.php_devs[i].valid &&
814 dpci_infos.php_devs[i].r_bus == bus &&
815 dpci_infos.php_devs[i].r_dev == dev &&
816 dpci_infos.php_devs[i].r_func == func )
817 {
818 return PHP_TO_PCI_SLOT(i);
819 }
820 }
822 return -1;
823 }
825 /* Being called each time a mmio region has been updated */
826 void pt_iomem_map(PCIDevice *d, int i, uint32_t e_phys, uint32_t e_size,
827 int type)
828 {
829 struct pt_dev *assigned_device = (struct pt_dev *)d;
830 uint32_t old_ebase = assigned_device->bases[i].e_physbase;
831 int first_map = ( assigned_device->bases[i].e_size == 0 );
832 int ret = 0;
834 assigned_device->bases[i].e_physbase = e_phys;
835 assigned_device->bases[i].e_size= e_size;
837 PT_LOG("e_phys=%08x maddr=%lx type=%d len=%d index=%d first_map=%d\n",
838 e_phys, (unsigned long)assigned_device->bases[i].access.maddr,
839 type, e_size, i, first_map);
841 if ( e_size == 0 )
842 return;
844 if ( !first_map && old_ebase != -1 )
845 {
846 add_msix_mapping(assigned_device, i);
847 /* Remove old mapping */
848 ret = xc_domain_memory_mapping(xc_handle, domid,
849 old_ebase >> XC_PAGE_SHIFT,
850 assigned_device->bases[i].access.maddr >> XC_PAGE_SHIFT,
851 (e_size+XC_PAGE_SIZE-1) >> XC_PAGE_SHIFT,
852 DPCI_REMOVE_MAPPING);
853 if ( ret != 0 )
854 {
855 PT_LOG("Error: remove old mapping failed!\n");
856 return;
857 }
858 }
860 /* map only valid guest address */
861 if (e_phys != -1)
862 {
863 /* Create new mapping */
864 ret = xc_domain_memory_mapping(xc_handle, domid,
865 assigned_device->bases[i].e_physbase >> XC_PAGE_SHIFT,
866 assigned_device->bases[i].access.maddr >> XC_PAGE_SHIFT,
867 (e_size+XC_PAGE_SIZE-1) >> XC_PAGE_SHIFT,
868 DPCI_ADD_MAPPING);
870 if ( ret != 0 )
871 {
872 PT_LOG("Error: create new mapping failed!\n");
873 }
875 ret = remove_msix_mapping(assigned_device, i);
876 if ( ret != 0 )
877 PT_LOG("Error: remove MSI-X mmio mapping failed!\n");
878 }
879 }
881 /* Being called each time a pio region has been updated */
882 void pt_ioport_map(PCIDevice *d, int i,
883 uint32_t e_phys, uint32_t e_size, int type)
884 {
885 struct pt_dev *assigned_device = (struct pt_dev *)d;
886 uint32_t old_ebase = assigned_device->bases[i].e_physbase;
887 int first_map = ( assigned_device->bases[i].e_size == 0 );
888 int ret = 0;
890 assigned_device->bases[i].e_physbase = e_phys;
891 assigned_device->bases[i].e_size= e_size;
893 PT_LOG("e_phys=%04x pio_base=%04x len=%d index=%d first_map=%d\n",
894 (uint16_t)e_phys, (uint16_t)assigned_device->bases[i].access.pio_base,
895 (uint16_t)e_size, i, first_map);
897 if ( e_size == 0 )
898 return;
900 if ( !first_map && old_ebase != -1 )
901 {
902 /* Remove old mapping */
903 ret = xc_domain_ioport_mapping(xc_handle, domid, old_ebase,
904 assigned_device->bases[i].access.pio_base, e_size,
905 DPCI_REMOVE_MAPPING);
906 if ( ret != 0 )
907 {
908 PT_LOG("Error: remove old mapping failed!\n");
909 return;
910 }
911 }
913 /* map only valid guest address (include 0) */
914 if (e_phys != -1)
915 {
916 /* Create new mapping */
917 ret = xc_domain_ioport_mapping(xc_handle, domid, e_phys,
918 assigned_device->bases[i].access.pio_base, e_size,
919 DPCI_ADD_MAPPING);
920 if ( ret != 0 )
921 {
922 PT_LOG("Error: create new mapping failed!\n");
923 }
924 }
925 }
927 /* find emulate register group entry */
928 struct pt_reg_grp_tbl* pt_find_reg_grp(
929 struct pt_dev *ptdev, uint32_t address)
930 {
931 struct pt_reg_grp_tbl* reg_grp_entry = NULL;
933 /* find register group entry */
934 for (reg_grp_entry = ptdev->reg_grp_tbl_head.lh_first; reg_grp_entry;
935 reg_grp_entry = reg_grp_entry->entries.le_next)
936 {
937 /* check address */
938 if ((reg_grp_entry->base_offset <= address) &&
939 ((reg_grp_entry->base_offset + reg_grp_entry->size) > address))
940 goto out;
941 }
942 /* group entry not found */
943 reg_grp_entry = NULL;
945 out:
946 return reg_grp_entry;
947 }
949 /* find emulate register entry */
950 struct pt_reg_tbl* pt_find_reg(
951 struct pt_reg_grp_tbl* reg_grp, uint32_t address)
952 {
953 struct pt_reg_tbl* reg_entry = NULL;
954 struct pt_reg_info_tbl* reg = NULL;
955 uint32_t real_offset = 0;
957 /* find register entry */
958 for (reg_entry = reg_grp->reg_tbl_head.lh_first; reg_entry;
959 reg_entry = reg_entry->entries.le_next)
960 {
961 reg = reg_entry->reg;
962 real_offset = (reg_grp->base_offset + reg->offset);
963 /* check address */
964 if ((real_offset <= address) && ((real_offset + reg->size) > address))
965 goto out;
966 }
967 /* register entry not found */
968 reg_entry = NULL;
970 out:
971 return reg_entry;
972 }
974 /* get BAR index */
975 static int pt_bar_offset_to_index(uint32_t offset)
976 {
977 int index = 0;
979 /* check Exp ROM BAR */
980 if (offset == PCI_ROM_ADDRESS)
981 {
982 index = PCI_ROM_SLOT;
983 goto out;
984 }
986 /* calculate BAR index */
987 index = ((offset - PCI_BASE_ADDRESS_0) >> 2);
988 if (index >= PCI_NUM_REGIONS)
989 index = -1;
991 out:
992 return index;
993 }
995 static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val,
996 int len)
997 {
998 struct pt_dev *assigned_device = (struct pt_dev *)d;
999 struct pci_dev *pci_dev = assigned_device->pci_dev;
1000 struct pt_reg_grp_tbl *reg_grp_entry = NULL;
1001 struct pt_reg_grp_info_tbl *reg_grp = NULL;
1002 struct pt_reg_tbl *reg_entry = NULL;
1003 struct pt_reg_info_tbl *reg = NULL;
1004 uint32_t find_addr = address;
1005 uint32_t real_offset = 0;
1006 uint32_t valid_mask = 0xFFFFFFFF;
1007 uint32_t read_val = 0;
1008 uint8_t *ptr_val = NULL;
1009 int emul_len = 0;
1010 int index = 0;
1011 int ret = 0;
1013 #ifdef PT_DEBUG_PCI_CONFIG_ACCESS
1014 PT_LOG("[%02x:%02x.%x]: address=%04x val=0x%08x len=%d\n",
1015 pci_bus_num(d->bus), (d->devfn >> 3) & 0x1F, (d->devfn & 0x7),
1016 address, val, len);
1017 #endif
1019 /* check offset range */
1020 if (address >= 0xFF)
1022 PT_LOG("Failed to write register with offset exceeding FFh. "
1023 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1024 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1025 address, len);
1026 goto exit;
1029 /* check write size */
1030 if ((len != 1) && (len != 2) && (len != 4))
1032 PT_LOG("Failed to write register with invalid access length. "
1033 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1034 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1035 address, len);
1036 goto exit;
1039 /* check offset alignment */
1040 if (address & (len-1))
1042 PT_LOG("Failed to write register with invalid access size alignment. "
1043 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1044 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1045 address, len);
1046 goto exit;
1049 /* check unused BAR register */
1050 index = pt_bar_offset_to_index(address);
1051 if ((index >= 0) && (val > 0 && val < PT_BAR_ALLF) &&
1052 (assigned_device->bases[index].bar_flag == PT_BAR_FLAG_UNUSED))
1054 PT_LOG("Guest attempt to set address to unused Base Address Register. "
1055 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1056 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
1057 (d->devfn & 0x7), address, len);
1060 /* find register group entry */
1061 reg_grp_entry = pt_find_reg_grp(assigned_device, address);
1062 if (reg_grp_entry)
1064 reg_grp = reg_grp_entry->reg_grp;
1065 /* check 0 Hardwired register group */
1066 if (reg_grp->grp_type == GRP_TYPE_HARDWIRED)
1068 /* ignore silently */
1069 PT_LOG("Access to 0 Hardwired register. "
1070 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1071 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
1072 (d->devfn & 0x7), address, len);
1073 goto exit;
1077 /* read I/O device register value */
1078 switch (len) {
1079 case 1:
1080 read_val = pci_read_byte(pci_dev, address);
1081 break;
1082 case 2:
1083 read_val = pci_read_word(pci_dev, address);
1084 break;
1085 case 4:
1086 read_val = pci_read_long(pci_dev, address);
1087 break;
1090 /* check libpci result */
1091 valid_mask = (0xFFFFFFFF >> ((4 - len) << 3));
1092 if ((read_val & valid_mask) == valid_mask)
1094 PT_LOG("Warning: Return ALL F from libpci read. "
1095 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1096 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1097 address, len);
1100 /* pass directly to libpci for passthrough type register group */
1101 if (reg_grp_entry == NULL)
1102 goto out;
1104 /* adjust the read and write value to appropriate CFC-CFF window */
1105 read_val <<= ((address & 3) << 3);
1106 val <<= ((address & 3) << 3);
1107 emul_len = len;
1109 /* loop Guest request size */
1110 while (0 < emul_len)
1112 /* find register entry to be emulated */
1113 reg_entry = pt_find_reg(reg_grp_entry, find_addr);
1114 if (reg_entry)
1116 reg = reg_entry->reg;
1117 real_offset = (reg_grp_entry->base_offset + reg->offset);
1118 valid_mask = (0xFFFFFFFF >> ((4 - emul_len) << 3));
1119 valid_mask <<= ((find_addr - real_offset) << 3);
1120 ptr_val = ((uint8_t *)&val + (real_offset & 3));
1122 /* do emulation depend on register size */
1123 switch (reg->size) {
1124 case 1:
1125 /* emulate write to byte register */
1126 if (reg->u.b.write)
1127 ret = reg->u.b.write(assigned_device, reg_entry,
1128 (uint8_t *)ptr_val,
1129 (uint8_t)(read_val >> ((real_offset & 3) << 3)),
1130 (uint8_t)valid_mask);
1131 break;
1132 case 2:
1133 /* emulate write to word register */
1134 if (reg->u.w.write)
1135 ret = reg->u.w.write(assigned_device, reg_entry,
1136 (uint16_t *)ptr_val,
1137 (uint16_t)(read_val >> ((real_offset & 3) << 3)),
1138 (uint16_t)valid_mask);
1139 break;
1140 case 4:
1141 /* emulate write to double word register */
1142 if (reg->u.dw.write)
1143 ret = reg->u.dw.write(assigned_device, reg_entry,
1144 (uint32_t *)ptr_val,
1145 (uint32_t)(read_val >> ((real_offset & 3) << 3)),
1146 (uint32_t)valid_mask);
1147 break;
1150 /* write emulation error */
1151 if (ret < 0)
1153 /* exit I/O emulator */
1154 PT_LOG("Internal error: Invalid write emulation "
1155 "return value[%d]. I/O emulator exit.\n", ret);
1156 exit(1);
1159 /* calculate next address to find */
1160 emul_len -= reg->size;
1161 if (emul_len > 0)
1162 find_addr = real_offset + reg->size;
1164 else
1166 /* nothing to do with passthrough type register,
1167 * continue to find next byte
1168 */
1169 emul_len--;
1170 find_addr++;
1174 /* need to shift back before passing them to libpci */
1175 val >>= ((address & 3) << 3);
1177 out:
1178 switch (len){
1179 case 1:
1180 pci_write_byte(pci_dev, address, val);
1181 break;
1182 case 2:
1183 pci_write_word(pci_dev, address, val);
1184 break;
1185 case 4:
1186 pci_write_long(pci_dev, address, val);
1187 break;
1190 exit:
1191 return;
1194 static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len)
1196 struct pt_dev *assigned_device = (struct pt_dev *)d;
1197 struct pci_dev *pci_dev = assigned_device->pci_dev;
1198 uint32_t val = 0xFFFFFFFF;
1199 struct pt_reg_grp_tbl *reg_grp_entry = NULL;
1200 struct pt_reg_grp_info_tbl *reg_grp = NULL;
1201 struct pt_reg_tbl *reg_entry = NULL;
1202 struct pt_reg_info_tbl *reg = NULL;
1203 uint32_t find_addr = address;
1204 uint32_t real_offset = 0;
1205 uint32_t valid_mask = 0xFFFFFFFF;
1206 uint8_t *ptr_val = NULL;
1207 int emul_len = 0;
1208 int ret = 0;
1210 /* check offset range */
1211 if (address >= 0xFF)
1213 PT_LOG("Failed to read register with offset exceeding FFh. "
1214 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1215 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1216 address, len);
1217 goto exit;
1220 /* check read size */
1221 if ((len != 1) && (len != 2) && (len != 4))
1223 PT_LOG("Failed to read register with invalid access length. "
1224 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1225 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1226 address, len);
1227 goto exit;
1230 /* check offset alignment */
1231 if (address & (len-1))
1233 PT_LOG("Failed to read register with invalid access size alignment. "
1234 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1235 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1236 address, len);
1237 goto exit;
1240 /* find register group entry */
1241 reg_grp_entry = pt_find_reg_grp(assigned_device, address);
1242 if (reg_grp_entry)
1244 reg_grp = reg_grp_entry->reg_grp;
1245 /* check 0 Hardwired register group */
1246 if (reg_grp->grp_type == GRP_TYPE_HARDWIRED)
1248 /* no need to emulate, just return 0 */
1249 val = 0;
1250 goto exit;
1254 /* read I/O device register value */
1255 switch (len) {
1256 case 1:
1257 val = pci_read_byte(pci_dev, address);
1258 break;
1259 case 2:
1260 val = pci_read_word(pci_dev, address);
1261 break;
1262 case 4:
1263 val = pci_read_long(pci_dev, address);
1264 break;
1267 /* check libpci result */
1268 valid_mask = (0xFFFFFFFF >> ((4 - len) << 3));
1269 if ((val & valid_mask) == valid_mask)
1271 PT_LOG("Warning: Return ALL F from libpci read. "
1272 "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
1273 pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
1274 address, len);
1277 /* just return the I/O device register value for
1278 * passthrough type register group
1279 */
1280 if (reg_grp_entry == NULL)
1281 goto exit;
1283 /* adjust the read value to appropriate CFC-CFF window */
1284 val <<= ((address & 3) << 3);
1285 emul_len = len;
1287 /* loop Guest request size */
1288 while (0 < emul_len)
1290 /* find register entry to be emulated */
1291 reg_entry = pt_find_reg(reg_grp_entry, find_addr);
1292 if (reg_entry)
1294 reg = reg_entry->reg;
1295 real_offset = (reg_grp_entry->base_offset + reg->offset);
1296 valid_mask = (0xFFFFFFFF >> ((4 - emul_len) << 3));
1297 valid_mask <<= ((find_addr - real_offset) << 3);
1298 ptr_val = ((uint8_t *)&val + (real_offset & 3));
1300 /* do emulation depend on register size */
1301 switch (reg->size) {
1302 case 1:
1303 /* emulate read to byte register */
1304 if (reg->u.b.read)
1305 ret = reg->u.b.read(assigned_device, reg_entry,
1306 (uint8_t *)ptr_val,
1307 (uint8_t)valid_mask);
1308 break;
1309 case 2:
1310 /* emulate read to word register */
1311 if (reg->u.w.read)
1312 ret = reg->u.w.read(assigned_device, reg_entry,
1313 (uint16_t *)ptr_val,
1314 (uint16_t)valid_mask);
1315 break;
1316 case 4:
1317 /* emulate read to double word register */
1318 if (reg->u.dw.read)
1319 ret = reg->u.dw.read(assigned_device, reg_entry,
1320 (uint32_t *)ptr_val,
1321 (uint32_t)valid_mask);
1322 break;
1325 /* read emulation error */
1326 if (ret < 0)
1328 /* exit I/O emulator */
1329 PT_LOG("Internal error: Invalid read emulation "
1330 "return value[%d]. I/O emulator exit.\n", ret);
1331 exit(1);
1334 /* calculate next address to find */
1335 emul_len -= reg->size;
1336 if (emul_len > 0)
1337 find_addr = real_offset + reg->size;
1339 else
1341 /* nothing to do with passthrough type register,
1342 * continue to find next byte
1343 */
1344 emul_len--;
1345 find_addr++;
1349 /* need to shift back before returning them to pci bus emulator */
1350 val >>= ((address & 3) << 3);
1352 exit:
1354 #ifdef PT_DEBUG_PCI_CONFIG_ACCESS
1355 PT_LOG("[%02x:%02x.%x]: address=%04x val=0x%08x len=%d\n",
1356 pci_bus_num(d->bus), (d->devfn >> 3) & 0x1F, (d->devfn & 0x7),
1357 address, val, len);
1358 #endif
1360 return val;
1363 static int pt_register_regions(struct pt_dev *assigned_device)
1365 int i = 0;
1366 uint32_t bar_data = 0;
1367 struct pci_dev *pci_dev = assigned_device->pci_dev;
1368 PCIDevice *d = &assigned_device->dev;
1370 /* Register PIO/MMIO BARs */
1371 for ( i = 0; i < PCI_BAR_ENTRIES; i++ )
1373 if ( pci_dev->base_addr[i] )
1375 assigned_device->bases[i].e_physbase = pci_dev->base_addr[i];
1376 assigned_device->bases[i].access.u = pci_dev->base_addr[i];
1378 /* Register current region */
1379 bar_data = *((uint32_t*)(d->config + PCI_BASE_ADDRESS_0) + i);
1380 if ( bar_data & PCI_ADDRESS_SPACE_IO )
1381 pci_register_io_region((PCIDevice *)assigned_device, i,
1382 (uint32_t)pci_dev->size[i], PCI_ADDRESS_SPACE_IO,
1383 pt_ioport_map);
1384 else if ( bar_data & PCI_ADDRESS_SPACE_MEM_PREFETCH )
1385 pci_register_io_region((PCIDevice *)assigned_device, i,
1386 (uint32_t)pci_dev->size[i], PCI_ADDRESS_SPACE_MEM_PREFETCH,
1387 pt_iomem_map);
1388 else
1389 pci_register_io_region((PCIDevice *)assigned_device, i,
1390 (uint32_t)pci_dev->size[i], PCI_ADDRESS_SPACE_MEM,
1391 pt_iomem_map);
1393 PT_LOG("IO region registered (size=0x%08x base_addr=0x%08x)\n",
1394 (uint32_t)(pci_dev->size[i]),
1395 (uint32_t)(pci_dev->base_addr[i]));
1399 /* Register expansion ROM address */
1400 if ( pci_dev->rom_base_addr && pci_dev->rom_size )
1402 assigned_device->bases[PCI_ROM_SLOT].e_physbase =
1403 pci_dev->rom_base_addr;
1404 assigned_device->bases[PCI_ROM_SLOT].access.maddr =
1405 pci_dev->rom_base_addr;
1406 pci_register_io_region((PCIDevice *)assigned_device, PCI_ROM_SLOT,
1407 pci_dev->rom_size, PCI_ADDRESS_SPACE_MEM_PREFETCH,
1408 pt_iomem_map);
1410 PT_LOG("Expansion ROM registered (size=0x%08x base_addr=0x%08x)\n",
1411 (uint32_t)(pci_dev->rom_size), (uint32_t)(pci_dev->rom_base_addr));
1414 return 0;
1417 static void pt_unregister_regions(struct pt_dev *assigned_device)
1419 int i, type, ret;
1420 uint32_t e_size;
1421 PCIDevice *d = (PCIDevice*)assigned_device;
1423 for ( i = 0; i < PCI_NUM_REGIONS; i++ )
1425 e_size = assigned_device->bases[i].e_size;
1426 if ( (e_size == 0) || (assigned_device->bases[i].e_physbase == -1) )
1427 continue;
1429 type = d->io_regions[i].type;
1431 if ( type == PCI_ADDRESS_SPACE_MEM ||
1432 type == PCI_ADDRESS_SPACE_MEM_PREFETCH )
1434 ret = xc_domain_memory_mapping(xc_handle, domid,
1435 assigned_device->bases[i].e_physbase >> XC_PAGE_SHIFT,
1436 assigned_device->bases[i].access.maddr >> XC_PAGE_SHIFT,
1437 (e_size+XC_PAGE_SIZE-1) >> XC_PAGE_SHIFT,
1438 DPCI_REMOVE_MAPPING);
1439 if ( ret != 0 )
1441 PT_LOG("Error: remove old mem mapping failed!\n");
1442 continue;
1446 else if ( type == PCI_ADDRESS_SPACE_IO )
1448 ret = xc_domain_ioport_mapping(xc_handle, domid,
1449 assigned_device->bases[i].e_physbase,
1450 assigned_device->bases[i].access.pio_base,
1451 e_size,
1452 DPCI_REMOVE_MAPPING);
1453 if ( ret != 0 )
1455 PT_LOG("Error: remove old io mapping failed!\n");
1456 continue;
1465 uint8_t find_cap_offset(struct pci_dev *pci_dev, uint8_t cap)
1467 int id;
1468 int max_cap = 48;
1469 int pos = PCI_CAPABILITY_LIST;
1470 int status;
1472 status = pci_read_byte(pci_dev, PCI_STATUS);
1473 if ( (status & PCI_STATUS_CAP_LIST) == 0 )
1474 return 0;
1476 while ( max_cap-- )
1478 pos = pci_read_byte(pci_dev, pos);
1479 if ( pos < 0x40 )
1480 break;
1482 pos &= ~3;
1483 id = pci_read_byte(pci_dev, pos + PCI_CAP_LIST_ID);
1485 if ( id == 0xff )
1486 break;
1487 if ( id == cap )
1488 return pos;
1490 pos += PCI_CAP_LIST_NEXT;
1492 return 0;
1495 /* parse BAR */
1496 static int pt_bar_reg_parse(
1497 struct pt_dev *ptdev, struct pt_reg_info_tbl *reg)
1499 PCIDevice *d = &ptdev->dev;
1500 struct pt_region *region = NULL;
1501 PCIIORegion *r;
1502 uint32_t bar_64 = (reg->offset - 4);
1503 int bar_flag = PT_BAR_FLAG_UNUSED;
1504 int index = 0;
1505 int i;
1507 /* set again the BAR config because it has been overwritten
1508 * by pci_register_io_region()
1509 */
1510 for (i=reg->offset; i<(reg->offset + 4); i++)
1511 d->config[i] = pci_read_byte(ptdev->pci_dev, i);
1513 /* check 64bit BAR */
1514 index = pt_bar_offset_to_index(reg->offset);
1515 if ((index > 0) && (index < PCI_ROM_SLOT) &&
1516 ((d->config[bar_64] & (PCI_BASE_ADDRESS_SPACE |
1517 PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
1518 (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)))
1520 region = &ptdev->bases[index-1];
1521 if (region->bar_flag != PT_BAR_FLAG_UPPER)
1523 bar_flag = PT_BAR_FLAG_UPPER;
1524 goto out;
1528 /* check unused BAR */
1529 r = &d->io_regions[index];
1530 if (!r->size)
1531 goto out;
1533 /* for ExpROM BAR */
1534 if (index == PCI_ROM_SLOT)
1536 bar_flag = PT_BAR_FLAG_MEM;
1537 goto out;
1540 /* check BAR I/O indicator */
1541 if (d->config[reg->offset] & PCI_BASE_ADDRESS_SPACE_IO)
1542 bar_flag = PT_BAR_FLAG_IO;
1543 else
1544 bar_flag = PT_BAR_FLAG_MEM;
1546 out:
1547 return bar_flag;
1550 /* mapping BAR */
1551 static void pt_bar_mapping(struct pt_dev *ptdev, int io_enable, int mem_enable)
1553 PCIDevice *dev = (PCIDevice *)&ptdev->dev;
1554 PCIIORegion *r;
1555 struct pt_region *base = NULL;
1556 uint32_t r_size = 0, r_addr = -1;
1557 int ret = 0;
1558 int i;
1560 for (i=0; i<PCI_NUM_REGIONS; i++)
1562 r = &dev->io_regions[i];
1564 /* check valid region */
1565 if (!r->size)
1566 continue;
1568 base = &ptdev->bases[i];
1569 /* skip unused BAR or upper 64bit BAR */
1570 if ((base->bar_flag == PT_BAR_FLAG_UNUSED) ||
1571 (base->bar_flag == PT_BAR_FLAG_UPPER))
1572 continue;
1574 /* copy region address to temporary */
1575 r_addr = r->addr;
1577 /* need unmapping in case I/O Space or Memory Space disable */
1578 if (((base->bar_flag == PT_BAR_FLAG_IO) && !io_enable ) ||
1579 ((base->bar_flag == PT_BAR_FLAG_MEM) && !mem_enable ))
1580 r_addr = -1;
1582 /* prevent guest software mapping memory resource to 00000000h */
1583 if ((base->bar_flag == PT_BAR_FLAG_MEM) && (r_addr == 0))
1584 r_addr = -1;
1586 /* align resource size (memory type only) */
1587 r_size = r->size;
1588 PT_GET_EMUL_SIZE(base->bar_flag, r_size);
1590 /* check overlapped address */
1591 ret = pt_chk_bar_overlap(dev->bus, dev->devfn, r_addr, r_size);
1592 if (ret > 0)
1593 PT_LOG("ptdev[%02x:%02x.%x][Region:%d][Address:%08xh][Size:%08xh] "
1594 "is overlapped.\n", pci_bus_num(dev->bus),
1595 (dev->devfn >> 3) & 0x1F, (dev->devfn & 0x7),
1596 i, r_addr, r_size);
1598 /* check whether we need to update the mapping or not */
1599 if (r_addr != ptdev->bases[i].e_physbase)
1601 /* mapping BAR */
1602 r->map_func((PCIDevice *)ptdev, i, r_addr,
1603 r_size, r->type);
1607 return;
1610 /* initialize emulate register */
1611 static int pt_config_reg_init(struct pt_dev *ptdev,
1612 struct pt_reg_grp_tbl *reg_grp,
1613 struct pt_reg_info_tbl *reg)
1615 struct pt_reg_tbl *reg_entry;
1616 uint32_t data = 0;
1617 int err = 0;
1619 /* allocate register entry */
1620 reg_entry = qemu_mallocz(sizeof(struct pt_reg_tbl));
1621 if (reg_entry == NULL)
1623 PT_LOG("Failed to allocate memory.\n");
1624 err = -1;
1625 goto out;
1628 /* initialize register entry */
1629 reg_entry->reg = reg;
1630 reg_entry->data = 0;
1632 if (reg->init)
1634 /* initialize emulate register */
1635 data = reg->init(ptdev, reg_entry->reg,
1636 (reg_grp->base_offset + reg->offset));
1637 if (data == PT_INVALID_REG)
1639 /* free unused BAR register entry */
1640 free(reg_entry);
1641 goto out;
1643 /* set register value */
1644 reg_entry->data = data;
1646 /* list add register entry */
1647 LIST_INSERT_HEAD(&reg_grp->reg_tbl_head, reg_entry, entries);
1649 out:
1650 return err;
1653 /* initialize emulate register group */
1654 static int pt_config_init(struct pt_dev *ptdev)
1656 struct pt_reg_grp_tbl *reg_grp_entry = NULL;
1657 struct pt_reg_info_tbl *reg_tbl = NULL;
1658 uint32_t reg_grp_offset = 0;
1659 int i, j, err = 0;
1661 /* initialize register group list */
1662 LIST_INIT(&ptdev->reg_grp_tbl_head);
1664 /* initialize register group */
1665 for (i=0; pt_emu_reg_grp_tbl[i].grp_size != 0; i++)
1667 if (pt_emu_reg_grp_tbl[i].grp_id != 0xFF)
1669 reg_grp_offset = (uint32_t)find_cap_offset(ptdev->pci_dev,
1670 pt_emu_reg_grp_tbl[i].grp_id);
1671 if (!reg_grp_offset)
1672 continue;
1675 /* allocate register group table */
1676 reg_grp_entry = qemu_mallocz(sizeof(struct pt_reg_grp_tbl));
1677 if (reg_grp_entry == NULL)
1679 PT_LOG("Failed to allocate memory.\n");
1680 err = -1;
1681 goto out;
1684 /* initialize register group entry */
1685 LIST_INIT(&reg_grp_entry->reg_tbl_head);
1687 /* need to declare here, to enable searching Cap Ptr reg
1688 * (which is in the same reg group) when initializing Status reg
1689 */
1690 LIST_INSERT_HEAD(&ptdev->reg_grp_tbl_head, reg_grp_entry, entries);
1692 reg_grp_entry->base_offset = reg_grp_offset;
1693 reg_grp_entry->reg_grp =
1694 (struct pt_reg_grp_info_tbl*)&pt_emu_reg_grp_tbl[i];
1695 if (pt_emu_reg_grp_tbl[i].size_init)
1697 /* get register group size */
1698 reg_grp_entry->size = pt_emu_reg_grp_tbl[i].size_init(ptdev,
1699 reg_grp_entry->reg_grp,
1700 reg_grp_offset);
1703 if (pt_emu_reg_grp_tbl[i].grp_type == GRP_TYPE_EMU)
1705 if (pt_emu_reg_grp_tbl[i].emu_reg_tbl)
1707 reg_tbl = pt_emu_reg_grp_tbl[i].emu_reg_tbl;
1708 /* initialize capability register */
1709 for (j=0; reg_tbl->size != 0; j++, reg_tbl++)
1711 /* initialize capability register */
1712 err = pt_config_reg_init(ptdev, reg_grp_entry, reg_tbl);
1713 if (err < 0)
1714 goto out;
1718 reg_grp_offset = 0;
1721 out:
1722 return err;
1725 /* delete all emulate register */
1726 static void pt_config_delete(struct pt_dev *ptdev)
1728 struct pt_reg_grp_tbl *reg_grp_entry = NULL;
1729 struct pt_reg_tbl *reg_entry = NULL;
1731 /* free MSI/MSI-X info table */
1732 if (ptdev->msix)
1733 pt_msix_delete(ptdev);
1734 if (ptdev->msi)
1735 free(ptdev->msi);
1737 /* free all register group entry */
1738 while ((reg_grp_entry = ptdev->reg_grp_tbl_head.lh_first) != NULL)
1740 /* free all register entry */
1741 while ((reg_entry = reg_grp_entry->reg_tbl_head.lh_first) != NULL)
1743 LIST_REMOVE(reg_entry, entries);
1744 qemu_free(reg_entry);
1747 LIST_REMOVE(reg_grp_entry, entries);
1748 qemu_free(reg_grp_entry);
1752 /* initialize common register value */
1753 static uint32_t pt_common_reg_init(struct pt_dev *ptdev,
1754 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1756 return reg->init_val;
1759 /* initialize Capabilities Pointer or Next Pointer register */
1760 static uint32_t pt_ptr_reg_init(struct pt_dev *ptdev,
1761 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1763 uint32_t reg_field = (uint32_t)ptdev->dev.config[real_offset];
1764 int i;
1766 /* find capability offset */
1767 while (reg_field)
1769 for (i=0; pt_emu_reg_grp_tbl[i].grp_size != 0; i++)
1771 /* check whether the next capability
1772 * should be exported to guest or not
1773 */
1774 if (pt_emu_reg_grp_tbl[i].grp_id == ptdev->dev.config[reg_field])
1776 if (pt_emu_reg_grp_tbl[i].grp_type == GRP_TYPE_EMU)
1777 goto out;
1778 /* ignore the 0 hardwired capability, find next one */
1779 break;
1782 /* next capability */
1783 reg_field = (uint32_t)ptdev->dev.config[reg_field + 1];
1786 out:
1787 return reg_field;
1790 /* initialize Status register */
1791 static uint32_t pt_status_reg_init(struct pt_dev *ptdev,
1792 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1794 struct pt_reg_grp_tbl *reg_grp_entry = NULL;
1795 struct pt_reg_tbl *reg_entry = NULL;
1796 int reg_field = 0;
1798 /* find Header register group */
1799 reg_grp_entry = pt_find_reg_grp(ptdev, PCI_CAPABILITY_LIST);
1800 if (reg_grp_entry)
1802 /* find Capabilities Pointer register */
1803 reg_entry = pt_find_reg(reg_grp_entry, PCI_CAPABILITY_LIST);
1804 if (reg_entry)
1806 /* check Capabilities Pointer register */
1807 if (reg_entry->data)
1808 reg_field |= PCI_STATUS_CAP_LIST;
1809 else
1810 reg_field &= ~PCI_STATUS_CAP_LIST;
1812 else
1814 /* exit I/O emulator */
1815 PT_LOG("Internal error: Couldn't find pt_reg_tbl for "
1816 "Capabilities Pointer register. I/O emulator exit.\n");
1817 exit(1);
1820 else
1822 /* exit I/O emulator */
1823 PT_LOG("Internal error: Couldn't find pt_reg_grp_tbl for Header. "
1824 "I/O emulator exit.\n");
1825 exit(1);
1828 return reg_field;
1831 /* initialize Interrupt Pin register */
1832 static uint32_t pt_irqpin_reg_init(struct pt_dev *ptdev,
1833 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1835 int reg_field = 0;
1837 /* set Interrupt Pin register to use INTA# if it has */
1838 if (ptdev->dev.config[real_offset])
1839 reg_field = 0x01;
1841 return reg_field;
1844 /* initialize BAR */
1845 static uint32_t pt_bar_reg_init(struct pt_dev *ptdev,
1846 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1848 int reg_field = 0;
1849 int index;
1851 /* get BAR index */
1852 index = pt_bar_offset_to_index(reg->offset);
1853 if (index < 0)
1855 /* exit I/O emulator */
1856 PT_LOG("Internal error: Invalid BAR index[%d]. "
1857 "I/O emulator exit.\n", index);
1858 exit(1);
1861 /* set initial guest physical base address to -1 */
1862 ptdev->bases[index].e_physbase = -1;
1864 /* set BAR flag */
1865 ptdev->bases[index].bar_flag = pt_bar_reg_parse(ptdev, reg);
1866 if (ptdev->bases[index].bar_flag == PT_BAR_FLAG_UNUSED)
1867 reg_field = PT_INVALID_REG;
1869 return reg_field;
1872 /* initialize Link Control 2 register */
1873 static uint32_t pt_linkctrl2_reg_init(struct pt_dev *ptdev,
1874 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1876 int reg_field = 0;
1878 /* set Supported Link Speed */
1879 reg_field |=
1880 (0x0F &
1881 ptdev->dev.config[(real_offset - reg->offset) + PCI_EXP_LNKCAP]);
1883 return reg_field;
1886 /* initialize Message Control register */
1887 static uint32_t pt_msgctrl_reg_init(struct pt_dev *ptdev,
1888 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1890 PCIDevice *d = (struct PCIDevice *)ptdev;
1891 struct pci_dev *pdev = ptdev->pci_dev;
1892 uint32_t reg_field = 0;
1894 /* use I/O device register's value as initial value */
1895 reg_field |= *((uint16_t*)(d->config + real_offset));
1897 if (reg_field & PCI_MSI_FLAGS_ENABLE)
1899 PT_LOG("MSI enabled already, disable first\n");
1900 pci_write_word(pdev, real_offset, reg_field & ~PCI_MSI_FLAGS_ENABLE);
1902 ptdev->msi->flags |= (reg_field | MSI_FLAG_UNINIT);
1904 /* All register is 0 after reset, except first 4 byte */
1905 reg_field &= reg->ro_mask;
1907 return reg_field;
1910 /* initialize Message Address register */
1911 static uint32_t pt_msgaddr32_reg_init(struct pt_dev *ptdev,
1912 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1914 PCIDevice *d = (struct PCIDevice *)ptdev;
1915 uint32_t reg_field = 0;
1917 /* use I/O device register's value as initial value */
1918 reg_field |= *((uint32_t*)(d->config + real_offset));
1920 return reg_field;
1923 /* initialize Message Upper Address register */
1924 static uint32_t pt_msgaddr64_reg_init(struct pt_dev *ptdev,
1925 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1927 PCIDevice *d = (struct PCIDevice *)ptdev;
1928 uint32_t reg_field = 0;
1930 /* no need to initialize in case of 32 bit type */
1931 if (!(ptdev->msi->flags & PCI_MSI_FLAGS_64BIT))
1932 return PT_INVALID_REG;
1934 /* use I/O device register's value as initial value */
1935 reg_field |= *((uint32_t*)(d->config + real_offset));
1937 return reg_field;
1940 /* this function will be called twice (for 32 bit and 64 bit type) */
1941 /* initialize Message Data register */
1942 static uint32_t pt_msgdata_reg_init(struct pt_dev *ptdev,
1943 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1945 PCIDevice *d = (struct PCIDevice *)ptdev;
1946 uint32_t flags = ptdev->msi->flags;
1947 uint32_t offset = reg->offset;
1949 /* check the offset whether matches the type or not */
1950 if (((offset == PCI_MSI_DATA_64) && (flags & PCI_MSI_FLAGS_64BIT)) ||
1951 ((offset == PCI_MSI_DATA_32) && !(flags & PCI_MSI_FLAGS_64BIT)))
1952 return *((uint16_t*)(d->config + real_offset));
1953 else
1954 return PT_INVALID_REG;
1957 /* initialize Message Control register for MSI-X */
1958 static uint32_t pt_msixctrl_reg_init(struct pt_dev *ptdev,
1959 struct pt_reg_info_tbl *reg, uint32_t real_offset)
1961 PCIDevice *d = (struct PCIDevice *)ptdev;
1962 struct pci_dev *pdev = ptdev->pci_dev;
1963 uint16_t reg_field = 0;
1965 /* use I/O device register's value as initial value */
1966 reg_field |= *((uint16_t*)(d->config + real_offset));
1968 if (reg_field & PCI_MSIX_ENABLE)
1970 PT_LOG("MSIX enabled already, disable first\n");
1971 pci_write_word(pdev, real_offset, reg_field & ~PCI_MSIX_ENABLE);
1972 reg_field &= ~(PCI_MSIX_ENABLE | PCI_MSIX_MASK);
1975 return reg_field;
1978 /* get register group size */
1979 static uint8_t pt_reg_grp_size_init(struct pt_dev *ptdev,
1980 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset)
1982 return grp_reg->grp_size;
1985 /* get MSI Capability Structure register group size */
1986 static uint8_t pt_msi_size_init(struct pt_dev *ptdev,
1987 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset)
1989 PCIDevice *d = &ptdev->dev;
1990 uint16_t msg_ctrl = 0;
1991 uint8_t msi_size = 0xa;
1993 msg_ctrl = *((uint16_t*)(d->config + (base_offset + PCI_MSI_FLAGS)));
1995 /* check 64 bit address capable & Per-vector masking capable */
1996 if (msg_ctrl & PCI_MSI_FLAGS_64BIT)
1997 msi_size += 4;
1998 if (msg_ctrl & PCI_MSI_FLAGS_MASK_BIT)
1999 msi_size += 10;
2001 ptdev->msi = malloc(sizeof(struct pt_msi_info));
2002 if ( !ptdev->msi )
2004 /* exit I/O emulator */
2005 PT_LOG("error allocation pt_msi_info. I/O emulator exit.\n");
2006 exit(1);
2008 memset(ptdev->msi, 0, sizeof(struct pt_msi_info));
2010 return msi_size;
2013 /* get MSI-X Capability Structure register group size */
2014 static uint8_t pt_msix_size_init(struct pt_dev *ptdev,
2015 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset)
2017 int ret = 0;
2019 ret = pt_msix_init(ptdev, base_offset);
2021 if (ret == -1)
2023 /* exit I/O emulator */
2024 PT_LOG("Internal error: Invalid pt_msix_init return value[%d]. "
2025 "I/O emulator exit.\n", ret);
2026 exit(1);
2029 return grp_reg->grp_size;
2032 /* get Vendor Specific Capability Structure register group size */
2033 static uint8_t pt_vendor_size_init(struct pt_dev *ptdev,
2034 struct pt_reg_grp_info_tbl *grp_reg, uint32_t base_offset)
2036 return ptdev->dev.config[base_offset + 0x02];
2039 /* read byte size emulate register */
2040 static int pt_byte_reg_read(struct pt_dev *ptdev,
2041 struct pt_reg_tbl *cfg_entry,
2042 uint8_t *value, uint8_t valid_mask)
2044 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2045 uint8_t valid_emu_mask = 0;
2047 /* emulate byte register */
2048 valid_emu_mask = reg->emu_mask & valid_mask;
2049 *value = ((*value & ~valid_emu_mask) |
2050 (cfg_entry->data & valid_emu_mask));
2052 return 0;
2055 /* read word size emulate register */
2056 static int pt_word_reg_read(struct pt_dev *ptdev,
2057 struct pt_reg_tbl *cfg_entry,
2058 uint16_t *value, uint16_t valid_mask)
2060 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2061 uint16_t valid_emu_mask = 0;
2063 /* emulate word register */
2064 valid_emu_mask = reg->emu_mask & valid_mask;
2065 *value = ((*value & ~valid_emu_mask) |
2066 (cfg_entry->data & valid_emu_mask));
2068 return 0;
2071 /* read long size emulate register */
2072 static int pt_long_reg_read(struct pt_dev *ptdev,
2073 struct pt_reg_tbl *cfg_entry,
2074 uint32_t *value, uint32_t valid_mask)
2076 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2077 uint32_t valid_emu_mask = 0;
2079 /* emulate long register */
2080 valid_emu_mask = reg->emu_mask & valid_mask;
2081 *value = ((*value & ~valid_emu_mask) |
2082 (cfg_entry->data & valid_emu_mask));
2084 return 0;
2087 /* read BAR */
2088 static int pt_bar_reg_read(struct pt_dev *ptdev,
2089 struct pt_reg_tbl *cfg_entry,
2090 uint32_t *value, uint32_t valid_mask)
2092 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2093 uint32_t valid_emu_mask = 0;
2094 uint32_t bar_emu_mask = 0;
2095 int index;
2097 /* get BAR index */
2098 index = pt_bar_offset_to_index(reg->offset);
2099 if (index < 0)
2101 /* exit I/O emulator */
2102 PT_LOG("Internal error: Invalid BAR index[%d]. "
2103 "I/O emulator exit.\n", index);
2104 exit(1);
2107 /* set emulate mask depend on BAR flag */
2108 switch (ptdev->bases[index].bar_flag)
2110 case PT_BAR_FLAG_MEM:
2111 bar_emu_mask = PT_BAR_MEM_EMU_MASK;
2112 break;
2113 case PT_BAR_FLAG_IO:
2114 bar_emu_mask = PT_BAR_IO_EMU_MASK;
2115 break;
2116 case PT_BAR_FLAG_UPPER:
2117 bar_emu_mask = PT_BAR_ALLF;
2118 break;
2119 default:
2120 break;
2123 /* emulate BAR */
2124 valid_emu_mask = bar_emu_mask & valid_mask;
2125 *value = ((*value & ~valid_emu_mask) |
2126 (cfg_entry->data & valid_emu_mask));
2128 return 0;
2131 /* write byte size emulate register */
2132 static int pt_byte_reg_write(struct pt_dev *ptdev,
2133 struct pt_reg_tbl *cfg_entry,
2134 uint8_t *value, uint8_t dev_value, uint8_t valid_mask)
2136 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2137 uint8_t writable_mask = 0;
2138 uint8_t throughable_mask = 0;
2140 /* modify emulate register */
2141 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2142 cfg_entry->data = ((*value & writable_mask) |
2143 (cfg_entry->data & ~writable_mask));
2145 /* create value for writing to I/O device register */
2146 throughable_mask = ~reg->emu_mask & valid_mask;
2147 *value = ((*value & throughable_mask) |
2148 (dev_value & ~throughable_mask));
2150 return 0;
2153 /* write word size emulate register */
2154 static int pt_word_reg_write(struct pt_dev *ptdev,
2155 struct pt_reg_tbl *cfg_entry,
2156 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2158 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2159 uint16_t writable_mask = 0;
2160 uint16_t throughable_mask = 0;
2162 /* modify emulate register */
2163 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2164 cfg_entry->data = ((*value & writable_mask) |
2165 (cfg_entry->data & ~writable_mask));
2167 /* create value for writing to I/O device register */
2168 throughable_mask = ~reg->emu_mask & valid_mask;
2169 *value = ((*value & throughable_mask) |
2170 (dev_value & ~throughable_mask));
2172 return 0;
2175 /* write long size emulate register */
2176 static int pt_long_reg_write(struct pt_dev *ptdev,
2177 struct pt_reg_tbl *cfg_entry,
2178 uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
2180 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2181 uint32_t writable_mask = 0;
2182 uint32_t throughable_mask = 0;
2184 /* modify emulate register */
2185 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2186 cfg_entry->data = ((*value & writable_mask) |
2187 (cfg_entry->data & ~writable_mask));
2189 /* create value for writing to I/O device register */
2190 throughable_mask = ~reg->emu_mask & valid_mask;
2191 *value = ((*value & throughable_mask) |
2192 (dev_value & ~throughable_mask));
2194 return 0;
2197 /* write Command register */
2198 static int pt_cmd_reg_write(struct pt_dev *ptdev,
2199 struct pt_reg_tbl *cfg_entry,
2200 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2202 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2203 uint16_t writable_mask = 0;
2204 uint16_t throughable_mask = 0;
2205 uint16_t wr_value = *value;
2207 /* modify emulate register */
2208 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2209 cfg_entry->data = ((*value & writable_mask) |
2210 (cfg_entry->data & ~writable_mask));
2212 /* create value for writing to I/O device register */
2213 throughable_mask = ~reg->emu_mask & valid_mask;
2214 *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
2216 /* mapping BAR */
2217 pt_bar_mapping(ptdev, wr_value & PCI_COMMAND_IO,
2218 wr_value & PCI_COMMAND_MEMORY);
2220 return 0;
2223 /* write BAR */
2224 static int pt_bar_reg_write(struct pt_dev *ptdev,
2225 struct pt_reg_tbl *cfg_entry,
2226 uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
2228 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2229 struct pt_reg_grp_tbl *reg_grp_entry = NULL;
2230 struct pt_reg_tbl *reg_entry = NULL;
2231 struct pt_region *base = NULL;
2232 PCIDevice *d = (PCIDevice *)&ptdev->dev;
2233 PCIIORegion *r;
2234 uint32_t writable_mask = 0;
2235 uint32_t throughable_mask = 0;
2236 uint32_t bar_emu_mask = 0;
2237 uint32_t bar_ro_mask = 0;
2238 uint32_t new_addr, last_addr;
2239 uint32_t prev_offset;
2240 uint32_t r_size = 0;
2241 int index = 0;
2243 /* get BAR index */
2244 index = pt_bar_offset_to_index(reg->offset);
2245 if (index < 0)
2247 /* exit I/O emulator */
2248 PT_LOG("Internal error: Invalid BAR index[%d]. "
2249 "I/O emulator exit.\n", index);
2250 exit(1);
2253 r = &d->io_regions[index];
2254 r_size = r->size;
2255 base = &ptdev->bases[index];
2256 /* align resource size (memory type only) */
2257 PT_GET_EMUL_SIZE(base->bar_flag, r_size);
2259 /* set emulate mask and read-only mask depend on BAR flag */
2260 switch (ptdev->bases[index].bar_flag)
2262 case PT_BAR_FLAG_MEM:
2263 bar_emu_mask = PT_BAR_MEM_EMU_MASK;
2264 bar_ro_mask = PT_BAR_MEM_RO_MASK | (r_size - 1);
2265 break;
2266 case PT_BAR_FLAG_IO:
2267 bar_emu_mask = PT_BAR_IO_EMU_MASK;
2268 bar_ro_mask = PT_BAR_IO_RO_MASK | (r_size - 1);
2269 break;
2270 case PT_BAR_FLAG_UPPER:
2271 bar_emu_mask = PT_BAR_ALLF;
2272 bar_ro_mask = 0; /* all upper 32bit are R/W */
2273 break;
2274 default:
2275 break;
2278 /* modify emulate register */
2279 writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
2280 cfg_entry->data = ((*value & writable_mask) |
2281 (cfg_entry->data & ~writable_mask));
2283 /* check whether we need to update the virtual region address or not */
2284 switch (ptdev->bases[index].bar_flag)
2286 case PT_BAR_FLAG_MEM:
2287 /* nothing to do */
2288 break;
2289 case PT_BAR_FLAG_IO:
2290 new_addr = cfg_entry->data;
2291 last_addr = new_addr + r_size - 1;
2292 /* check invalid address */
2293 if (last_addr <= new_addr || !new_addr || last_addr >= 0x10000)
2295 /* check 64K range */
2296 if ((last_addr >= 0x10000) &&
2297 (cfg_entry->data != (PT_BAR_ALLF & ~bar_ro_mask)))
2299 PT_LOG("Guest attempt to set Base Address over the 64KB. "
2300 "[%02x:%02x.%x][Offset:%02xh][Address:%08xh][Size:%08xh]\n",
2301 pci_bus_num(d->bus),
2302 ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
2303 reg->offset, new_addr, r_size);
2305 /* just remove mapping */
2306 r->addr = -1;
2307 goto exit;
2309 break;
2310 case PT_BAR_FLAG_UPPER:
2311 if (cfg_entry->data)
2313 if (cfg_entry->data != (PT_BAR_ALLF & ~bar_ro_mask))
2315 PT_LOG("Guest attempt to set high MMIO Base Address. "
2316 "Ignore mapping. "
2317 "[%02x:%02x.%x][Offset:%02xh][High Address:%08xh]\n",
2318 pci_bus_num(d->bus),
2319 ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7),
2320 reg->offset, cfg_entry->data);
2322 /* clear lower address */
2323 d->io_regions[index-1].addr = -1;
2325 else
2327 /* find lower 32bit BAR */
2328 prev_offset = (reg->offset - 4);
2329 reg_grp_entry = pt_find_reg_grp(ptdev, prev_offset);
2330 if (reg_grp_entry)
2332 reg_entry = pt_find_reg(reg_grp_entry, prev_offset);
2333 if (reg_entry)
2334 /* restore lower address */
2335 d->io_regions[index-1].addr = reg_entry->data;
2336 else
2337 return -1;
2339 else
2340 return -1;
2343 /* never mapping the 'empty' upper region,
2344 * because we'll do it enough for the lower region.
2345 */
2346 r->addr = -1;
2347 goto exit;
2348 default:
2349 break;
2352 /* update the corresponding virtual region address */
2353 r->addr = cfg_entry->data;
2355 exit:
2356 /* create value for writing to I/O device register */
2357 throughable_mask = ~bar_emu_mask & valid_mask;
2358 *value = ((*value & throughable_mask) |
2359 (dev_value & ~throughable_mask));
2361 return 0;
2364 /* write Exp ROM BAR */
2365 static int pt_exp_rom_bar_reg_write(struct pt_dev *ptdev,
2366 struct pt_reg_tbl *cfg_entry,
2367 uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
2369 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2370 struct pt_region *base = NULL;
2371 PCIDevice *d = (PCIDevice *)&ptdev->dev;
2372 PCIIORegion *r;
2373 uint32_t writable_mask = 0;
2374 uint32_t throughable_mask = 0;
2375 uint32_t r_size = 0;
2376 uint32_t bar_emu_mask = 0;
2377 uint32_t bar_ro_mask = 0;
2379 r = &d->io_regions[PCI_ROM_SLOT];
2380 r_size = r->size;
2381 base = &ptdev->bases[PCI_ROM_SLOT];
2382 /* align memory type resource size */
2383 PT_GET_EMUL_SIZE(base->bar_flag, r_size);
2385 /* set emulate mask and read-only mask */
2386 bar_emu_mask = reg->emu_mask;
2387 bar_ro_mask = reg->ro_mask | (r_size - 1);
2389 /* modify emulate register */
2390 writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
2391 cfg_entry->data = ((*value & writable_mask) |
2392 (cfg_entry->data & ~writable_mask));
2394 /* update the corresponding virtual region address */
2395 r->addr = cfg_entry->data;
2397 /* create value for writing to I/O device register */
2398 throughable_mask = ~bar_emu_mask & valid_mask;
2399 *value = ((*value & throughable_mask) |
2400 (dev_value & ~throughable_mask));
2402 return 0;
2405 /* write Power Management Control/Status register */
2406 static int pt_pmcsr_reg_write(struct pt_dev *ptdev,
2407 struct pt_reg_tbl *cfg_entry,
2408 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2410 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2411 uint16_t writable_mask = 0;
2412 uint16_t throughable_mask = 0;
2413 uint16_t pmcsr_mask = (PCI_PM_CTRL_PME_ENABLE |
2414 PCI_PM_CTRL_DATA_SEL_MASK |
2415 PCI_PM_CTRL_PME_STATUS);
2417 /* modify emulate register */
2418 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~pmcsr_mask;
2419 /* ignore it when the requested state neither D3 nor D0 */
2420 if (((*value & PCI_PM_CTRL_STATE_MASK) != PCI_PM_CTRL_STATE_MASK) &&
2421 ((*value & PCI_PM_CTRL_STATE_MASK) != 0))
2422 writable_mask &= ~PCI_PM_CTRL_STATE_MASK;
2424 cfg_entry->data = ((*value & writable_mask) |
2425 (cfg_entry->data & ~writable_mask));
2427 /* create value for writing to I/O device register */
2428 throughable_mask = ~reg->emu_mask & valid_mask;
2429 *value = ((*value & throughable_mask) |
2430 (dev_value & ~throughable_mask));
2432 return 0;
2435 /* write Device Control register */
2436 static int pt_devctrl_reg_write(struct pt_dev *ptdev,
2437 struct pt_reg_tbl *cfg_entry,
2438 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2440 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2441 uint16_t writable_mask = 0;
2442 uint16_t throughable_mask = 0;
2443 uint16_t devctrl_mask = (PCI_EXP_DEVCTL_AUX_PME | 0x8000);
2445 /* modify emulate register */
2446 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~devctrl_mask;
2447 cfg_entry->data = ((*value & writable_mask) |
2448 (cfg_entry->data & ~writable_mask));
2450 /* create value for writing to I/O device register */
2451 throughable_mask = ~reg->emu_mask & valid_mask;
2452 *value = ((*value & throughable_mask) |
2453 (dev_value & ~throughable_mask));
2455 return 0;
2458 /* write Link Control register */
2459 static int pt_linkctrl_reg_write(struct pt_dev *ptdev,
2460 struct pt_reg_tbl *cfg_entry,
2461 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2463 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2464 uint16_t writable_mask = 0;
2465 uint16_t throughable_mask = 0;
2466 uint16_t linkctrl_mask = (PCI_EXP_LNKCTL_ASPM | 0x04 |
2467 PCI_EXP_LNKCTL_DISABLE |
2468 PCI_EXP_LNKCTL_RETRAIN |
2469 0x0400 | 0x0800 | 0xF000);
2471 /* modify emulate register */
2472 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~linkctrl_mask;
2473 cfg_entry->data = ((*value & writable_mask) |
2474 (cfg_entry->data & ~writable_mask));
2476 /* create value for writing to I/O device register */
2477 throughable_mask = ~reg->emu_mask & valid_mask;
2478 *value = ((*value & throughable_mask) |
2479 (dev_value & ~throughable_mask));
2481 return 0;
2484 /* write Device Control2 register */
2485 static int pt_devctrl2_reg_write(struct pt_dev *ptdev,
2486 struct pt_reg_tbl *cfg_entry,
2487 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2489 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2490 uint16_t writable_mask = 0;
2491 uint16_t throughable_mask = 0;
2492 uint16_t devctrl2_mask = 0xFFE0;
2494 /* modify emulate register */
2495 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~devctrl2_mask;
2496 cfg_entry->data = ((*value & writable_mask) |
2497 (cfg_entry->data & ~writable_mask));
2499 /* create value for writing to I/O device register */
2500 throughable_mask = ~reg->emu_mask & valid_mask;
2501 *value = ((*value & throughable_mask) |
2502 (dev_value & ~throughable_mask));
2504 return 0;
2507 /* write Link Control2 register */
2508 static int pt_linkctrl2_reg_write(struct pt_dev *ptdev,
2509 struct pt_reg_tbl *cfg_entry,
2510 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2512 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2513 uint16_t writable_mask = 0;
2514 uint16_t throughable_mask = 0;
2515 uint16_t linkctrl2_mask = (0x0040 | 0xE000);
2517 /* modify emulate register */
2518 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask &
2519 ~linkctrl2_mask;
2520 cfg_entry->data = ((*value & writable_mask) |
2521 (cfg_entry->data & ~writable_mask));
2523 /* create value for writing to I/O device register */
2524 throughable_mask = ~reg->emu_mask & valid_mask;
2525 *value = ((*value & throughable_mask) |
2526 (dev_value & ~throughable_mask));
2528 return 0;
2531 /* write Message Control register */
2532 static int pt_msgctrl_reg_write(struct pt_dev *ptdev,
2533 struct pt_reg_tbl *cfg_entry,
2534 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2536 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2537 uint16_t writable_mask = 0;
2538 uint16_t throughable_mask = 0;
2539 uint16_t old_ctrl = cfg_entry->data;
2540 PCIDevice *pd = (PCIDevice *)ptdev;
2542 /* Currently no support for multi-vector */
2543 if ((*value & PCI_MSI_FLAGS_QSIZE) != 0x0)
2544 PT_LOG("try to set more than 1 vector ctrl %x\n", *value);
2546 /* modify emulate register */
2547 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2548 cfg_entry->data = ((*value & writable_mask) |
2549 (cfg_entry->data & ~writable_mask));
2550 /* update the msi_info too */
2551 ptdev->msi->flags |= cfg_entry->data &
2552 ~(MSI_FLAG_UNINIT | PT_MSI_MAPPED | PCI_MSI_FLAGS_ENABLE);
2554 PT_LOG("old_ctrl:%04xh new_ctrl:%04xh\n", old_ctrl, cfg_entry->data);
2556 /* create value for writing to I/O device register */
2557 throughable_mask = ~reg->emu_mask & valid_mask;
2558 *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
2560 /* update MSI */
2561 if (*value & PCI_MSI_FLAGS_ENABLE)
2563 /* setup MSI pirq for the first time */
2564 if (ptdev->msi->flags & MSI_FLAG_UNINIT)
2566 /* Init physical one */
2567 PT_LOG("setup msi for dev %x\n", pd->devfn);
2568 if (pt_msi_setup(ptdev))
2570 PT_LOG("pt_msi_setup error!!!\n");
2571 return -1;
2573 pt_msi_update(ptdev);
2575 ptdev->msi->flags &= ~MSI_FLAG_UNINIT;
2576 ptdev->msi->flags |= PT_MSI_MAPPED;
2578 ptdev->msi->flags |= PCI_MSI_FLAGS_ENABLE;
2580 else
2581 ptdev->msi->flags &= ~PCI_MSI_FLAGS_ENABLE;
2583 return 0;
2586 /* write Message Address register */
2587 static int pt_msgaddr32_reg_write(struct pt_dev *ptdev,
2588 struct pt_reg_tbl *cfg_entry,
2589 uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
2591 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2592 uint32_t writable_mask = 0;
2593 uint32_t throughable_mask = 0;
2594 uint32_t old_addr = cfg_entry->data;
2596 /* modify emulate register */
2597 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2598 cfg_entry->data = ((*value & writable_mask) |
2599 (cfg_entry->data & ~writable_mask));
2600 /* update the msi_info too */
2601 ptdev->msi->addr_lo = cfg_entry->data;
2603 PT_LOG("old_addr_lo:%08xh new_addr_lo:%08xh\n", old_addr, cfg_entry->data);
2605 /* create value for writing to I/O device register */
2606 throughable_mask = ~reg->emu_mask & valid_mask;
2607 *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
2609 /* update MSI */
2610 if (cfg_entry->data != old_addr)
2612 if (ptdev->msi->flags & PCI_MSI_FLAGS_ENABLE)
2613 pt_msi_update(ptdev);
2616 return 0;
2619 /* write Message Upper Address register */
2620 static int pt_msgaddr64_reg_write(struct pt_dev *ptdev,
2621 struct pt_reg_tbl *cfg_entry,
2622 uint32_t *value, uint32_t dev_value, uint32_t valid_mask)
2624 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2625 uint32_t writable_mask = 0;
2626 uint32_t throughable_mask = 0;
2627 uint32_t old_addr = cfg_entry->data;
2629 /* check whether the type is 64 bit or not */
2630 if (!(ptdev->msi->flags & PCI_MSI_FLAGS_64BIT))
2632 /* exit I/O emulator */
2633 PT_LOG("why comes to Upper Address without 64 bit support??\n");
2634 return -1;
2637 /* modify emulate register */
2638 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2639 cfg_entry->data = ((*value & writable_mask) |
2640 (cfg_entry->data & ~writable_mask));
2641 /* update the msi_info too */
2642 ptdev->msi->addr_hi = cfg_entry->data;
2644 PT_LOG("old_addr_hi:%08xh new_addr_hi:%08xh\n", old_addr, cfg_entry->data);
2646 /* create value for writing to I/O device register */
2647 throughable_mask = ~reg->emu_mask & valid_mask;
2648 *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
2650 /* update MSI */
2651 if (cfg_entry->data != old_addr)
2653 if (ptdev->msi->flags & PCI_MSI_FLAGS_ENABLE)
2654 pt_msi_update(ptdev);
2657 return 0;
2660 /* this function will be called twice (for 32 bit and 64 bit type) */
2661 /* write Message Data register */
2662 static int pt_msgdata_reg_write(struct pt_dev *ptdev,
2663 struct pt_reg_tbl *cfg_entry,
2664 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2666 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2667 uint16_t writable_mask = 0;
2668 uint16_t throughable_mask = 0;
2669 uint16_t old_data = cfg_entry->data;
2670 uint32_t flags = ptdev->msi->flags;
2671 uint32_t offset = reg->offset;
2673 /* check the offset whether matches the type or not */
2674 if (!((offset == PCI_MSI_DATA_64) && (flags & PCI_MSI_FLAGS_64BIT)) &&
2675 !((offset == PCI_MSI_DATA_32) && !(flags & PCI_MSI_FLAGS_64BIT)))
2677 /* exit I/O emulator */
2678 PT_LOG("Error: the offset is not match with the 32/64 bit type!!\n");
2679 return -1;
2682 /* modify emulate register */
2683 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2684 cfg_entry->data = ((*value & writable_mask) |
2685 (cfg_entry->data & ~writable_mask));
2686 /* update the msi_info too */
2687 ptdev->msi->data = cfg_entry->data;
2689 PT_LOG("old_data:%04xh new_data:%04xh\n", old_data, cfg_entry->data);
2691 /* create value for writing to I/O device register */
2692 throughable_mask = ~reg->emu_mask & valid_mask;
2693 *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
2695 /* update MSI */
2696 if (cfg_entry->data != old_data)
2698 if (flags & PCI_MSI_FLAGS_ENABLE)
2699 pt_msi_update(ptdev);
2702 return 0;
2705 /* write Message Control register for MSI-X */
2706 static int pt_msixctrl_reg_write(struct pt_dev *ptdev,
2707 struct pt_reg_tbl *cfg_entry,
2708 uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
2710 struct pt_reg_info_tbl *reg = cfg_entry->reg;
2711 uint16_t writable_mask = 0;
2712 uint16_t throughable_mask = 0;
2713 uint16_t old_ctrl = cfg_entry->data;
2715 /* modify emulate register */
2716 writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
2717 cfg_entry->data = ((*value & writable_mask) |
2718 (cfg_entry->data & ~writable_mask));
2720 PT_LOG("old_ctrl:%04xh new_ctrl:%04xh\n", old_ctrl, cfg_entry->data);
2722 /* create value for writing to I/O device register */
2723 throughable_mask = ~reg->emu_mask & valid_mask;
2724 *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask));
2726 /* update MSI-X */
2727 if ((*value & PCI_MSIX_ENABLE) && !(*value & PCI_MSIX_MASK))
2728 pt_msix_update(ptdev);
2730 ptdev->msix->enabled = !!(*value & PCI_MSIX_ENABLE);
2732 return 0;
2735 struct pt_dev * register_real_device(PCIBus *e_bus,
2736 const char *e_dev_name, int e_devfn, uint8_t r_bus, uint8_t r_dev,
2737 uint8_t r_func, uint32_t machine_irq, struct pci_access *pci_access)
2739 int rc = -1, i;
2740 struct pt_dev *assigned_device = NULL;
2741 struct pci_dev *pci_dev;
2742 uint8_t e_device, e_intx;
2743 struct pci_config_cf8 machine_bdf;
2744 int free_pci_slot = -1;
2746 PT_LOG("Assigning real physical device %02x:%02x.%x ...\n",
2747 r_bus, r_dev, r_func);
2749 /* Find real device structure */
2750 for (pci_dev = pci_access->devices; pci_dev != NULL;
2751 pci_dev = pci_dev->next)
2753 if ((r_bus == pci_dev->bus) && (r_dev == pci_dev->dev)
2754 && (r_func == pci_dev->func))
2755 break;
2757 if ( pci_dev == NULL )
2759 PT_LOG("Error: couldn't locate device in libpci structures\n");
2760 return NULL;
2762 pci_fill_info(pci_dev, PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES);
2764 if ( e_devfn == PT_VIRT_DEVFN_AUTO ) {
2765 /*indicate a static assignment(not hotplug), so find a free PCI hot plug slot */
2766 free_pci_slot = __insert_to_pci_slot(r_bus, r_dev, r_func, 0);
2767 if ( free_pci_slot > 0 )
2768 e_devfn = free_pci_slot << 3;
2769 else
2770 PT_LOG("Error: no free virtual PCI hot plug slot, thus no live migration.\n");
2773 /* Register device */
2774 assigned_device = (struct pt_dev *) pci_register_device(e_bus, e_dev_name,
2775 sizeof(struct pt_dev), e_devfn,
2776 pt_pci_read_config, pt_pci_write_config);
2777 if ( assigned_device == NULL )
2779 PT_LOG("Error: couldn't register real device\n");
2780 return NULL;
2783 if ( free_pci_slot > 0 )
2784 dpci_infos.php_devs[PCI_TO_PHP_SLOT(free_pci_slot)].pt_dev = assigned_device;
2786 assigned_device->pci_dev = pci_dev;
2788 /* Assign device */
2789 machine_bdf.reg = 0;
2790 machine_bdf.bus = r_bus;
2791 machine_bdf.dev = r_dev;
2792 machine_bdf.func = r_func;
2793 rc = xc_assign_device(xc_handle, domid, machine_bdf.value);
2794 if ( rc < 0 )
2795 PT_LOG("Error: xc_assign_device error %d\n", rc);
2797 /* Initialize virtualized PCI configuration (Extended 256 Bytes) */
2798 for ( i = 0; i < PCI_CONFIG_SIZE; i++ )
2799 assigned_device->dev.config[i] = pci_read_byte(pci_dev, i);
2801 /* Handle real device's MMIO/PIO BARs */
2802 pt_register_regions(assigned_device);
2804 /* reinitialize each config register to be emulated */
2805 rc = pt_config_init(assigned_device);
2806 if ( rc < 0 ) {
2807 return NULL;
2810 /* Bind interrupt */
2811 if (!assigned_device->dev.config[0x3d])
2812 goto out;
2814 e_device = (assigned_device->dev.devfn >> 3) & 0x1f;
2815 /* fix virtual interrupt pin to INTA# */
2816 e_intx = 0;
2818 if ( PT_MACHINE_IRQ_AUTO == machine_irq )
2820 int pirq = pci_dev->irq;
2822 machine_irq = pci_dev->irq;
2823 rc = xc_physdev_map_pirq(xc_handle, domid, machine_irq, &pirq);
2825 if ( rc )
2827 /* TBD: unregister device in case of an error */
2828 PT_LOG("Error: Mapping irq failed, rc = %d\n", rc);
2830 else
2831 machine_irq = pirq;
2834 /* bind machine_irq to device */
2835 if ( 0 != machine_irq )
2837 rc = xc_domain_bind_pt_pci_irq(xc_handle, domid, machine_irq, 0,
2838 e_device, e_intx);
2839 if ( rc < 0 )
2841 /* TBD: unregister device in case of an error */
2842 PT_LOG("Error: Binding of interrupt failed! rc=%d\n", rc);
2845 else {
2846 /* Disable PCI intx assertion (turn on bit10 of devctl) */
2847 assigned_device->dev.config[0x05] |= 0x04;
2848 pci_write_word(pci_dev, 0x04,
2849 *(uint16_t *)(&assigned_device->dev.config[0x04]));
2852 out:
2853 PT_LOG("Real physical device %02x:%02x.%x registered successfuly!\n",
2854 r_bus, r_dev, r_func);
2856 return assigned_device;
2859 int unregister_real_device(int php_slot)
2861 struct php_dev *php_dev;
2862 struct pci_dev *pci_dev;
2863 uint8_t e_device, e_intx;
2864 struct pt_dev *assigned_device = NULL;
2865 uint32_t machine_irq;
2866 uint32_t bdf = 0;
2867 int rc = -1;
2869 if ( php_slot < 0 || php_slot >= PHP_SLOT_LEN )
2870 return -1;
2872 php_dev = &dpci_infos.php_devs[php_slot];
2873 assigned_device = php_dev->pt_dev;
2875 if ( !assigned_device || !php_dev->valid )
2876 return -1;
2878 pci_dev = assigned_device->pci_dev;
2880 /* hide pci dev from qemu */
2881 pci_hide_device((PCIDevice*)assigned_device);
2883 /* Unbind interrupt */
2884 e_device = (assigned_device->dev.devfn >> 3) & 0x1f;
2885 /* fix virtual interrupt pin to INTA# */
2886 e_intx = 0;
2887 machine_irq = pci_dev->irq;
2889 if ( machine_irq != 0 ) {
2890 rc = xc_domain_unbind_pt_irq(xc_handle, domid, machine_irq, PT_IRQ_TYPE_PCI, 0,
2891 e_device, e_intx, 0);
2892 if ( rc < 0 )
2894 /* TBD: unregister device in case of an error */
2895 PT_LOG("Error: Unbinding of interrupt failed! rc=%d\n", rc);
2899 /* delete all emulated config registers */
2900 pt_config_delete(assigned_device);
2902 /* unregister real device's MMIO/PIO BARs */
2903 pt_unregister_regions(assigned_device);
2905 /* deassign the dev to dom0 */
2906 bdf |= (pci_dev->bus & 0xff) << 16;
2907 bdf |= (pci_dev->dev & 0x1f) << 11;
2908 bdf |= (pci_dev->func & 0x1f) << 8;
2909 if ( (rc = xc_deassign_device(xc_handle, domid, bdf)) != 0)
2910 PT_LOG("Error: Revoking the device failed! rc=%d\n", rc);
2912 /* mark this slot as free */
2913 php_dev->valid = 0;
2914 php_dev->pt_dev = NULL;
2915 qemu_free(assigned_device);
2917 return 0;
2920 int power_on_php_slot(int php_slot)
2922 struct php_dev *php_dev = &dpci_infos.php_devs[php_slot];
2923 int pci_slot = php_slot + PHP_SLOT_START;
2924 struct pt_dev *pt_dev;
2925 pt_dev =
2926 register_real_device(dpci_infos.e_bus,
2927 "DIRECT PCI",
2928 pci_slot << 3,
2929 php_dev->r_bus,
2930 php_dev->r_dev,
2931 php_dev->r_func,
2932 PT_MACHINE_IRQ_AUTO,
2933 dpci_infos.pci_access);
2935 php_dev->pt_dev = pt_dev;
2937 return 0;
2941 int power_off_php_slot(int php_slot)
2943 return unregister_real_device(php_slot);
2946 int pt_init(PCIBus *e_bus, char *direct_pci)
2948 int seg, b, d, f, php_slot = 0;
2949 struct pt_dev *pt_dev;
2950 struct pci_access *pci_access;
2951 char *vslots;
2952 char slot_str[8];
2954 /* Initialize libpci */
2955 pci_access = pci_alloc();
2956 if ( pci_access == NULL )
2958 PT_LOG("pci_access is NULL\n");
2959 return -1;
2961 pci_init(pci_access);
2962 pci_scan_bus(pci_access);
2964 memset(&dpci_infos, 0, sizeof(struct dpci_infos));
2965 dpci_infos.pci_access = pci_access;
2966 dpci_infos.e_bus = e_bus;
2968 if ( strlen(direct_pci) == 0 ) {
2969 return 0;
2972 /* the virtual pci slots of all pass-through devs
2973 * with hex format: xx;xx...;
2974 */
2975 vslots = qemu_mallocz ( strlen(direct_pci) / 3 );
2977 /* Assign given devices to guest */
2978 while ( next_bdf(&direct_pci, &seg, &b, &d, &f) )
2980 /* Register real device with the emulated bus */
2981 pt_dev = register_real_device(e_bus, "DIRECT PCI", PT_VIRT_DEVFN_AUTO,
2982 b, d, f, PT_MACHINE_IRQ_AUTO, pci_access);
2983 if ( pt_dev == NULL )
2985 PT_LOG("Error: Registration failed (%02x:%02x.%x)\n", b, d, f);
2986 return -1;
2989 /* Record the virtual slot info */
2990 if ( php_slot < PHP_SLOT_LEN &&
2991 dpci_infos.php_devs[php_slot].pt_dev == pt_dev )
2993 sprintf(slot_str, "0x%x;", PHP_TO_PCI_SLOT(php_slot));
2995 else
2996 sprintf(slot_str, "0x%x;", 0);
2998 strcat(vslots, slot_str);
2999 php_slot++;
3002 /* Write virtual slots info to xenstore for Control panel use */
3003 xenstore_write_vslots(vslots);
3005 qemu_free(vslots);
3007 /* Success */
3008 return 0;