ia64/xen-unstable

view xen/arch/x86/domain.c @ 14175:5943a8314d69

[XEN] Make the compat-mode l4 page table look more like a page table
and remove some special-case code in the shadows.
Signed-off-by: Tim Deegan <Tim.Deegan@xensource.com>
author Tim Deegan <Tim.Deegan@xensource.com>
date Wed Feb 28 13:17:27 2007 +0000 (2007-02-28)
parents 1e5a83fb928b
children f3271ae6a485
line source
1 /******************************************************************************
2 * arch/x86/domain.c
3 *
4 * x86-specific domain handling (e.g., register setup and context switching).
5 */
7 /*
8 * Copyright (C) 1995 Linus Torvalds
9 *
10 * Pentium III FXSR, SSE support
11 * Gareth Hughes <gareth@valinux.com>, May 2000
12 */
14 #include <xen/config.h>
15 #include <xen/init.h>
16 #include <xen/lib.h>
17 #include <xen/errno.h>
18 #include <xen/sched.h>
19 #include <xen/domain.h>
20 #include <xen/smp.h>
21 #include <xen/delay.h>
22 #include <xen/softirq.h>
23 #include <xen/grant_table.h>
24 #include <xen/iocap.h>
25 #include <xen/kernel.h>
26 #include <xen/multicall.h>
27 #include <xen/irq.h>
28 #include <xen/event.h>
29 #include <xen/console.h>
30 #include <xen/percpu.h>
31 #include <asm/regs.h>
32 #include <asm/mc146818rtc.h>
33 #include <asm/system.h>
34 #include <asm/io.h>
35 #include <asm/processor.h>
36 #include <asm/desc.h>
37 #include <asm/i387.h>
38 #include <asm/mpspec.h>
39 #include <asm/ldt.h>
40 #include <asm/paging.h>
41 #include <asm/hvm/hvm.h>
42 #include <asm/hvm/support.h>
43 #include <asm/msr.h>
44 #ifdef CONFIG_COMPAT
45 #include <compat/vcpu.h>
46 #endif
48 DEFINE_PER_CPU(struct vcpu *, curr_vcpu);
50 static void paravirt_ctxt_switch_from(struct vcpu *v);
51 static void paravirt_ctxt_switch_to(struct vcpu *v);
53 static void vcpu_destroy_pagetables(struct vcpu *v);
55 static void continue_idle_domain(struct vcpu *v)
56 {
57 reset_stack_and_jump(idle_loop);
58 }
60 static void continue_nonidle_domain(struct vcpu *v)
61 {
62 reset_stack_and_jump(ret_from_intr);
63 }
65 static void default_idle(void)
66 {
67 local_irq_disable();
68 if ( !softirq_pending(smp_processor_id()) )
69 safe_halt();
70 else
71 local_irq_enable();
72 }
74 void idle_loop(void)
75 {
76 for ( ; ; )
77 {
78 page_scrub_schedule_work();
79 default_idle();
80 do_softirq();
81 }
82 }
84 void startup_cpu_idle_loop(void)
85 {
86 struct vcpu *v = current;
88 ASSERT(is_idle_vcpu(v));
89 cpu_set(smp_processor_id(), v->domain->domain_dirty_cpumask);
90 cpu_set(smp_processor_id(), v->vcpu_dirty_cpumask);
92 reset_stack_and_jump(idle_loop);
93 }
95 void dump_pageframe_info(struct domain *d)
96 {
97 struct page_info *page;
99 printk("Memory pages belonging to domain %u:\n", d->domain_id);
101 if ( d->tot_pages >= 10 )
102 {
103 printk(" DomPage list too long to display\n");
104 }
105 else
106 {
107 list_for_each_entry ( page, &d->page_list, list )
108 {
109 printk(" DomPage %p: mfn=%p, caf=%08x, taf=%" PRtype_info "\n",
110 _p(page_to_maddr(page)), _p(page_to_mfn(page)),
111 page->count_info, page->u.inuse.type_info);
112 }
113 }
115 list_for_each_entry ( page, &d->xenpage_list, list )
116 {
117 printk(" XenPage %p: mfn=%p, caf=%08x, taf=%" PRtype_info "\n",
118 _p(page_to_maddr(page)), _p(page_to_mfn(page)),
119 page->count_info, page->u.inuse.type_info);
120 }
121 }
123 struct vcpu *alloc_vcpu_struct(void)
124 {
125 struct vcpu *v;
126 if ( (v = xmalloc(struct vcpu)) != NULL )
127 memset(v, 0, sizeof(*v));
128 return v;
129 }
131 void free_vcpu_struct(struct vcpu *v)
132 {
133 xfree(v);
134 }
136 #ifdef CONFIG_COMPAT
138 int setup_arg_xlat_area(struct vcpu *v, l4_pgentry_t *l4tab)
139 {
140 struct domain *d = v->domain;
141 unsigned i;
142 struct page_info *pg;
144 if ( !d->arch.mm_arg_xlat_l3 )
145 {
146 pg = alloc_domheap_page(NULL);
147 if ( !pg )
148 return -ENOMEM;
149 d->arch.mm_arg_xlat_l3 = clear_page(page_to_virt(pg));
150 }
152 l4tab[l4_table_offset(COMPAT_ARG_XLAT_VIRT_BASE)] =
153 l4e_from_paddr(__pa(d->arch.mm_arg_xlat_l3), __PAGE_HYPERVISOR);
155 for ( i = 0; i < COMPAT_ARG_XLAT_PAGES; ++i )
156 {
157 unsigned long va = COMPAT_ARG_XLAT_VIRT_START(v->vcpu_id) + i * PAGE_SIZE;
158 l2_pgentry_t *l2tab;
159 l1_pgentry_t *l1tab;
161 if ( !l3e_get_intpte(d->arch.mm_arg_xlat_l3[l3_table_offset(va)]) )
162 {
163 pg = alloc_domheap_page(NULL);
164 if ( !pg )
165 return -ENOMEM;
166 clear_page(page_to_virt(pg));
167 d->arch.mm_arg_xlat_l3[l3_table_offset(va)] = l3e_from_page(pg, __PAGE_HYPERVISOR);
168 }
169 l2tab = l3e_to_l2e(d->arch.mm_arg_xlat_l3[l3_table_offset(va)]);
170 if ( !l2e_get_intpte(l2tab[l2_table_offset(va)]) )
171 {
172 pg = alloc_domheap_page(NULL);
173 if ( !pg )
174 return -ENOMEM;
175 clear_page(page_to_virt(pg));
176 l2tab[l2_table_offset(va)] = l2e_from_page(pg, __PAGE_HYPERVISOR);
177 }
178 l1tab = l2e_to_l1e(l2tab[l2_table_offset(va)]);
179 BUG_ON(l1e_get_intpte(l1tab[l1_table_offset(va)]));
180 pg = alloc_domheap_page(NULL);
181 if ( !pg )
182 return -ENOMEM;
183 l1tab[l1_table_offset(va)] = l1e_from_page(pg, PAGE_HYPERVISOR);
184 }
186 return 0;
187 }
189 static void release_arg_xlat_area(struct domain *d)
190 {
191 if ( d->arch.mm_arg_xlat_l3 )
192 {
193 unsigned l3;
195 for ( l3 = 0; l3 < L3_PAGETABLE_ENTRIES; ++l3 )
196 {
197 if ( l3e_get_intpte(d->arch.mm_arg_xlat_l3[l3]) )
198 {
199 l2_pgentry_t *l2tab = l3e_to_l2e(d->arch.mm_arg_xlat_l3[l3]);
200 unsigned l2;
202 for ( l2 = 0; l2 < L2_PAGETABLE_ENTRIES; ++l2 )
203 {
204 if ( l2e_get_intpte(l2tab[l2]) )
205 {
206 l1_pgentry_t *l1tab = l2e_to_l1e(l2tab[l2]);
207 unsigned l1;
209 for ( l1 = 0; l1 < L1_PAGETABLE_ENTRIES; ++l1 )
210 {
211 if ( l1e_get_intpte(l1tab[l1]) )
212 free_domheap_page(l1e_get_page(l1tab[l1]));
213 }
214 free_domheap_page(l2e_get_page(l2tab[l2]));
215 }
216 }
217 free_domheap_page(l3e_get_page(d->arch.mm_arg_xlat_l3[l3]));
218 }
219 }
220 free_domheap_page(virt_to_page(d->arch.mm_arg_xlat_l3));
221 }
222 }
224 static int setup_compat_l4(struct vcpu *v)
225 {
226 struct page_info *pg = alloc_domheap_page(NULL);
227 l4_pgentry_t *l4tab;
228 int rc;
230 if ( !pg )
231 return -ENOMEM;
233 /* This page needs to look like a pagetable so that it can be shadowed */
234 pg->u.inuse.type_info = PGT_l4_page_table|PGT_validated;
236 l4tab = copy_page(page_to_virt(pg), idle_pg_table);
237 l4tab[l4_table_offset(LINEAR_PT_VIRT_START)] =
238 l4e_from_page(pg, __PAGE_HYPERVISOR);
239 l4tab[l4_table_offset(PERDOMAIN_VIRT_START)] =
240 l4e_from_paddr(__pa(v->domain->arch.mm_perdomain_l3), __PAGE_HYPERVISOR);
241 v->arch.guest_table = pagetable_from_page(pg);
242 v->arch.guest_table_user = v->arch.guest_table;
244 if ( (rc = setup_arg_xlat_area(v, l4tab)) < 0 )
245 {
246 free_domheap_page(pg);
247 return rc;
248 }
250 return 0;
251 }
253 static void release_compat_l4(struct vcpu *v)
254 {
255 free_domheap_page(pagetable_get_page(v->arch.guest_table));
256 v->arch.guest_table = pagetable_null();
257 v->arch.guest_table_user = pagetable_null();
258 }
260 static inline int may_switch_mode(struct domain *d)
261 {
262 return (d->tot_pages == 0);
263 }
265 int switch_native(struct domain *d)
266 {
267 l1_pgentry_t gdt_l1e;
268 unsigned int vcpuid;
270 if ( d == NULL )
271 return -EINVAL;
272 if ( !may_switch_mode(d) )
273 return -EACCES;
274 if ( !IS_COMPAT(d) )
275 return 0;
277 clear_bit(_DOMF_compat, &d->domain_flags);
278 release_arg_xlat_area(d);
280 /* switch gdt */
281 gdt_l1e = l1e_from_page(virt_to_page(gdt_table), PAGE_HYPERVISOR);
282 for ( vcpuid = 0; vcpuid < MAX_VIRT_CPUS; vcpuid++ )
283 {
284 d->arch.mm_perdomain_pt[((vcpuid << GDT_LDT_VCPU_SHIFT) +
285 FIRST_RESERVED_GDT_PAGE)] = gdt_l1e;
286 if (d->vcpu[vcpuid])
287 release_compat_l4(d->vcpu[vcpuid]);
288 }
290 d->arch.physaddr_bitsize = 64;
292 return 0;
293 }
295 int switch_compat(struct domain *d)
296 {
297 l1_pgentry_t gdt_l1e;
298 unsigned int vcpuid;
300 if ( d == NULL )
301 return -EINVAL;
302 if ( compat_disabled )
303 return -ENOSYS;
304 if ( !may_switch_mode(d) )
305 return -EACCES;
306 if ( IS_COMPAT(d) )
307 return 0;
309 set_bit(_DOMF_compat, &d->domain_flags);
311 /* switch gdt */
312 gdt_l1e = l1e_from_page(virt_to_page(compat_gdt_table), PAGE_HYPERVISOR);
313 for ( vcpuid = 0; vcpuid < MAX_VIRT_CPUS; vcpuid++ )
314 {
315 d->arch.mm_perdomain_pt[((vcpuid << GDT_LDT_VCPU_SHIFT) +
316 FIRST_RESERVED_GDT_PAGE)] = gdt_l1e;
317 if (d->vcpu[vcpuid]
318 && setup_compat_l4(d->vcpu[vcpuid]) != 0)
319 return -ENOMEM;
320 }
322 d->arch.physaddr_bitsize =
323 fls((1UL << 32) - HYPERVISOR_COMPAT_VIRT_START(d)) - 1
324 + (PAGE_SIZE - 2);
326 return 0;
327 }
329 #else
330 #define release_arg_xlat_area(d) ((void)0)
331 #define setup_compat_l4(v) 0
332 #define release_compat_l4(v) ((void)0)
333 #endif
335 int vcpu_initialise(struct vcpu *v)
336 {
337 struct domain *d = v->domain;
338 int rc;
340 v->arch.flags = TF_kernel_mode;
342 pae_l3_cache_init(&v->arch.pae_l3_cache);
344 paging_vcpu_init(v);
346 if ( is_hvm_domain(d) )
347 {
348 if ( (rc = hvm_vcpu_initialise(v)) != 0 )
349 return rc;
350 }
351 else
352 {
353 /* PV guests get an emulated PIT too for video BIOSes to use. */
354 if ( !is_idle_domain(d) && (v->vcpu_id == 0) )
355 pit_init(v, cpu_khz);
357 v->arch.schedule_tail = continue_nonidle_domain;
358 v->arch.ctxt_switch_from = paravirt_ctxt_switch_from;
359 v->arch.ctxt_switch_to = paravirt_ctxt_switch_to;
361 if ( is_idle_domain(d) )
362 {
363 v->arch.schedule_tail = continue_idle_domain;
364 v->arch.cr3 = __pa(idle_pg_table);
365 }
366 }
368 v->arch.perdomain_ptes =
369 d->arch.mm_perdomain_pt + (v->vcpu_id << GDT_LDT_VCPU_SHIFT);
371 if ( IS_COMPAT(d) && (rc = setup_compat_l4(v)) != 0 )
372 return rc;
374 return 0;
375 }
377 void vcpu_destroy(struct vcpu *v)
378 {
379 if ( IS_COMPAT(v->domain) )
380 release_compat_l4(v);
381 }
383 int arch_domain_create(struct domain *d)
384 {
385 #ifdef __x86_64__
386 struct page_info *pg;
387 int i;
388 #endif
389 l1_pgentry_t gdt_l1e;
390 int vcpuid, pdpt_order;
391 int rc = -ENOMEM;
393 pdpt_order = get_order_from_bytes(PDPT_L1_ENTRIES * sizeof(l1_pgentry_t));
394 d->arch.mm_perdomain_pt = alloc_xenheap_pages(pdpt_order);
395 if ( d->arch.mm_perdomain_pt == NULL )
396 goto fail;
397 memset(d->arch.mm_perdomain_pt, 0, PAGE_SIZE << pdpt_order);
399 /*
400 * Map Xen segments into every VCPU's GDT, irrespective of whether every
401 * VCPU will actually be used. This avoids an NMI race during context
402 * switch: if we take an interrupt after switching CR3 but before switching
403 * GDT, and the old VCPU# is invalid in the new domain, we would otherwise
404 * try to load CS from an invalid table.
405 */
406 gdt_l1e = l1e_from_page(virt_to_page(gdt_table), PAGE_HYPERVISOR);
407 for ( vcpuid = 0; vcpuid < MAX_VIRT_CPUS; vcpuid++ )
408 d->arch.mm_perdomain_pt[((vcpuid << GDT_LDT_VCPU_SHIFT) +
409 FIRST_RESERVED_GDT_PAGE)] = gdt_l1e;
411 #if defined(__i386__)
413 mapcache_init(d);
415 #else /* __x86_64__ */
417 if ( (pg = alloc_domheap_page(NULL)) == NULL )
418 goto fail;
419 d->arch.mm_perdomain_l2 = clear_page(page_to_virt(pg));
420 for ( i = 0; i < (1 << pdpt_order); i++ )
421 d->arch.mm_perdomain_l2[l2_table_offset(PERDOMAIN_VIRT_START)+i] =
422 l2e_from_page(virt_to_page(d->arch.mm_perdomain_pt)+i,
423 __PAGE_HYPERVISOR);
425 if ( (pg = alloc_domheap_page(NULL)) == NULL )
426 goto fail;
427 d->arch.mm_perdomain_l3 = clear_page(page_to_virt(pg));
428 d->arch.mm_perdomain_l3[l3_table_offset(PERDOMAIN_VIRT_START)] =
429 l3e_from_page(virt_to_page(d->arch.mm_perdomain_l2),
430 __PAGE_HYPERVISOR);
432 #endif /* __x86_64__ */
434 #ifdef CONFIG_COMPAT
435 HYPERVISOR_COMPAT_VIRT_START(d) = __HYPERVISOR_COMPAT_VIRT_START;
436 #endif
438 paging_domain_init(d);
440 if ( !is_idle_domain(d) )
441 {
442 d->arch.ioport_caps =
443 rangeset_new(d, "I/O Ports", RANGESETF_prettyprint_hex);
444 if ( d->arch.ioport_caps == NULL )
445 goto fail;
447 if ( (d->shared_info = alloc_xenheap_page()) == NULL )
448 goto fail;
450 memset(d->shared_info, 0, PAGE_SIZE);
451 share_xen_page_with_guest(
452 virt_to_page(d->shared_info), d, XENSHARE_writable);
453 }
455 return is_hvm_domain(d) ? hvm_domain_initialise(d) : 0;
457 fail:
458 free_xenheap_page(d->shared_info);
459 #ifdef __x86_64__
460 free_domheap_page(virt_to_page(d->arch.mm_perdomain_l2));
461 free_domheap_page(virt_to_page(d->arch.mm_perdomain_l3));
462 #endif
463 free_xenheap_pages(d->arch.mm_perdomain_pt, pdpt_order);
464 return rc;
465 }
467 void arch_domain_destroy(struct domain *d)
468 {
469 struct vcpu *v;
471 if ( is_hvm_domain(d) )
472 {
473 for_each_vcpu ( d, v )
474 hvm_vcpu_destroy(v);
475 hvm_domain_destroy(d);
476 }
478 paging_final_teardown(d);
480 free_xenheap_pages(
481 d->arch.mm_perdomain_pt,
482 get_order_from_bytes(PDPT_L1_ENTRIES * sizeof(l1_pgentry_t)));
484 #ifdef __x86_64__
485 free_domheap_page(virt_to_page(d->arch.mm_perdomain_l2));
486 free_domheap_page(virt_to_page(d->arch.mm_perdomain_l3));
487 #endif
489 if ( IS_COMPAT(d) )
490 release_arg_xlat_area(d);
492 free_xenheap_page(d->shared_info);
493 }
495 /* This is called by arch_final_setup_guest and do_boot_vcpu */
496 int arch_set_info_guest(
497 struct vcpu *v, vcpu_guest_context_u c)
498 {
499 struct domain *d = v->domain;
500 #ifdef CONFIG_COMPAT
501 #define c(fld) (!IS_COMPAT(d) ? (c.nat->fld) : (c.cmp->fld))
502 #else
503 #define c(fld) (c.nat->fld)
504 #endif
505 unsigned long cr3_pfn = INVALID_MFN;
506 unsigned long flags = c(flags);
507 int i, rc;
509 if ( !is_hvm_vcpu(v) )
510 {
511 if ( !IS_COMPAT(d) )
512 {
513 fixup_guest_stack_selector(d, c.nat->user_regs.ss);
514 fixup_guest_stack_selector(d, c.nat->kernel_ss);
515 fixup_guest_code_selector(d, c.nat->user_regs.cs);
516 #ifdef __i386__
517 fixup_guest_code_selector(d, c.nat->event_callback_cs);
518 fixup_guest_code_selector(d, c.nat->failsafe_callback_cs);
519 #endif
521 for ( i = 0; i < 256; i++ )
522 fixup_guest_code_selector(d, c.nat->trap_ctxt[i].cs);
524 /* LDT safety checks. */
525 if ( ((c.nat->ldt_base & (PAGE_SIZE-1)) != 0) ||
526 (c.nat->ldt_ents > 8192) ||
527 !array_access_ok(c.nat->ldt_base,
528 c.nat->ldt_ents,
529 LDT_ENTRY_SIZE) )
530 return -EINVAL;
531 }
532 #ifdef CONFIG_COMPAT
533 else
534 {
535 fixup_guest_stack_selector(d, c.cmp->user_regs.ss);
536 fixup_guest_stack_selector(d, c.cmp->kernel_ss);
537 fixup_guest_code_selector(d, c.cmp->user_regs.cs);
538 fixup_guest_code_selector(d, c.cmp->event_callback_cs);
539 fixup_guest_code_selector(d, c.cmp->failsafe_callback_cs);
541 for ( i = 0; i < 256; i++ )
542 fixup_guest_code_selector(d, c.cmp->trap_ctxt[i].cs);
544 /* LDT safety checks. */
545 if ( ((c.cmp->ldt_base & (PAGE_SIZE-1)) != 0) ||
546 (c.cmp->ldt_ents > 8192) ||
547 !compat_array_access_ok(c.cmp->ldt_base,
548 c.cmp->ldt_ents,
549 LDT_ENTRY_SIZE) )
550 return -EINVAL;
551 }
552 #endif
553 }
555 clear_bit(_VCPUF_fpu_initialised, &v->vcpu_flags);
556 if ( flags & VGCF_I387_VALID )
557 set_bit(_VCPUF_fpu_initialised, &v->vcpu_flags);
559 v->arch.flags &= ~TF_kernel_mode;
560 if ( (flags & VGCF_in_kernel) || is_hvm_vcpu(v)/*???*/ )
561 v->arch.flags |= TF_kernel_mode;
563 if ( !IS_COMPAT(v->domain) )
564 memcpy(&v->arch.guest_context, c.nat, sizeof(*c.nat));
565 #ifdef CONFIG_COMPAT
566 else
567 {
568 XLAT_vcpu_guest_context(&v->arch.guest_context, c.cmp);
569 }
570 #endif
572 /* Only CR0.TS is modifiable by guest or admin. */
573 v->arch.guest_context.ctrlreg[0] &= X86_CR0_TS;
574 v->arch.guest_context.ctrlreg[0] |= read_cr0() & ~X86_CR0_TS;
576 init_int80_direct_trap(v);
578 if ( !is_hvm_vcpu(v) )
579 {
580 /* IOPL privileges are virtualised. */
581 v->arch.iopl = (v->arch.guest_context.user_regs.eflags >> 12) & 3;
582 v->arch.guest_context.user_regs.eflags &= ~EF_IOPL;
584 /* Ensure real hardware interrupts are enabled. */
585 v->arch.guest_context.user_regs.eflags |= EF_IE;
586 }
587 else
588 {
589 hvm_load_cpu_guest_regs(v, &v->arch.guest_context.user_regs);
590 }
592 if ( test_bit(_VCPUF_initialised, &v->vcpu_flags) )
593 return 0;
595 memset(v->arch.guest_context.debugreg, 0,
596 sizeof(v->arch.guest_context.debugreg));
597 for ( i = 0; i < 8; i++ )
598 (void)set_debugreg(v, i, c(debugreg[i]));
600 if ( v->vcpu_id == 0 )
601 d->vm_assist = c(vm_assist);
603 if ( !is_hvm_vcpu(v) )
604 {
605 if ( !IS_COMPAT(d) )
606 rc = (int)set_gdt(v, c.nat->gdt_frames, c.nat->gdt_ents);
607 #ifdef CONFIG_COMPAT
608 else
609 {
610 unsigned long gdt_frames[ARRAY_SIZE(c.cmp->gdt_frames)];
611 unsigned int i, n = (c.cmp->gdt_ents + 511) / 512;
613 if ( n > ARRAY_SIZE(c.cmp->gdt_frames) )
614 return -EINVAL;
615 for ( i = 0; i < n; ++i )
616 gdt_frames[i] = c.cmp->gdt_frames[i];
617 rc = (int)set_gdt(v, gdt_frames, c.cmp->gdt_ents);
618 }
619 #endif
620 if ( rc != 0 )
621 return rc;
623 if ( !IS_COMPAT(d) )
624 {
625 cr3_pfn = gmfn_to_mfn(d, xen_cr3_to_pfn(c.nat->ctrlreg[3]));
627 if ( paging_mode_refcounts(d)
628 ? !get_page(mfn_to_page(cr3_pfn), d)
629 : !get_page_and_type(mfn_to_page(cr3_pfn), d,
630 PGT_base_page_table) )
631 {
632 destroy_gdt(v);
633 return -EINVAL;
634 }
636 v->arch.guest_table = pagetable_from_pfn(cr3_pfn);
637 }
638 #ifdef CONFIG_COMPAT
639 else
640 {
641 l4_pgentry_t *l4tab;
643 cr3_pfn = gmfn_to_mfn(d, compat_cr3_to_pfn(c.cmp->ctrlreg[3]));
645 if ( paging_mode_refcounts(d)
646 ? !get_page(mfn_to_page(cr3_pfn), d)
647 : !get_page_and_type(mfn_to_page(cr3_pfn), d,
648 PGT_l3_page_table) )
649 {
650 destroy_gdt(v);
651 return -EINVAL;
652 }
654 l4tab = __va(pagetable_get_paddr(v->arch.guest_table));
655 *l4tab = l4e_from_pfn(cr3_pfn, _PAGE_PRESENT|_PAGE_RW|_PAGE_USER|_PAGE_ACCESSED);
656 }
657 #endif
658 }
660 if ( v->vcpu_id == 0 )
661 update_domain_wallclock_time(d);
663 /* Don't redo final setup */
664 set_bit(_VCPUF_initialised, &v->vcpu_flags);
666 if ( paging_mode_enabled(d) )
667 paging_update_paging_modes(v);
669 update_cr3(v);
671 return 0;
672 #undef c
673 }
675 int arch_vcpu_reset(struct vcpu *v)
676 {
677 destroy_gdt(v);
678 vcpu_destroy_pagetables(v);
679 return 0;
680 }
682 long
683 arch_do_vcpu_op(
684 int cmd, struct vcpu *v, XEN_GUEST_HANDLE(void) arg)
685 {
686 long rc = 0;
688 switch ( cmd )
689 {
690 case VCPUOP_register_runstate_memory_area:
691 {
692 struct vcpu_register_runstate_memory_area area;
693 struct vcpu_runstate_info runstate;
695 rc = -EFAULT;
696 if ( copy_from_guest(&area, arg, 1) )
697 break;
699 if ( !guest_handle_okay(area.addr.h, 1) )
700 break;
702 rc = 0;
703 runstate_guest(v) = area.addr.h;
705 if ( v == current )
706 {
707 __copy_to_guest(runstate_guest(v), &v->runstate, 1);
708 }
709 else
710 {
711 vcpu_runstate_get(v, &runstate);
712 __copy_to_guest(runstate_guest(v), &runstate, 1);
713 }
715 break;
716 }
718 default:
719 rc = -ENOSYS;
720 break;
721 }
723 return rc;
724 }
726 #ifdef __x86_64__
728 #define loadsegment(seg,value) ({ \
729 int __r = 1; \
730 __asm__ __volatile__ ( \
731 "1: movl %k1,%%" #seg "\n2:\n" \
732 ".section .fixup,\"ax\"\n" \
733 "3: xorl %k0,%k0\n" \
734 " movl %k0,%%" #seg "\n" \
735 " jmp 2b\n" \
736 ".previous\n" \
737 ".section __ex_table,\"a\"\n" \
738 " .align 8\n" \
739 " .quad 1b,3b\n" \
740 ".previous" \
741 : "=r" (__r) : "r" (value), "0" (__r) );\
742 __r; })
744 /*
745 * save_segments() writes a mask of segments which are dirty (non-zero),
746 * allowing load_segments() to avoid some expensive segment loads and
747 * MSR writes.
748 */
749 static DEFINE_PER_CPU(unsigned int, dirty_segment_mask);
750 #define DIRTY_DS 0x01
751 #define DIRTY_ES 0x02
752 #define DIRTY_FS 0x04
753 #define DIRTY_GS 0x08
754 #define DIRTY_FS_BASE 0x10
755 #define DIRTY_GS_BASE_USER 0x20
757 static void load_segments(struct vcpu *n)
758 {
759 struct vcpu_guest_context *nctxt = &n->arch.guest_context;
760 int all_segs_okay = 1;
761 unsigned int dirty_segment_mask, cpu = smp_processor_id();
763 /* Load and clear the dirty segment mask. */
764 dirty_segment_mask = per_cpu(dirty_segment_mask, cpu);
765 per_cpu(dirty_segment_mask, cpu) = 0;
767 /* Either selector != 0 ==> reload. */
768 if ( unlikely((dirty_segment_mask & DIRTY_DS) | nctxt->user_regs.ds) )
769 all_segs_okay &= loadsegment(ds, nctxt->user_regs.ds);
771 /* Either selector != 0 ==> reload. */
772 if ( unlikely((dirty_segment_mask & DIRTY_ES) | nctxt->user_regs.es) )
773 all_segs_okay &= loadsegment(es, nctxt->user_regs.es);
775 /*
776 * Either selector != 0 ==> reload.
777 * Also reload to reset FS_BASE if it was non-zero.
778 */
779 if ( unlikely((dirty_segment_mask & (DIRTY_FS | DIRTY_FS_BASE)) |
780 nctxt->user_regs.fs) )
781 all_segs_okay &= loadsegment(fs, nctxt->user_regs.fs);
783 /*
784 * Either selector != 0 ==> reload.
785 * Also reload to reset GS_BASE if it was non-zero.
786 */
787 if ( unlikely((dirty_segment_mask & (DIRTY_GS | DIRTY_GS_BASE_USER)) |
788 nctxt->user_regs.gs) )
789 {
790 /* Reset GS_BASE with user %gs? */
791 if ( (dirty_segment_mask & DIRTY_GS) || !nctxt->gs_base_user )
792 all_segs_okay &= loadsegment(gs, nctxt->user_regs.gs);
793 }
795 if ( !IS_COMPAT(n->domain) )
796 {
797 /* This can only be non-zero if selector is NULL. */
798 if ( nctxt->fs_base )
799 wrmsr(MSR_FS_BASE,
800 nctxt->fs_base,
801 nctxt->fs_base>>32);
803 /* Most kernels have non-zero GS base, so don't bother testing. */
804 /* (This is also a serialising instruction, avoiding AMD erratum #88.) */
805 wrmsr(MSR_SHADOW_GS_BASE,
806 nctxt->gs_base_kernel,
807 nctxt->gs_base_kernel>>32);
809 /* This can only be non-zero if selector is NULL. */
810 if ( nctxt->gs_base_user )
811 wrmsr(MSR_GS_BASE,
812 nctxt->gs_base_user,
813 nctxt->gs_base_user>>32);
815 /* If in kernel mode then switch the GS bases around. */
816 if ( (n->arch.flags & TF_kernel_mode) )
817 __asm__ __volatile__ ( "swapgs" );
818 }
820 if ( unlikely(!all_segs_okay) )
821 {
822 struct cpu_user_regs *regs = guest_cpu_user_regs();
823 unsigned long *rsp =
824 (n->arch.flags & TF_kernel_mode) ?
825 (unsigned long *)regs->rsp :
826 (unsigned long *)nctxt->kernel_sp;
827 unsigned long cs_and_mask, rflags;
829 if ( IS_COMPAT(n->domain) )
830 {
831 unsigned int *esp = ring_1(regs) ?
832 (unsigned int *)regs->rsp :
833 (unsigned int *)nctxt->kernel_sp;
834 unsigned int cs_and_mask, eflags;
835 int ret = 0;
837 /* CS longword also contains full evtchn_upcall_mask. */
838 cs_and_mask = (unsigned short)regs->cs |
839 ((unsigned int)vcpu_info(n, evtchn_upcall_mask) << 16);
840 /* Fold upcall mask into RFLAGS.IF. */
841 eflags = regs->_eflags & ~X86_EFLAGS_IF;
842 eflags |= !vcpu_info(n, evtchn_upcall_mask) << 9;
844 if ( !ring_1(regs) )
845 {
846 ret = put_user(regs->ss, esp-1);
847 ret |= put_user(regs->_esp, esp-2);
848 esp -= 2;
849 }
851 if ( ret |
852 put_user(eflags, esp-1) |
853 put_user(cs_and_mask, esp-2) |
854 put_user(regs->_eip, esp-3) |
855 put_user(nctxt->user_regs.gs, esp-4) |
856 put_user(nctxt->user_regs.fs, esp-5) |
857 put_user(nctxt->user_regs.es, esp-6) |
858 put_user(nctxt->user_regs.ds, esp-7) )
859 {
860 gdprintk(XENLOG_ERR, "Error while creating compat "
861 "failsafe callback frame.\n");
862 domain_crash(n->domain);
863 }
865 if ( test_bit(_VGCF_failsafe_disables_events,
866 &n->arch.guest_context.flags) )
867 vcpu_info(n, evtchn_upcall_mask) = 1;
869 regs->entry_vector = TRAP_syscall;
870 regs->_eflags &= 0xFFFCBEFFUL;
871 regs->ss = FLAT_COMPAT_KERNEL_SS;
872 regs->_esp = (unsigned long)(esp-7);
873 regs->cs = FLAT_COMPAT_KERNEL_CS;
874 regs->_eip = nctxt->failsafe_callback_eip;
875 return;
876 }
878 if ( !(n->arch.flags & TF_kernel_mode) )
879 toggle_guest_mode(n);
880 else
881 regs->cs &= ~3;
883 /* CS longword also contains full evtchn_upcall_mask. */
884 cs_and_mask = (unsigned long)regs->cs |
885 ((unsigned long)vcpu_info(n, evtchn_upcall_mask) << 32);
887 /* Fold upcall mask into RFLAGS.IF. */
888 rflags = regs->rflags & ~X86_EFLAGS_IF;
889 rflags |= !vcpu_info(n, evtchn_upcall_mask) << 9;
891 if ( put_user(regs->ss, rsp- 1) |
892 put_user(regs->rsp, rsp- 2) |
893 put_user(rflags, rsp- 3) |
894 put_user(cs_and_mask, rsp- 4) |
895 put_user(regs->rip, rsp- 5) |
896 put_user(nctxt->user_regs.gs, rsp- 6) |
897 put_user(nctxt->user_regs.fs, rsp- 7) |
898 put_user(nctxt->user_regs.es, rsp- 8) |
899 put_user(nctxt->user_regs.ds, rsp- 9) |
900 put_user(regs->r11, rsp-10) |
901 put_user(regs->rcx, rsp-11) )
902 {
903 gdprintk(XENLOG_ERR, "Error while creating failsafe "
904 "callback frame.\n");
905 domain_crash(n->domain);
906 }
908 if ( test_bit(_VGCF_failsafe_disables_events,
909 &n->arch.guest_context.flags) )
910 vcpu_info(n, evtchn_upcall_mask) = 1;
912 regs->entry_vector = TRAP_syscall;
913 regs->rflags &= ~(X86_EFLAGS_AC|X86_EFLAGS_VM|X86_EFLAGS_RF|
914 X86_EFLAGS_NT|X86_EFLAGS_TF);
915 regs->ss = FLAT_KERNEL_SS;
916 regs->rsp = (unsigned long)(rsp-11);
917 regs->cs = FLAT_KERNEL_CS;
918 regs->rip = nctxt->failsafe_callback_eip;
919 }
920 }
922 static void save_segments(struct vcpu *v)
923 {
924 struct vcpu_guest_context *ctxt = &v->arch.guest_context;
925 struct cpu_user_regs *regs = &ctxt->user_regs;
926 unsigned int dirty_segment_mask = 0;
928 regs->ds = read_segment_register(ds);
929 regs->es = read_segment_register(es);
930 regs->fs = read_segment_register(fs);
931 regs->gs = read_segment_register(gs);
933 if ( regs->ds )
934 dirty_segment_mask |= DIRTY_DS;
936 if ( regs->es )
937 dirty_segment_mask |= DIRTY_ES;
939 if ( regs->fs || IS_COMPAT(v->domain) )
940 {
941 dirty_segment_mask |= DIRTY_FS;
942 ctxt->fs_base = 0; /* != 0 selector kills fs_base */
943 }
944 else if ( ctxt->fs_base )
945 {
946 dirty_segment_mask |= DIRTY_FS_BASE;
947 }
949 if ( regs->gs || IS_COMPAT(v->domain) )
950 {
951 dirty_segment_mask |= DIRTY_GS;
952 ctxt->gs_base_user = 0; /* != 0 selector kills gs_base_user */
953 }
954 else if ( ctxt->gs_base_user )
955 {
956 dirty_segment_mask |= DIRTY_GS_BASE_USER;
957 }
959 this_cpu(dirty_segment_mask) = dirty_segment_mask;
960 }
962 #define switch_kernel_stack(v) ((void)0)
964 #elif defined(__i386__)
966 #define load_segments(n) ((void)0)
967 #define save_segments(p) ((void)0)
969 static inline void switch_kernel_stack(struct vcpu *v)
970 {
971 struct tss_struct *tss = &init_tss[smp_processor_id()];
972 tss->esp1 = v->arch.guest_context.kernel_sp;
973 tss->ss1 = v->arch.guest_context.kernel_ss;
974 }
976 #endif /* __i386__ */
978 static void paravirt_ctxt_switch_from(struct vcpu *v)
979 {
980 save_segments(v);
981 }
983 static void paravirt_ctxt_switch_to(struct vcpu *v)
984 {
985 set_int80_direct_trap(v);
986 switch_kernel_stack(v);
987 }
989 #define loaddebug(_v,_reg) \
990 __asm__ __volatile__ ("mov %0,%%db" #_reg : : "r" ((_v)->debugreg[_reg]))
992 static void __context_switch(void)
993 {
994 struct cpu_user_regs *stack_regs = guest_cpu_user_regs();
995 unsigned int cpu = smp_processor_id();
996 struct vcpu *p = per_cpu(curr_vcpu, cpu);
997 struct vcpu *n = current;
999 ASSERT(p != n);
1000 ASSERT(cpus_empty(n->vcpu_dirty_cpumask));
1002 if ( !is_idle_vcpu(p) )
1004 memcpy(&p->arch.guest_context.user_regs,
1005 stack_regs,
1006 CTXT_SWITCH_STACK_BYTES);
1007 unlazy_fpu(p);
1008 p->arch.ctxt_switch_from(p);
1011 if ( !is_idle_vcpu(n) )
1013 memcpy(stack_regs,
1014 &n->arch.guest_context.user_regs,
1015 CTXT_SWITCH_STACK_BYTES);
1017 /* Maybe switch the debug registers. */
1018 if ( unlikely(n->arch.guest_context.debugreg[7]) )
1020 loaddebug(&n->arch.guest_context, 0);
1021 loaddebug(&n->arch.guest_context, 1);
1022 loaddebug(&n->arch.guest_context, 2);
1023 loaddebug(&n->arch.guest_context, 3);
1024 /* no 4 and 5 */
1025 loaddebug(&n->arch.guest_context, 6);
1026 loaddebug(&n->arch.guest_context, 7);
1028 n->arch.ctxt_switch_to(n);
1031 if ( p->domain != n->domain )
1032 cpu_set(cpu, n->domain->domain_dirty_cpumask);
1033 cpu_set(cpu, n->vcpu_dirty_cpumask);
1035 write_ptbase(n);
1037 if ( p->vcpu_id != n->vcpu_id )
1039 char gdt_load[10];
1040 *(unsigned short *)(&gdt_load[0]) = LAST_RESERVED_GDT_BYTE;
1041 *(unsigned long *)(&gdt_load[2]) = GDT_VIRT_START(n);
1042 __asm__ __volatile__ ( "lgdt %0" : "=m" (gdt_load) );
1045 if ( p->domain != n->domain )
1046 cpu_clear(cpu, p->domain->domain_dirty_cpumask);
1047 cpu_clear(cpu, p->vcpu_dirty_cpumask);
1049 per_cpu(curr_vcpu, cpu) = n;
1053 void context_switch(struct vcpu *prev, struct vcpu *next)
1055 unsigned int cpu = smp_processor_id();
1056 cpumask_t dirty_mask = next->vcpu_dirty_cpumask;
1058 ASSERT(local_irq_is_enabled());
1060 /* Allow at most one CPU at a time to be dirty. */
1061 ASSERT(cpus_weight(dirty_mask) <= 1);
1062 if ( unlikely(!cpu_isset(cpu, dirty_mask) && !cpus_empty(dirty_mask)) )
1064 /* Other cpus call __sync_lazy_execstate from flush ipi handler. */
1065 if ( !cpus_empty(next->vcpu_dirty_cpumask) )
1066 flush_tlb_mask(next->vcpu_dirty_cpumask);
1069 local_irq_disable();
1071 if ( is_hvm_vcpu(prev) && !list_empty(&prev->arch.hvm_vcpu.tm_list) )
1072 pt_freeze_time(prev);
1074 set_current(next);
1076 if ( (per_cpu(curr_vcpu, cpu) == next) || is_idle_vcpu(next) )
1078 local_irq_enable();
1080 else
1082 __context_switch();
1084 #ifdef CONFIG_COMPAT
1085 if ( is_idle_vcpu(prev)
1086 || IS_COMPAT(prev->domain) != IS_COMPAT(next->domain) )
1088 uint32_t efer_lo, efer_hi;
1090 local_flush_tlb_one(GDT_VIRT_START(next) + FIRST_RESERVED_GDT_BYTE);
1092 rdmsr(MSR_EFER, efer_lo, efer_hi);
1093 if ( !IS_COMPAT(next->domain) == !(efer_lo & EFER_SCE) )
1095 efer_lo ^= EFER_SCE;
1096 wrmsr(MSR_EFER, efer_lo, efer_hi);
1099 #endif
1101 /* Re-enable interrupts before restoring state which may fault. */
1102 local_irq_enable();
1104 if ( !is_hvm_vcpu(next) )
1106 load_LDT(next);
1107 load_segments(next);
1111 context_saved(prev);
1113 /* Update per-VCPU guest runstate shared memory area (if registered). */
1114 if ( !guest_handle_is_null(runstate_guest(next)) )
1116 if ( !IS_COMPAT(next->domain) )
1117 __copy_to_guest(runstate_guest(next), &next->runstate, 1);
1118 #ifdef CONFIG_COMPAT
1119 else
1121 struct compat_vcpu_runstate_info info;
1123 XLAT_vcpu_runstate_info(&info, &next->runstate);
1124 __copy_to_guest(next->runstate_guest.compat, &info, 1);
1126 #endif
1129 schedule_tail(next);
1130 BUG();
1133 void continue_running(struct vcpu *same)
1135 schedule_tail(same);
1136 BUG();
1139 int __sync_lazy_execstate(void)
1141 unsigned long flags;
1142 int switch_required;
1144 local_irq_save(flags);
1146 switch_required = (this_cpu(curr_vcpu) != current);
1148 if ( switch_required )
1150 ASSERT(current == idle_vcpu[smp_processor_id()]);
1151 __context_switch();
1154 local_irq_restore(flags);
1156 return switch_required;
1159 void sync_vcpu_execstate(struct vcpu *v)
1161 if ( cpu_isset(smp_processor_id(), v->vcpu_dirty_cpumask) )
1162 (void)__sync_lazy_execstate();
1164 /* Other cpus call __sync_lazy_execstate from flush ipi handler. */
1165 flush_tlb_mask(v->vcpu_dirty_cpumask);
1168 #define next_arg(fmt, args) ({ \
1169 unsigned long __arg; \
1170 switch ( *(fmt)++ ) \
1171 { \
1172 case 'i': __arg = (unsigned long)va_arg(args, unsigned int); break; \
1173 case 'l': __arg = (unsigned long)va_arg(args, unsigned long); break; \
1174 case 'h': __arg = (unsigned long)va_arg(args, void *); break; \
1175 default: __arg = 0; BUG(); \
1176 } \
1177 __arg; \
1178 })
1180 unsigned long hypercall_create_continuation(
1181 unsigned int op, const char *format, ...)
1183 struct mc_state *mcs = &this_cpu(mc_state);
1184 struct cpu_user_regs *regs;
1185 const char *p = format;
1186 unsigned long arg;
1187 unsigned int i;
1188 va_list args;
1190 va_start(args, format);
1192 if ( test_bit(_MCSF_in_multicall, &mcs->flags) )
1194 __set_bit(_MCSF_call_preempted, &mcs->flags);
1196 for ( i = 0; *p != '\0'; i++ )
1197 mcs->call.args[i] = next_arg(p, args);
1198 if ( IS_COMPAT(current->domain) )
1200 for ( ; i < 6; i++ )
1201 mcs->call.args[i] = 0;
1204 else
1206 regs = guest_cpu_user_regs();
1207 regs->eax = op;
1208 regs->eip -= 2; /* re-execute 'syscall' / 'int 0x82' */
1210 #ifdef __x86_64__
1211 if ( !IS_COMPAT(current->domain) )
1213 for ( i = 0; *p != '\0'; i++ )
1215 arg = next_arg(p, args);
1216 switch ( i )
1218 case 0: regs->rdi = arg; break;
1219 case 1: regs->rsi = arg; break;
1220 case 2: regs->rdx = arg; break;
1221 case 3: regs->r10 = arg; break;
1222 case 4: regs->r8 = arg; break;
1223 case 5: regs->r9 = arg; break;
1227 else
1228 #endif
1230 if ( supervisor_mode_kernel || is_hvm_vcpu(current) )
1231 regs->eip &= ~31; /* re-execute entire hypercall entry stub */
1233 for ( i = 0; *p != '\0'; i++ )
1235 arg = next_arg(p, args);
1236 switch ( i )
1238 case 0: regs->ebx = arg; break;
1239 case 1: regs->ecx = arg; break;
1240 case 2: regs->edx = arg; break;
1241 case 3: regs->esi = arg; break;
1242 case 4: regs->edi = arg; break;
1243 case 5: regs->ebp = arg; break;
1249 va_end(args);
1251 return op;
1254 #ifdef CONFIG_COMPAT
1255 int hypercall_xlat_continuation(unsigned int *id, unsigned int mask, ...)
1257 int rc = 0;
1258 struct mc_state *mcs = &this_cpu(mc_state);
1259 struct cpu_user_regs *regs;
1260 unsigned int i, cval = 0;
1261 unsigned long nval = 0;
1262 va_list args;
1264 BUG_ON(*id > 5);
1265 BUG_ON(mask & (1U << *id));
1267 va_start(args, mask);
1269 if ( test_bit(_MCSF_in_multicall, &mcs->flags) )
1271 if ( !test_bit(_MCSF_call_preempted, &mcs->flags) )
1272 return 0;
1273 for ( i = 0; i < 6; ++i, mask >>= 1 )
1275 if ( mask & 1 )
1277 nval = va_arg(args, unsigned long);
1278 cval = va_arg(args, unsigned int);
1279 if ( cval == nval )
1280 mask &= ~1U;
1281 else
1282 BUG_ON(nval == (unsigned int)nval);
1284 else if ( id && *id == i )
1286 *id = mcs->call.args[i];
1287 id = NULL;
1289 if ( (mask & 1) && mcs->call.args[i] == nval )
1290 ++rc;
1291 else
1293 cval = mcs->call.args[i];
1294 BUG_ON(mcs->call.args[i] != cval);
1296 mcs->compat_call.args[i] = cval;
1299 else
1301 regs = guest_cpu_user_regs();
1302 for ( i = 0; i < 6; ++i, mask >>= 1 )
1304 unsigned long *reg;
1306 switch ( i )
1308 case 0: reg = &regs->ebx; break;
1309 case 1: reg = &regs->ecx; break;
1310 case 2: reg = &regs->edx; break;
1311 case 3: reg = &regs->esi; break;
1312 case 4: reg = &regs->edi; break;
1313 case 5: reg = &regs->ebp; break;
1314 default: BUG(); reg = NULL; break;
1316 if ( (mask & 1) )
1318 nval = va_arg(args, unsigned long);
1319 cval = va_arg(args, unsigned int);
1320 if ( cval == nval )
1321 mask &= ~1U;
1322 else
1323 BUG_ON(nval == (unsigned int)nval);
1325 else if ( id && *id == i )
1327 *id = *reg;
1328 id = NULL;
1330 if ( (mask & 1) && *reg == nval )
1332 *reg = cval;
1333 ++rc;
1335 else
1336 BUG_ON(*reg != (unsigned int)*reg);
1340 va_end(args);
1342 return rc;
1344 #endif
1346 static void relinquish_memory(struct domain *d, struct list_head *list)
1348 struct list_head *ent;
1349 struct page_info *page;
1350 unsigned long x, y;
1352 /* Use a recursive lock, as we may enter 'free_domheap_page'. */
1353 spin_lock_recursive(&d->page_alloc_lock);
1355 ent = list->next;
1356 while ( ent != list )
1358 page = list_entry(ent, struct page_info, list);
1360 /* Grab a reference to the page so it won't disappear from under us. */
1361 if ( unlikely(!get_page(page, d)) )
1363 /* Couldn't get a reference -- someone is freeing this page. */
1364 ent = ent->next;
1365 continue;
1368 if ( test_and_clear_bit(_PGT_pinned, &page->u.inuse.type_info) )
1369 put_page_and_type(page);
1371 if ( test_and_clear_bit(_PGC_allocated, &page->count_info) )
1372 put_page(page);
1374 /*
1375 * Forcibly invalidate base page tables at this point to break circular
1376 * 'linear page table' references. This is okay because MMU structures
1377 * are not shared across domains and this domain is now dead. Thus base
1378 * tables are not in use so a non-zero count means circular reference.
1379 */
1380 y = page->u.inuse.type_info;
1381 for ( ; ; )
1383 x = y;
1384 if ( likely((x & (PGT_type_mask|PGT_validated)) !=
1385 (PGT_base_page_table|PGT_validated)) )
1386 break;
1388 y = cmpxchg(&page->u.inuse.type_info, x, x & ~PGT_validated);
1389 if ( likely(y == x) )
1391 free_page_type(page, PGT_base_page_table);
1392 break;
1396 /* Follow the list chain and /then/ potentially free the page. */
1397 ent = ent->next;
1398 put_page(page);
1401 spin_unlock_recursive(&d->page_alloc_lock);
1404 static void vcpu_destroy_pagetables(struct vcpu *v)
1406 struct domain *d = v->domain;
1407 unsigned long pfn;
1409 #ifdef CONFIG_COMPAT
1410 if ( IS_COMPAT(d) )
1412 if ( is_hvm_vcpu(v) )
1413 pfn = pagetable_get_pfn(v->arch.guest_table);
1414 else
1415 pfn = l4e_get_pfn(*(l4_pgentry_t *)
1416 __va(pagetable_get_paddr(v->arch.guest_table)));
1418 if ( pfn != 0 )
1420 if ( paging_mode_refcounts(d) )
1421 put_page(mfn_to_page(pfn));
1422 else
1423 put_page_and_type(mfn_to_page(pfn));
1426 if ( is_hvm_vcpu(v) )
1427 v->arch.guest_table = pagetable_null();
1428 else
1429 l4e_write(
1430 (l4_pgentry_t *) __va(pagetable_get_paddr(v->arch.guest_table)),
1431 l4e_empty());
1433 v->arch.cr3 = 0;
1434 return;
1436 #endif
1438 pfn = pagetable_get_pfn(v->arch.guest_table);
1439 if ( pfn != 0 )
1441 if ( paging_mode_refcounts(d) )
1442 put_page(mfn_to_page(pfn));
1443 else
1444 put_page_and_type(mfn_to_page(pfn));
1445 #ifdef __x86_64__
1446 if ( pfn == pagetable_get_pfn(v->arch.guest_table_user) )
1447 v->arch.guest_table_user = pagetable_null();
1448 #endif
1449 v->arch.guest_table = pagetable_null();
1452 #ifdef __x86_64__
1453 /* Drop ref to guest_table_user (from MMUEXT_NEW_USER_BASEPTR) */
1454 pfn = pagetable_get_pfn(v->arch.guest_table_user);
1455 if ( pfn != 0 )
1457 if ( paging_mode_refcounts(d) )
1458 put_page(mfn_to_page(pfn));
1459 else
1460 put_page_and_type(mfn_to_page(pfn));
1461 v->arch.guest_table_user = pagetable_null();
1463 #endif
1465 v->arch.cr3 = 0;
1468 void domain_relinquish_resources(struct domain *d)
1470 struct vcpu *v;
1472 BUG_ON(!cpus_empty(d->domain_dirty_cpumask));
1474 /* Drop the in-use references to page-table bases. */
1475 for_each_vcpu ( d, v )
1476 vcpu_destroy_pagetables(v);
1478 /* Tear down paging-assistance stuff. */
1479 paging_teardown(d);
1481 /*
1482 * Relinquish GDT mappings. No need for explicit unmapping of the LDT as
1483 * it automatically gets squashed when the guest's mappings go away.
1484 */
1485 for_each_vcpu(d, v)
1486 destroy_gdt(v);
1488 /* Relinquish every page of memory. */
1489 relinquish_memory(d, &d->xenpage_list);
1490 relinquish_memory(d, &d->page_list);
1492 /* Free page used by xen oprofile buffer */
1493 free_xenoprof_pages(d);
1496 void arch_dump_domain_info(struct domain *d)
1498 paging_dump_domain_info(d);
1501 void arch_dump_vcpu_info(struct vcpu *v)
1503 paging_dump_vcpu_info(v);
1506 /*
1507 * Local variables:
1508 * mode: C
1509 * c-set-style: "BSD"
1510 * c-basic-offset: 4
1511 * tab-width: 4
1512 * indent-tabs-mode: nil
1513 * End:
1514 */