ia64/xen-unstable

view xen/include/asm-x86/hvm/vlapic.h @ 19848:5839491bbf20

[IA64] replace MAX_VCPUS with d->max_vcpus where necessary.

don't use MAX_VCPUS, and use vcpu::max_vcpus.
The changeset of 2f9e1348aa98 introduced max_vcpus to allow more vcpus
per guest. This patch is ia64 counter part.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 11:26:05 2009 +0900 (2009-06-29)
parents ae891977a4d3
children
line source
1 /*
2 * hvm_vlapic.h: virtualize LAPIC definitions.
3 *
4 * Copyright (c) 2004, Intel Corporation.
5 * Copyright (c) 2006 Keir Fraser, XenSource Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
18 * Place - Suite 330, Boston, MA 02111-1307 USA.
19 */
21 #ifndef __ASM_X86_HVM_VLAPIC_H__
22 #define __ASM_X86_HVM_VLAPIC_H__
24 #include <xen/softirq.h>
25 #include <asm/msr.h>
26 #include <public/hvm/ioreq.h>
27 #include <asm/hvm/vpt.h>
29 #define MAX_VECTOR 256
31 #define vcpu_vlapic(vcpu) (&(vcpu)->arch.hvm_vcpu.vlapic)
32 #define vlapic_vcpu(vpic) (container_of((vpic), struct vcpu, \
33 arch.hvm_vcpu.vlapic))
34 #define vlapic_domain(vpic) (vlapic_vcpu(vlapic)->domain)
36 #define VLAPIC_ID(vlapic) \
37 (GET_xAPIC_ID(vlapic_get_reg((vlapic), APIC_ID)))
39 /*
40 * APIC can be disabled in two ways:
41 * 1. 'Hardware disable': via IA32_APIC_BASE_MSR[11]
42 * CPU should behave as if it does not have an APIC.
43 * 2. 'Software disable': via APIC_SPIV[8].
44 * APIC is visible but does not respond to interrupt messages.
45 */
46 #define VLAPIC_HW_DISABLED 0x1
47 #define VLAPIC_SW_DISABLED 0x2
48 #define vlapic_sw_disabled(vlapic) ((vlapic)->hw.disabled & VLAPIC_SW_DISABLED)
49 #define vlapic_hw_disabled(vlapic) ((vlapic)->hw.disabled & VLAPIC_HW_DISABLED)
50 #define vlapic_disabled(vlapic) ((vlapic)->hw.disabled)
51 #define vlapic_enabled(vlapic) (!vlapic_disabled(vlapic))
53 #define vlapic_base_address(vlapic) \
54 ((vlapic)->hw.apic_base_msr & MSR_IA32_APICBASE_BASE)
56 struct vlapic {
57 struct hvm_hw_lapic hw;
58 struct hvm_hw_lapic_regs *regs;
59 struct periodic_time pt;
60 s_time_t timer_last_update;
61 struct page_info *regs_page;
62 struct tasklet init_tasklet;
63 };
65 static inline uint32_t vlapic_get_reg(struct vlapic *vlapic, uint32_t reg)
66 {
67 return *((uint32_t *)(&vlapic->regs->data[reg]));
68 }
70 static inline void vlapic_set_reg(
71 struct vlapic *vlapic, uint32_t reg, uint32_t val)
72 {
73 *((uint32_t *)(&vlapic->regs->data[reg])) = val;
74 }
76 static inline int is_vlapic_lvtpc_enabled(struct vlapic *vlapic)
77 {
78 return vlapic_enabled(vlapic) &&
79 !(vlapic_get_reg(vlapic, APIC_LVTPC) & APIC_LVT_MASKED);
80 }
82 int vlapic_set_irq(struct vlapic *vlapic, uint8_t vec, uint8_t trig);
84 int vlapic_has_pending_irq(struct vcpu *v);
85 int vlapic_ack_pending_irq(struct vcpu *v, int vector);
87 int vlapic_init(struct vcpu *v);
88 void vlapic_destroy(struct vcpu *v);
90 void vlapic_reset(struct vlapic *vlapic);
92 void vlapic_msr_set(struct vlapic *vlapic, uint64_t value);
94 int vlapic_accept_pic_intr(struct vcpu *v);
96 struct vlapic *apic_lowest_prio(struct domain *d, uint32_t bitmap);
98 int vlapic_match_logical_addr(struct vlapic *vlapic, uint8_t mda);
100 void vlapic_EOI_set(struct vlapic *vlapic);
102 int vlapic_ipi(struct vlapic *vlapic, uint32_t icr_low, uint32_t icr_high);
104 #endif /* __ASM_X86_HVM_VLAPIC_H__ */