ia64/xen-unstable

view xen/include/asm-x86/cpufeature.h @ 19848:5839491bbf20

[IA64] replace MAX_VCPUS with d->max_vcpus where necessary.

don't use MAX_VCPUS, and use vcpu::max_vcpus.
The changeset of 2f9e1348aa98 introduced max_vcpus to allow more vcpus
per guest. This patch is ia64 counter part.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 11:26:05 2009 +0900 (2009-06-29)
parents b44db970f6b7
children
line source
1 /*
2 * cpufeature.h
3 *
4 * Defines x86 CPU feature bits
5 */
7 #ifndef __ASM_I386_CPUFEATURE_H
8 #define __ASM_I386_CPUFEATURE_H
10 #include <xen/bitops.h>
12 #define NCAPINTS 7 /* N 32-bit words worth of info */
14 /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
15 #define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
16 #define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
17 #define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
18 #define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
19 #define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
20 #define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
21 #define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
22 #define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
23 #define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
24 #define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
25 #define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
26 #define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
27 #define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
28 #define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
29 #define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
30 #define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
31 #define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
32 #define X86_FEATURE_PN (0*32+18) /* Processor serial number */
33 #define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */
34 #define X86_FEATURE_DS (0*32+21) /* Debug Store */
35 #define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
36 #define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
37 #define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
38 /* of FPU context), and CR4.OSFXSR available */
39 #define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */
40 #define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */
41 #define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */
42 #define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
43 #define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */
44 #define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
45 #define X86_FEATURE_PBE (0*32+31) /* Pending Break Enable */
47 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
48 /* Don't duplicate feature flags which are redundant with Intel! */
49 #define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
50 #define X86_FEATURE_MP (1*32+19) /* MP Capable. */
51 #define X86_FEATURE_NX (1*32+20) /* Execute Disable */
52 #define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
53 #define X86_FEATURE_FFXSR (1*32+25) /* FFXSR instruction optimizations */
54 #define X86_FEATURE_PAGE1GB (1*32+26) /* 1Gb large page support */
55 #define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
56 #define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
57 #define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
58 #define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
60 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
61 #define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */
62 #define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */
63 #define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */
65 /* Other features, Linux-defined mapping, word 3 */
66 /* This range is used for feature bits which conflict or are synthesized */
67 #define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */
68 #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */
69 #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
70 #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
71 /* cpu types for specific tunings: */
72 #define X86_FEATURE_K8 (3*32+ 4) /* Opteron, Athlon64 */
73 #define X86_FEATURE_K7 (3*32+ 5) /* Athlon */
74 #define X86_FEATURE_P3 (3*32+ 6) /* P3 */
75 #define X86_FEATURE_P4 (3*32+ 7) /* P4 */
76 #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
77 #define X86_FEATURE_NOSTOP_TSC (3*32+ 9) /* TSC does not stop in C states */
78 #define X86_FEATURE_ARAT (3*32+ 10) /* Always running APIC timer */
80 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
81 #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
82 #define X86_FEATURE_DTES64 (4*32+ 2) /* 64-bit Debug Store */
83 #define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */
84 #define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
85 #define X86_FEATURE_VMXE (4*32+ 5) /* Virtual Machine Extensions */
86 #define X86_FEATURE_SMXE (4*32+ 6) /* Safer Mode Extensions */
87 #define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */
88 #define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
89 #define X86_FEATURE_SSSE3 (4*32+ 9) /* Supplemental Streaming SIMD Extensions-3 */
90 #define X86_FEATURE_CID (4*32+10) /* Context ID */
91 #define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
92 #define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
93 #define X86_FEATURE_PDCM (4*32+15) /* Perf/Debug Capability MSR */
94 #define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
95 #define X86_FEATURE_SSE4_1 (4*32+19) /* Streaming SIMD Extensions 4.1 */
96 #define X86_FEATURE_SSE4_2 (4*32+20) /* Streaming SIMD Extensions 4.2 */
97 #define X86_FEATURE_X2APIC (4*32+21) /* Extended xAPIC */
98 #define X86_FEATURE_POPCNT (4*32+23) /* POPCNT instruction */
99 #define X86_FEATURE_XSAVE (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
100 #define X86_FEATURE_HYPERVISOR (4*32+31) /* Running under some hypervisor */
102 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
103 #define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
104 #define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */
105 #define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
106 #define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */
107 #define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */
108 #define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */
109 #define X86_FEATURE_PHE (5*32+ 10) /* PadLock Hash Engine */
110 #define X86_FEATURE_PHE_EN (5*32+ 11) /* PHE enabled */
111 #define X86_FEATURE_PMM (5*32+ 12) /* PadLock Montgomery Multiplier */
112 #define X86_FEATURE_PMM_EN (5*32+ 13) /* PMM enabled */
114 /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
115 #define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
116 #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
117 #define X86_FEATURE_SVME (6*32+ 2) /* Secure Virtual Machine */
118 #define X86_FEATURE_EXTAPICSPACE (6*32+ 3) /* Extended APIC space */
119 #define X86_FEATURE_ALTMOVCR (6*32+ 4) /* LOCK MOV CR accesses CR+8 */
120 #define X86_FEATURE_ABM (6*32+ 5) /* Advanced Bit Manipulation */
121 #define X86_FEATURE_SSE4A (6*32+ 6) /* AMD Streaming SIMD Extensions-4a */
122 #define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE Access */
123 #define X86_FEATURE_3DNOWPF (6*32+ 8) /* 3DNow! Prefetch */
124 #define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */
125 #define X86_FEATURE_IBS (6*32+ 10) /* Instruction Based Sampling */
126 #define X86_FEATURE_SSE5 (6*32+ 11) /* AMD Streaming SIMD Extensions-5 */
127 #define X86_FEATURE_SKINIT (6*32+ 12) /* SKINIT, STGI/CLGI, DEV */
128 #define X86_FEATURE_WDT (6*32+ 13) /* Watchdog Timer */
130 #define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
131 #define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
133 #ifdef __i386__
134 #define cpu_has_vme boot_cpu_has(X86_FEATURE_VME)
135 #define cpu_has_de boot_cpu_has(X86_FEATURE_DE)
136 #define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE)
137 #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC)
138 #define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE)
139 #define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE)
140 #define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
141 #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
142 #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
143 #define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR)
144 #define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX)
145 #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
146 #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
147 #define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
148 #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
149 #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
150 #define cpu_has_syscall boot_cpu_has(X86_FEATURE_SYSCALL)
151 #define cpu_has_mp boot_cpu_has(X86_FEATURE_MP)
152 #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
153 #define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR)
154 #define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR)
155 #define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
156 #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
157 #define cpu_has_page1gb 0
158 #define cpu_has_efer (boot_cpu_data.x86_capability[1] & 0x20100800)
159 #else /* __x86_64__ */
160 #define cpu_has_vme 0
161 #define cpu_has_de 1
162 #define cpu_has_pse 1
163 #define cpu_has_tsc 1
164 #define cpu_has_pae 1
165 #define cpu_has_pge 1
166 #define cpu_has_pat 1
167 #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
168 #define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
169 #define cpu_has_mtrr 1
170 #define cpu_has_mmx 1
171 #define cpu_has_fxsr 1
172 #define cpu_has_xmm 1
173 #define cpu_has_xmm2 1
174 #define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
175 #define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
176 #define cpu_has_syscall 1
177 #define cpu_has_mp 1
178 #define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
179 #define cpu_has_k6_mtrr 0
180 #define cpu_has_cyrix_arr 0
181 #define cpu_has_centaur_mcr 0
182 #define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
183 #define cpu_has_page1gb boot_cpu_has(X86_FEATURE_PAGE1GB)
184 #define cpu_has_efer 1
185 #endif
187 #define cpu_has_ffxsr ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) \
188 && boot_cpu_has(X86_FEATURE_FFXSR))
190 #define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
191 #endif /* __ASM_I386_CPUFEATURE_H */
193 /*
194 * Local Variables:
195 * mode:c
196 * comment-column:42
197 * End:
198 */