ia64/xen-unstable

view xen/include/asm-x86/config.h @ 19848:5839491bbf20

[IA64] replace MAX_VCPUS with d->max_vcpus where necessary.

don't use MAX_VCPUS, and use vcpu::max_vcpus.
The changeset of 2f9e1348aa98 introduced max_vcpus to allow more vcpus
per guest. This patch is ia64 counter part.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 11:26:05 2009 +0900 (2009-06-29)
parents 2f9e1348aa98
children
line source
1 /******************************************************************************
2 * config.h
3 *
4 * A Linux-style configuration list.
5 */
7 #ifndef __X86_CONFIG_H__
8 #define __X86_CONFIG_H__
10 #if defined(__x86_64__)
11 # define CONFIG_PAGING_LEVELS 4
12 #else
13 # define CONFIG_PAGING_LEVELS 3
14 #endif
16 #define CONFIG_X86 1
17 #define CONFIG_X86_HT 1
18 #define CONFIG_PAGING_ASSISTANCE 1
19 #define CONFIG_SMP 1
20 #define CONFIG_X86_LOCAL_APIC 1
21 #define CONFIG_X86_GOOD_APIC 1
22 #define CONFIG_X86_IO_APIC 1
23 #define CONFIG_X86_PM_TIMER 1
24 #define CONFIG_HPET_TIMER 1
25 #define CONFIG_X86_MCE_THERMAL 1
26 #define CONFIG_NUMA 1
27 #define CONFIG_DISCONTIGMEM 1
28 #define CONFIG_NUMA_EMU 1
30 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */
31 #define CONFIG_X86_L1_CACHE_SHIFT 7
33 #define CONFIG_ACPI 1
34 #define CONFIG_ACPI_BOOT 1
35 #define CONFIG_ACPI_SLEEP 1
36 #define CONFIG_ACPI_NUMA 1
37 #define CONFIG_ACPI_SRAT 1
38 #define CONFIG_ACPI_CSTATE 1
40 #define CONFIG_VGA 1
42 #define CONFIG_HOTPLUG 1
43 #define CONFIG_HOTPLUG_CPU 1
45 #define HZ 100
47 #define OPT_CONSOLE_STR "vga"
49 #ifdef MAX_PHYS_CPUS
50 #define NR_CPUS MAX_PHYS_CPUS
51 #else
52 #define NR_CPUS 32
53 #endif
55 #ifdef __i386__
56 #if NR_CPUS > 32
57 #error "Maximum of 32 physical processors supported by Xen on x86_32"
58 #endif
59 /* Maximum number of virtual CPUs in multi-processor guests. */
60 #define MAX_VIRT_CPUS XEN_LEGACY_MAX_VCPUS
61 #endif
63 #ifdef CONFIG_X86_SUPERVISOR_MODE_KERNEL
64 # define supervisor_mode_kernel (1)
65 #else
66 # define supervisor_mode_kernel (0)
67 #endif
69 /* Linkage for x86 */
70 #define __ALIGN .align 16,0x90
71 #define __ALIGN_STR ".align 16,0x90"
72 #ifdef __ASSEMBLY__
73 #define ALIGN __ALIGN
74 #define ALIGN_STR __ALIGN_STR
75 #define ENTRY(name) \
76 .globl name; \
77 ALIGN; \
78 name:
79 #endif
81 #define NR_hypercalls 64
83 #ifndef NDEBUG
84 #define MEMORY_GUARD
85 #endif
87 #ifdef __i386__
88 #define STACK_ORDER 2
89 #else
90 #define STACK_ORDER 3
91 #endif
92 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER)
94 /* Primary stack is restricted to 8kB by guard pages. */
95 #define PRIMARY_STACK_SIZE 8192
97 #define BOOT_TRAMPOLINE 0x8c000
98 #define bootsym_phys(sym) \
99 (((unsigned long)&(sym)-(unsigned long)&trampoline_start)+BOOT_TRAMPOLINE)
100 #define bootsym(sym) \
101 (*RELOC_HIDE((typeof(&(sym)))__va(__pa(&(sym))), \
102 BOOT_TRAMPOLINE-__pa(trampoline_start)))
103 #ifndef __ASSEMBLY__
104 extern char trampoline_start[], trampoline_end[];
105 extern char trampoline_realmode_entry[];
106 extern unsigned int trampoline_xen_phys_start;
107 extern unsigned char trampoline_cpu_started;
108 extern char wakeup_start[];
109 extern unsigned int video_mode, video_flags;
110 #endif
112 #if defined(__x86_64__)
114 #define CONFIG_X86_64 1
115 #define CONFIG_COMPAT 1
117 #define asmlinkage
119 #define PML4_ENTRY_BITS 39
120 #ifndef __ASSEMBLY__
121 #define PML4_ENTRY_BYTES (1UL << PML4_ENTRY_BITS)
122 #define PML4_ADDR(_slot) \
123 ((((_slot ## UL) >> 8) * 0xffff000000000000UL) | \
124 (_slot ## UL << PML4_ENTRY_BITS))
125 #else
126 #define PML4_ENTRY_BYTES (1 << PML4_ENTRY_BITS)
127 #define PML4_ADDR(_slot) \
128 (((_slot >> 8) * 0xffff000000000000) | (_slot << PML4_ENTRY_BITS))
129 #endif
131 /*
132 * Memory layout:
133 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255]
134 * Guest-defined use (see below for compatibility mode guests).
135 * 0x0000800000000000 - 0xffff7fffffffffff [16EB]
136 * Inaccessible: current arch only supports 48-bit sign-extended VAs.
137 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256]
138 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
139 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256]
140 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE).
141 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257]
142 * ioremap for PCI mmconfig space
143 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258]
144 * Guest linear page table.
145 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259]
146 * Shadow linear page table.
147 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260]
148 * Per-domain mappings (e.g., GDT, LDT).
149 * 0xffff828000000000 - 0xffff8283ffffffff [16GB, 2^34 bytes, PML4:261]
150 * Machine-to-phys translation table.
151 * 0xffff828400000000 - 0xffff8287ffffffff [16GB, 2^34 bytes, PML4:261]
152 * Page-frame information array.
153 * 0xffff828800000000 - 0xffff828bffffffff [16GB, 2^34 bytes, PML4:261]
154 * ioremap()/fixmap area.
155 * 0xffff828c00000000 - 0xffff828c3fffffff [1GB, 2^30 bytes, PML4:261]
156 * Compatibility machine-to-phys translation table.
157 * 0xffff828c40000000 - 0xffff828c7fffffff [1GB, 2^30 bytes, PML4:261]
158 * High read-only compatibility machine-to-phys translation table.
159 * 0xffff828c80000000 - 0xffff828cbfffffff [1GB, 2^30 bytes, PML4:261]
160 * Xen text, static data, bss.
161 * 0xffff828cc0000000 - 0xffff82ffffffffff [461GB, PML4:261]
162 * Reserved for future use.
163 * 0xffff830000000000 - 0xffff83ffffffffff [1TB, 2^40 bytes, PML4:262-263]
164 * 1:1 direct mapping of all physical memory.
165 * 0xffff840000000000 - 0xffff87ffffffffff [4TB, 2^42 bytes, PML4:264-271]
166 * Reserved for future use.
167 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511]
168 * Guest-defined use.
169 *
170 * Compatibility guest area layout:
171 * 0x0000000000000000 - 0x00000000f57fffff [3928MB, PML4:0]
172 * Guest-defined use.
173 * 0x00000000f5800000 - 0x00000000ffffffff [168MB, PML4:0]
174 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
175 * 0x0000000100000000 - 0x0000007fffffffff [508GB, PML4:0]
176 * Unused.
177 * 0x0000008000000000 - 0x000000ffffffffff [512GB, 2^39 bytes, PML4:1]
178 * Hypercall argument translation area.
179 * 0x0000010000000000 - 0x00007fffffffffff [127TB, 2^46 bytes, PML4:2-255]
180 * Reserved for future use.
181 */
184 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256
185 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271
186 #define ROOT_PAGETABLE_XEN_SLOTS \
187 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1)
189 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */
190 #define HYPERVISOR_VIRT_START (PML4_ADDR(256))
191 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16)
192 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */
193 #define RO_MPT_VIRT_START (PML4_ADDR(256))
194 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + PML4_ENTRY_BYTES/2)
195 /* Slot 257: ioremap for PCI mmconfig space for 2048 segments (512GB)
196 * - full 16-bit segment support needs 44 bits
197 * - since PML4 slot has 39 bits, we limit segments to 2048 (11-bits)
198 */
199 #define PCI_MCFG_VIRT_START (PML4_ADDR(257))
200 #define PCI_MCFG_VIRT_END (RDWR_MPT_VIRT_START + PML4_ENTRY_BYTES)
201 /* Slot 258: linear page table (guest table). */
202 #define LINEAR_PT_VIRT_START (PML4_ADDR(258))
203 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
204 /* Slot 259: linear page table (shadow table). */
205 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259))
206 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
207 /* Slot 260: per-domain mappings. */
208 #define PERDOMAIN_VIRT_START (PML4_ADDR(260))
209 #define PERDOMAIN_VIRT_END (PERDOMAIN_VIRT_START + (PERDOMAIN_MBYTES<<20))
210 #define PERDOMAIN_MBYTES (PML4_ENTRY_BYTES >> (20 + PAGETABLE_ORDER))
211 /* Slot 261: machine-to-phys conversion table (16GB). */
212 #define RDWR_MPT_VIRT_START (PML4_ADDR(261))
213 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + (16UL<<30))
214 /* Slot 261: page-frame information array (16GB). */
215 #define FRAMETABLE_VIRT_START (RDWR_MPT_VIRT_END)
216 #define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + (16UL<<30))
217 /* Slot 261: ioremap()/fixmap area (16GB). */
218 #define IOREMAP_VIRT_START (FRAMETABLE_VIRT_END)
219 #define IOREMAP_VIRT_END (IOREMAP_VIRT_START + (16UL<<30))
220 /* Slot 261: compatibility machine-to-phys conversion table (1GB). */
221 #define RDWR_COMPAT_MPT_VIRT_START IOREMAP_VIRT_END
222 #define RDWR_COMPAT_MPT_VIRT_END (RDWR_COMPAT_MPT_VIRT_START + (1UL << 30))
223 /* Slot 261: high read-only compat machine-to-phys conversion table (1GB). */
224 #define HIRO_COMPAT_MPT_VIRT_START RDWR_COMPAT_MPT_VIRT_END
225 #define HIRO_COMPAT_MPT_VIRT_END (HIRO_COMPAT_MPT_VIRT_START + (1UL << 30))
226 /* Slot 261: xen text, static data and bss (1GB). */
227 #define XEN_VIRT_START (HIRO_COMPAT_MPT_VIRT_END)
228 #define XEN_VIRT_END (XEN_VIRT_START + (1UL << 30))
229 /* Slot 262-263: A direct 1:1 mapping of all of physical memory. */
230 #define DIRECTMAP_VIRT_START (PML4_ADDR(262))
231 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + PML4_ENTRY_BYTES*2)
233 #ifndef __ASSEMBLY__
235 /* This is not a fixed value, just a lower limit. */
236 #define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000
237 #define HYPERVISOR_COMPAT_VIRT_START(d) ((d)->arch.hv_compat_vstart)
238 #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START
239 #define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000
240 #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \
241 ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2)
243 #define COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) \
244 l2_table_offset(HYPERVISOR_COMPAT_VIRT_START(d))
245 #define COMPAT_L2_PAGETABLE_LAST_XEN_SLOT l2_table_offset(~0U)
246 #define COMPAT_L2_PAGETABLE_XEN_SLOTS(d) \
247 (COMPAT_L2_PAGETABLE_LAST_XEN_SLOT - COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) + 1)
249 #define COMPAT_LEGACY_MAX_VCPUS XEN_LEGACY_MAX_VCPUS
251 #endif
253 #define PGT_base_page_table PGT_l4_page_table
255 #define __HYPERVISOR_CS64 0xe008
256 #define __HYPERVISOR_CS32 0xe038
257 #define __HYPERVISOR_CS __HYPERVISOR_CS64
258 #define __HYPERVISOR_DS64 0x0000
259 #define __HYPERVISOR_DS32 0xe010
260 #define __HYPERVISOR_DS __HYPERVISOR_DS64
262 /* For generic assembly code: use macros to define operation/operand sizes. */
263 #define __OS "q" /* Operation Suffix */
264 #define __OP "r" /* Operand Prefix */
265 #define __FIXUP_ALIGN ".align 8"
266 #define __FIXUP_WORD ".quad"
268 #elif defined(__i386__)
270 #define CONFIG_X86_32 1
271 #define CONFIG_DOMAIN_PAGE 1
273 #define asmlinkage __attribute__((regparm(0)))
275 /*
276 * Memory layout (high to low): PAE-SIZE
277 * ------
278 * I/O remapping area ( 4MB)
279 * Direct-map (1:1) area [Xen code/data/heap] (12MB)
280 * Per-domain mappings (inc. 4MB map_domain_page cache) ( 8MB)
281 * Shadow linear pagetable ( 8MB)
282 * Guest linear pagetable ( 8MB)
283 * Machine-to-physical translation table [writable] (16MB)
284 * Frame-info table (96MB)
285 * * Start of guest inaccessible area
286 * Machine-to-physical translation table [read-only] (16MB)
287 * * Start of guest unmodifiable area
288 */
290 #define IOREMAP_MBYTES 4
291 #define DIRECTMAP_MBYTES 12
292 #define MAPCACHE_MBYTES 4
293 #define PERDOMAIN_MBYTES 8
295 #define LINEARPT_MBYTES 8
296 #define MACHPHYS_MBYTES 16 /* 1 MB needed per 1 GB memory */
297 #define FRAMETABLE_MBYTES (MACHPHYS_MBYTES * 6)
299 #define IOREMAP_VIRT_END 0UL
300 #define IOREMAP_VIRT_START (IOREMAP_VIRT_END - (IOREMAP_MBYTES<<20))
301 #define DIRECTMAP_VIRT_END IOREMAP_VIRT_START
302 #define DIRECTMAP_VIRT_START (DIRECTMAP_VIRT_END - (DIRECTMAP_MBYTES<<20))
303 #define MAPCACHE_VIRT_END DIRECTMAP_VIRT_START
304 #define MAPCACHE_VIRT_START (MAPCACHE_VIRT_END - (MAPCACHE_MBYTES<<20))
305 #define PERDOMAIN_VIRT_END DIRECTMAP_VIRT_START
306 #define PERDOMAIN_VIRT_START (PERDOMAIN_VIRT_END - (PERDOMAIN_MBYTES<<20))
307 #define SH_LINEAR_PT_VIRT_END PERDOMAIN_VIRT_START
308 #define SH_LINEAR_PT_VIRT_START (SH_LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
309 #define LINEAR_PT_VIRT_END SH_LINEAR_PT_VIRT_START
310 #define LINEAR_PT_VIRT_START (LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
311 #define RDWR_MPT_VIRT_END LINEAR_PT_VIRT_START
312 #define RDWR_MPT_VIRT_START (RDWR_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
313 #define FRAMETABLE_VIRT_END RDWR_MPT_VIRT_START
314 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - (FRAMETABLE_MBYTES<<20))
315 #define RO_MPT_VIRT_END FRAMETABLE_VIRT_START
316 #define RO_MPT_VIRT_START (RO_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
318 #define DIRECTMAP_PHYS_END (DIRECTMAP_MBYTES<<20)
320 /* Maximum linear address accessible via guest memory segments. */
321 #define GUEST_SEGMENT_MAX_ADDR RO_MPT_VIRT_END
323 /* Hypervisor owns top 168MB of virtual address space. */
324 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xF5800000)
326 #define L2_PAGETABLE_FIRST_XEN_SLOT \
327 (HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT)
328 #define L2_PAGETABLE_LAST_XEN_SLOT \
329 (~0UL >> L2_PAGETABLE_SHIFT)
330 #define L2_PAGETABLE_XEN_SLOTS \
331 (L2_PAGETABLE_LAST_XEN_SLOT - L2_PAGETABLE_FIRST_XEN_SLOT + 1)
333 #define PGT_base_page_table PGT_l3_page_table
335 #define __HYPERVISOR_CS 0xe008
336 #define __HYPERVISOR_DS 0xe010
338 /* For generic assembly code: use macros to define operation/operand sizes. */
339 #define __OS "l" /* Operation Suffix */
340 #define __OP "e" /* Operand Prefix */
341 #define __FIXUP_ALIGN ".align 4"
342 #define __FIXUP_WORD ".long"
344 #endif /* __i386__ */
346 #ifndef __ASSEMBLY__
347 extern unsigned long xen_phys_start;
348 #if defined(__i386__)
349 extern unsigned long xenheap_phys_end;
350 #endif
351 #endif
353 /* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */
354 #define GDT_LDT_VCPU_SHIFT 5
355 #define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT)
356 #ifdef MAX_VIRT_CPUS
357 #define GDT_LDT_MBYTES (MAX_VIRT_CPUS >> (20-GDT_LDT_VCPU_VA_SHIFT))
358 #else
359 #define GDT_LDT_MBYTES PERDOMAIN_MBYTES
360 #define MAX_VIRT_CPUS (GDT_LDT_MBYTES << (20-GDT_LDT_VCPU_VA_SHIFT))
361 #endif
362 #define GDT_LDT_VIRT_START PERDOMAIN_VIRT_START
363 #define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20))
365 /* The address of a particular VCPU's GDT or LDT. */
366 #define GDT_VIRT_START(v) \
367 (PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT))
368 #define LDT_VIRT_START(v) \
369 (GDT_VIRT_START(v) + (64*1024))
371 #define PDPT_L1_ENTRIES \
372 ((PERDOMAIN_VIRT_END - PERDOMAIN_VIRT_START) >> PAGE_SHIFT)
373 #define PDPT_L2_ENTRIES \
374 ((PDPT_L1_ENTRIES + (1 << PAGETABLE_ORDER) - 1) >> PAGETABLE_ORDER)
376 #if defined(__x86_64__)
377 #define ELFSIZE 64
378 #else
379 #define ELFSIZE 32
380 #endif
382 #define ARCH_CRASH_SAVE_VMCOREINFO
384 #endif /* __X86_CONFIG_H__ */