ia64/xen-unstable

view xen/include/asm-x86/apicdef.h @ 19848:5839491bbf20

[IA64] replace MAX_VCPUS with d->max_vcpus where necessary.

don't use MAX_VCPUS, and use vcpu::max_vcpus.
The changeset of 2f9e1348aa98 introduced max_vcpus to allow more vcpus
per guest. This patch is ia64 counter part.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 11:26:05 2009 +0900 (2009-06-29)
parents 4d5203f95498
children
line source
1 #ifndef __ASM_APICDEF_H
2 #define __ASM_APICDEF_H
4 /*
5 * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
6 *
7 * Alan Cox <Alan.Cox@linux.org>, 1995.
8 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
9 */
11 #define APIC_DEFAULT_PHYS_BASE 0xfee00000
13 #define APIC_ID 0x20
14 #define APIC_ID_MASK (0xFFu<<24)
15 #define GET_xAPIC_ID(x) (((x)>>24)&0xFFu)
16 #define SET_xAPIC_ID(x) (((x)<<24))
17 #define APIC_LVR 0x30
18 #define APIC_LVR_MASK 0xFF00FF
19 #define GET_APIC_VERSION(x) ((x)&0xFF)
20 #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF)
21 #define APIC_INTEGRATED(x) ((x)&0xF0)
22 #define APIC_XAPIC(x) ((x) >= 0x14)
23 #define APIC_TASKPRI 0x80
24 #define APIC_TPRI_MASK 0xFF
25 #define APIC_ARBPRI 0x90
26 #define APIC_ARBPRI_MASK 0xFF
27 #define APIC_PROCPRI 0xA0
28 #define APIC_EOI 0xB0
29 #define APIC_EIO_ACK 0x0 /* Write this to the EOI register */
30 #define APIC_RRR 0xC0
31 #define APIC_LDR 0xD0
32 #define APIC_LDR_MASK (0xFF<<24)
33 #define GET_xAPIC_LOGICAL_ID(x) (((x)>>24)&0xFF)
34 #define SET_xAPIC_LOGICAL_ID(x) (((x)<<24))
35 #define APIC_ALL_CPUS 0xFF
36 #define APIC_DFR 0xE0
37 #define APIC_DFR_CLUSTER 0x0FFFFFFFul
38 #define APIC_DFR_FLAT 0xFFFFFFFFul
39 #define APIC_SPIV 0xF0
40 #define APIC_SPIV_FOCUS_DISABLED (1<<9)
41 #define APIC_SPIV_APIC_ENABLED (1<<8)
42 #define APIC_ISR 0x100
43 #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */
44 #define APIC_TMR 0x180
45 #define APIC_IRR 0x200
46 #define APIC_ESR 0x280
47 #define APIC_ESR_SEND_CS 0x00001
48 #define APIC_ESR_RECV_CS 0x00002
49 #define APIC_ESR_SEND_ACC 0x00004
50 #define APIC_ESR_RECV_ACC 0x00008
51 #define APIC_ESR_SENDILL 0x00020
52 #define APIC_ESR_RECVILL 0x00040
53 #define APIC_ESR_ILLREGA 0x00080
54 #define APIC_ICR 0x300
55 #define APIC_DEST_SELF 0x40000
56 #define APIC_DEST_ALLINC 0x80000
57 #define APIC_DEST_ALLBUT 0xC0000
58 #define APIC_ICR_RR_MASK 0x30000
59 #define APIC_ICR_RR_INVALID 0x00000
60 #define APIC_ICR_RR_INPROG 0x10000
61 #define APIC_ICR_RR_VALID 0x20000
62 #define APIC_INT_LEVELTRIG 0x08000
63 #define APIC_INT_ASSERT 0x04000
64 #define APIC_ICR_BUSY 0x01000
65 #define APIC_DEST_LOGICAL 0x00800
66 #define APIC_DEST_PHYSICAL 0x00000
67 #define APIC_DM_FIXED 0x00000
68 #define APIC_DM_LOWEST 0x00100
69 #define APIC_DM_SMI 0x00200
70 #define APIC_DM_REMRD 0x00300
71 #define APIC_DM_NMI 0x00400
72 #define APIC_DM_INIT 0x00500
73 #define APIC_DM_STARTUP 0x00600
74 #define APIC_DM_EXTINT 0x00700
75 #define APIC_VECTOR_MASK 0x000FF
76 #define APIC_ICR2 0x310
77 #define GET_xAPIC_DEST_FIELD(x) (((x)>>24)&0xFF)
78 #define SET_xAPIC_DEST_FIELD(x) ((x)<<24)
79 #define APIC_LVTT 0x320
80 #define APIC_LVTTHMR 0x330
81 #define APIC_LVTPC 0x340
82 #define APIC_LVT0 0x350
83 #define APIC_CMCI 0x2F0
85 #define APIC_LVT_TIMER_BASE_MASK (0x3<<18)
86 #define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3)
87 #define SET_APIC_TIMER_BASE(x) (((x)<<18))
88 #define APIC_TIMER_BASE_CLKIN 0x0
89 #define APIC_TIMER_BASE_TMBASE 0x1
90 #define APIC_TIMER_BASE_DIV 0x2
91 #define APIC_LVT_TIMER_PERIODIC (1<<17)
92 #define APIC_LVT_MASKED (1<<16)
93 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
94 #define APIC_LVT_REMOTE_IRR (1<<14)
95 #define APIC_INPUT_POLARITY (1<<13)
96 #define APIC_SEND_PENDING (1<<12)
97 #define APIC_MODE_MASK 0x700
98 #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7)
99 #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8))
100 #define APIC_MODE_FIXED 0x0
101 #define APIC_MODE_NMI 0x4
102 #define APIC_MODE_EXTINT 0x7
103 #define APIC_LVT1 0x360
104 #define APIC_LVTERR 0x370
105 #define APIC_TMICT 0x380
106 #define APIC_TMCCT 0x390
107 #define APIC_TDCR 0x3E0
109 /* Only available in x2APIC mode */
110 #define APIC_SELF_IPI 0x400
112 #define APIC_TDR_DIV_TMBASE (1<<2)
113 #define APIC_TDR_DIV_1 0xB
114 #define APIC_TDR_DIV_2 0x0
115 #define APIC_TDR_DIV_4 0x1
116 #define APIC_TDR_DIV_8 0x2
117 #define APIC_TDR_DIV_16 0x3
118 #define APIC_TDR_DIV_32 0x8
119 #define APIC_TDR_DIV_64 0x9
120 #define APIC_TDR_DIV_128 0xA
122 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
124 /* It's only used in x2APIC mode of an x2APIC unit. */
125 #define APIC_MSR_BASE 0x800
127 #ifdef __i386__
128 #define MAX_IO_APICS 64
129 #else
130 #define MAX_IO_APICS 128
131 #endif
133 /*
134 * the local APIC register structure, memory mapped. Not terribly well
135 * tested, but we might eventually use this one in the future - the
136 * problem why we cannot use it right now is the P5 APIC, it has an
137 * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
138 */
139 #define u32 unsigned int
141 #define lapic ((volatile struct local_apic *)APIC_BASE)
143 #ifndef __ASSEMBLY__
144 struct local_apic {
146 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
148 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
150 /*020*/ struct { /* APIC ID Register */
151 u32 __reserved_1 : 24,
152 phys_apic_id : 4,
153 __reserved_2 : 4;
154 u32 __reserved[3];
155 } id;
157 /*030*/ const
158 struct { /* APIC Version Register */
159 u32 version : 8,
160 __reserved_1 : 8,
161 max_lvt : 8,
162 __reserved_2 : 8;
163 u32 __reserved[3];
164 } version;
166 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
168 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
170 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
172 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
174 /*080*/ struct { /* Task Priority Register */
175 u32 priority : 8,
176 __reserved_1 : 24;
177 u32 __reserved_2[3];
178 } tpr;
180 /*090*/ const
181 struct { /* Arbitration Priority Register */
182 u32 priority : 8,
183 __reserved_1 : 24;
184 u32 __reserved_2[3];
185 } apr;
187 /*0A0*/ const
188 struct { /* Processor Priority Register */
189 u32 priority : 8,
190 __reserved_1 : 24;
191 u32 __reserved_2[3];
192 } ppr;
194 /*0B0*/ struct { /* End Of Interrupt Register */
195 u32 eoi;
196 u32 __reserved[3];
197 } eoi;
199 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
201 /*0D0*/ struct { /* Logical Destination Register */
202 u32 __reserved_1 : 24,
203 logical_dest : 8;
204 u32 __reserved_2[3];
205 } ldr;
207 /*0E0*/ struct { /* Destination Format Register */
208 u32 __reserved_1 : 28,
209 model : 4;
210 u32 __reserved_2[3];
211 } dfr;
213 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
214 u32 spurious_vector : 8,
215 apic_enabled : 1,
216 focus_cpu : 1,
217 __reserved_2 : 22;
218 u32 __reserved_3[3];
219 } svr;
221 /*100*/ struct { /* In Service Register */
222 /*170*/ u32 bitfield;
223 u32 __reserved[3];
224 } isr [8];
226 /*180*/ struct { /* Trigger Mode Register */
227 /*1F0*/ u32 bitfield;
228 u32 __reserved[3];
229 } tmr [8];
231 /*200*/ struct { /* Interrupt Request Register */
232 /*270*/ u32 bitfield;
233 u32 __reserved[3];
234 } irr [8];
236 /*280*/ union { /* Error Status Register */
237 struct {
238 u32 send_cs_error : 1,
239 receive_cs_error : 1,
240 send_accept_error : 1,
241 receive_accept_error : 1,
242 __reserved_1 : 1,
243 send_illegal_vector : 1,
244 receive_illegal_vector : 1,
245 illegal_register_address : 1,
246 __reserved_2 : 24;
247 u32 __reserved_3[3];
248 } error_bits;
249 struct {
250 u32 errors;
251 u32 __reserved_3[3];
252 } all_errors;
253 } esr;
255 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
257 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
259 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
261 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
263 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
265 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
267 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
269 /*300*/ struct { /* Interrupt Command Register 1 */
270 u32 vector : 8,
271 delivery_mode : 3,
272 destination_mode : 1,
273 delivery_status : 1,
274 __reserved_1 : 1,
275 level : 1,
276 trigger : 1,
277 __reserved_2 : 2,
278 shorthand : 2,
279 __reserved_3 : 12;
280 u32 __reserved_4[3];
281 } icr1;
283 /*310*/ struct { /* Interrupt Command Register 2 */
284 union {
285 u32 __reserved_1 : 24,
286 phys_dest : 4,
287 __reserved_2 : 4;
288 u32 __reserved_3 : 24,
289 logical_dest : 8;
290 } dest;
291 u32 __reserved_4[3];
292 } icr2;
294 /*320*/ struct { /* LVT - Timer */
295 u32 vector : 8,
296 __reserved_1 : 4,
297 delivery_status : 1,
298 __reserved_2 : 3,
299 mask : 1,
300 timer_mode : 1,
301 __reserved_3 : 14;
302 u32 __reserved_4[3];
303 } lvt_timer;
305 /*330*/ struct { /* LVT - Thermal Sensor */
306 u32 vector : 8,
307 delivery_mode : 3,
308 __reserved_1 : 1,
309 delivery_status : 1,
310 __reserved_2 : 3,
311 mask : 1,
312 __reserved_3 : 15;
313 u32 __reserved_4[3];
314 } lvt_thermal;
316 /*340*/ struct { /* LVT - Performance Counter */
317 u32 vector : 8,
318 delivery_mode : 3,
319 __reserved_1 : 1,
320 delivery_status : 1,
321 __reserved_2 : 3,
322 mask : 1,
323 __reserved_3 : 15;
324 u32 __reserved_4[3];
325 } lvt_pc;
327 /*350*/ struct { /* LVT - LINT0 */
328 u32 vector : 8,
329 delivery_mode : 3,
330 __reserved_1 : 1,
331 delivery_status : 1,
332 polarity : 1,
333 remote_irr : 1,
334 trigger : 1,
335 mask : 1,
336 __reserved_2 : 15;
337 u32 __reserved_3[3];
338 } lvt_lint0;
340 /*360*/ struct { /* LVT - LINT1 */
341 u32 vector : 8,
342 delivery_mode : 3,
343 __reserved_1 : 1,
344 delivery_status : 1,
345 polarity : 1,
346 remote_irr : 1,
347 trigger : 1,
348 mask : 1,
349 __reserved_2 : 15;
350 u32 __reserved_3[3];
351 } lvt_lint1;
353 /*370*/ struct { /* LVT - Error */
354 u32 vector : 8,
355 __reserved_1 : 4,
356 delivery_status : 1,
357 __reserved_2 : 3,
358 mask : 1,
359 __reserved_3 : 15;
360 u32 __reserved_4[3];
361 } lvt_error;
363 /*380*/ struct { /* Timer Initial Count Register */
364 u32 initial_count;
365 u32 __reserved_2[3];
366 } timer_icr;
368 /*390*/ const
369 struct { /* Timer Current Count Register */
370 u32 curr_count;
371 u32 __reserved_2[3];
372 } timer_ccr;
374 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
376 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
378 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
380 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
382 /*3E0*/ struct { /* Timer Divide Configuration Register */
383 u32 divisor : 4,
384 __reserved_1 : 28;
385 u32 __reserved_2[3];
386 } timer_dcr;
388 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
390 } __attribute__ ((packed));
391 #endif /* !__ASSEMBLY__ */
393 #undef u32
395 #endif