ia64/xen-unstable

view xen/arch/x86/smpboot.c @ 9518:5715cf117178

Ensure curr_vcpu in domain.c is set correctly, even when
nr physical cpus is greater than max virtual cpus per domain.

Also do not initialise secondary CPU smp_processor_id() from
smpboot.c cpucount. It will be wrong if some CPUs fail to boot.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Wed Mar 29 15:39:22 2006 +0100 (2006-03-29)
parents d7cbcf5d7cd6
children 05d8c51c7550
line source
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 *
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
9 *
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
13 *
14 * This code is released under the GNU General Public License version 2 or
15 * later.
16 *
17 * Fixes
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
28 * from Jose Renau
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <xen/config.h>
37 #include <xen/init.h>
38 #include <xen/kernel.h>
39 #include <xen/mm.h>
40 #include <xen/sched.h>
41 #include <xen/irq.h>
42 #include <xen/delay.h>
43 #include <xen/softirq.h>
44 #include <asm/current.h>
45 #include <asm/mc146818rtc.h>
46 #include <asm/desc.h>
47 #include <asm/div64.h>
48 #include <asm/flushtlb.h>
49 #include <asm/msr.h>
50 #include <mach_apic.h>
51 #include <mach_wakecpu.h>
52 #include <smpboot_hooks.h>
54 static inline int set_kernel_exec(unsigned long x, int y) { return 0; }
55 #define alloc_bootmem_low_pages(x) __va(0x90000) /* trampoline address */
57 /* Set if we find a B stepping CPU */
58 static int __devinitdata smp_b_stepping;
60 /* Number of siblings per CPU package */
61 int smp_num_siblings = 1;
62 #ifdef CONFIG_X86_HT
63 EXPORT_SYMBOL(smp_num_siblings);
64 #endif
66 /* Package ID of each logical CPU */
67 int phys_proc_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
69 /* Core ID of each logical CPU */
70 int cpu_core_id[NR_CPUS] __read_mostly = {[0 ... NR_CPUS-1] = BAD_APICID};
72 /* representing HT siblings of each logical CPU */
73 cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
74 EXPORT_SYMBOL(cpu_sibling_map);
76 /* representing HT and core siblings of each logical CPU */
77 cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
78 EXPORT_SYMBOL(cpu_core_map);
80 /* bitmap of online cpus */
81 cpumask_t cpu_online_map __read_mostly;
82 EXPORT_SYMBOL(cpu_online_map);
84 cpumask_t cpu_callin_map;
85 cpumask_t cpu_callout_map;
86 EXPORT_SYMBOL(cpu_callout_map);
87 #ifdef CONFIG_HOTPLUG_CPU
88 cpumask_t cpu_possible_map = CPU_MASK_ALL;
89 #else
90 cpumask_t cpu_possible_map;
91 #endif
92 EXPORT_SYMBOL(cpu_possible_map);
93 static cpumask_t smp_commenced_mask;
95 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
96 * is no way to resync one AP against BP. TBD: for prescott and above, we
97 * should use IA64's algorithm
98 */
99 static int __devinitdata tsc_sync_disabled;
101 /* Per CPU bogomips and other parameters */
102 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
103 EXPORT_SYMBOL(cpu_data);
105 u8 x86_cpu_to_apicid[NR_CPUS] __read_mostly =
106 { [0 ... NR_CPUS-1] = 0xff };
107 EXPORT_SYMBOL(x86_cpu_to_apicid);
109 /*
110 * Trampoline 80x86 program as an array.
111 */
113 extern unsigned char trampoline_data [];
114 extern unsigned char trampoline_end [];
115 static unsigned char *trampoline_base;
116 static int trampoline_exec;
118 static void map_cpu_to_logical_apicid(void);
120 /* State of each CPU. */
121 /*DEFINE_PER_CPU(int, cpu_state) = { 0 };*/
123 /*
124 * Currently trivial. Write the real->protected mode
125 * bootstrap into the page concerned. The caller
126 * has made sure it's suitably aligned.
127 */
129 static unsigned long __devinit setup_trampoline(void)
130 {
131 memcpy(trampoline_base, trampoline_data, trampoline_end - trampoline_data);
132 return virt_to_maddr(trampoline_base);
133 }
135 /*
136 * We are called very early to get the low memory for the
137 * SMP bootup trampoline page.
138 */
139 void __init smp_alloc_memory(void)
140 {
141 trampoline_base = (void *) alloc_bootmem_low_pages(PAGE_SIZE);
142 /*
143 * Has to be in very low memory so we can execute
144 * real-mode AP code.
145 */
146 if (__pa(trampoline_base) >= 0x9F000)
147 BUG();
148 /*
149 * Make the SMP trampoline executable:
150 */
151 trampoline_exec = set_kernel_exec((unsigned long)trampoline_base, 1);
152 }
154 /*
155 * The bootstrap kernel entry code has set these up. Save them for
156 * a given CPU
157 */
159 static void __devinit smp_store_cpu_info(int id)
160 {
161 struct cpuinfo_x86 *c = cpu_data + id;
163 *c = boot_cpu_data;
164 if (id!=0)
165 identify_cpu(c);
166 /*
167 * Mask B, Pentium, but not Pentium MMX
168 */
169 if (c->x86_vendor == X86_VENDOR_INTEL &&
170 c->x86 == 5 &&
171 c->x86_mask >= 1 && c->x86_mask <= 4 &&
172 c->x86_model <= 3)
173 /*
174 * Remember we have B step Pentia with bugs
175 */
176 smp_b_stepping = 1;
178 /*
179 * Certain Athlons might work (for various values of 'work') in SMP
180 * but they are not certified as MP capable.
181 */
182 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) {
184 /* Athlon 660/661 is valid. */
185 if ((c->x86_model==6) && ((c->x86_mask==0) || (c->x86_mask==1)))
186 goto valid_k7;
188 /* Duron 670 is valid */
189 if ((c->x86_model==7) && (c->x86_mask==0))
190 goto valid_k7;
192 /*
193 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
194 * It's worth noting that the A5 stepping (662) of some Athlon XP's
195 * have the MP bit set.
196 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
197 */
198 if (((c->x86_model==6) && (c->x86_mask>=2)) ||
199 ((c->x86_model==7) && (c->x86_mask>=1)) ||
200 (c->x86_model> 7))
201 if (cpu_has_mp)
202 goto valid_k7;
204 /* If we get here, it's not a certified SMP capable AMD system. */
205 add_taint(TAINT_UNSAFE_SMP);
206 }
208 valid_k7:
209 ;
210 }
212 /*
213 * TSC synchronization.
214 *
215 * We first check whether all CPUs have their TSC's synchronized,
216 * then we print a warning if not, and always resync.
217 */
219 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
220 static atomic_t tsc_count_start = ATOMIC_INIT(0);
221 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
222 static unsigned long long tsc_values[NR_CPUS];
224 #define NR_LOOPS 5
226 static void __init synchronize_tsc_bp (void)
227 {
228 int i;
229 unsigned long long t0;
230 unsigned long long sum, avg;
231 long long delta;
232 unsigned int one_usec;
233 int buggy = 0;
235 printk(KERN_INFO "checking TSC synchronization across %u CPUs: ", num_booting_cpus());
237 /* convert from kcyc/sec to cyc/usec */
238 one_usec = cpu_khz / 1000;
240 atomic_set(&tsc_start_flag, 1);
241 wmb();
243 /*
244 * We loop a few times to get a primed instruction cache,
245 * then the last pass is more or less synchronized and
246 * the BP and APs set their cycle counters to zero all at
247 * once. This reduces the chance of having random offsets
248 * between the processors, and guarantees that the maximum
249 * delay between the cycle counters is never bigger than
250 * the latency of information-passing (cachelines) between
251 * two CPUs.
252 */
253 for (i = 0; i < NR_LOOPS; i++) {
254 /*
255 * all APs synchronize but they loop on '== num_cpus'
256 */
257 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1)
258 mb();
259 atomic_set(&tsc_count_stop, 0);
260 wmb();
261 /*
262 * this lets the APs save their current TSC:
263 */
264 atomic_inc(&tsc_count_start);
266 rdtscll(tsc_values[smp_processor_id()]);
267 /*
268 * We clear the TSC in the last loop:
269 */
270 if (i == NR_LOOPS-1)
271 write_tsc(0, 0);
273 /*
274 * Wait for all APs to leave the synchronization point:
275 */
276 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1)
277 mb();
278 atomic_set(&tsc_count_start, 0);
279 wmb();
280 atomic_inc(&tsc_count_stop);
281 }
283 sum = 0;
284 for (i = 0; i < NR_CPUS; i++) {
285 if (cpu_isset(i, cpu_callout_map)) {
286 t0 = tsc_values[i];
287 sum += t0;
288 }
289 }
290 avg = sum;
291 do_div(avg, num_booting_cpus());
293 sum = 0;
294 for (i = 0; i < NR_CPUS; i++) {
295 if (!cpu_isset(i, cpu_callout_map))
296 continue;
297 delta = tsc_values[i] - avg;
298 if (delta < 0)
299 delta = -delta;
300 /*
301 * We report bigger than 2 microseconds clock differences.
302 */
303 if (delta > 2*one_usec) {
304 long realdelta;
305 if (!buggy) {
306 buggy = 1;
307 printk("\n");
308 }
309 realdelta = delta;
310 do_div(realdelta, one_usec);
311 if (tsc_values[i] < avg)
312 realdelta = -realdelta;
314 printk(KERN_INFO "CPU#%d had %ld usecs TSC skew, fixed it up.\n", i, realdelta);
315 }
317 sum += delta;
318 }
319 if (!buggy)
320 printk("passed.\n");
321 }
323 static void __init synchronize_tsc_ap (void)
324 {
325 int i;
327 /*
328 * Not every cpu is online at the time
329 * this gets called, so we first wait for the BP to
330 * finish SMP initialization:
331 */
332 while (!atomic_read(&tsc_start_flag)) mb();
334 for (i = 0; i < NR_LOOPS; i++) {
335 atomic_inc(&tsc_count_start);
336 while (atomic_read(&tsc_count_start) != num_booting_cpus())
337 mb();
339 rdtscll(tsc_values[smp_processor_id()]);
340 if (i == NR_LOOPS-1)
341 write_tsc(0, 0);
343 atomic_inc(&tsc_count_stop);
344 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
345 }
346 }
347 #undef NR_LOOPS
349 extern void calibrate_delay(void);
351 static atomic_t init_deasserted;
353 void __devinit smp_callin(void)
354 {
355 int cpuid, phys_id, i;
357 /*
358 * If waken up by an INIT in an 82489DX configuration
359 * we may get here before an INIT-deassert IPI reaches
360 * our local APIC. We have to wait for the IPI or we'll
361 * lock up on an APIC access.
362 */
363 wait_for_init_deassert(&init_deasserted);
365 /*
366 * (This works even if the APIC is not enabled.)
367 */
368 phys_id = GET_APIC_ID(apic_read(APIC_ID));
369 cpuid = smp_processor_id();
370 if (cpu_isset(cpuid, cpu_callin_map)) {
371 printk("huh, phys CPU#%d, CPU#%d already present??\n",
372 phys_id, cpuid);
373 BUG();
374 }
375 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
377 /*
378 * STARTUP IPIs are fragile beasts as they might sometimes
379 * trigger some glue motherboard logic. Complete APIC bus
380 * silence for 1 second, this overestimates the time the
381 * boot CPU is spending to send the up to 2 STARTUP IPIs
382 * by a factor of two. This should be enough.
383 */
385 /*
386 * Waiting 2s total for startup
387 */
388 for (i = 0; i < 200; i++) {
389 /*
390 * Has the boot CPU finished it's STARTUP sequence?
391 */
392 if (cpu_isset(cpuid, cpu_callout_map))
393 break;
394 rep_nop();
395 mdelay(10);
396 }
398 if (!cpu_isset(cpuid, cpu_callout_map)) {
399 printk("BUG: CPU%d started up but did not get a callout!\n",
400 cpuid);
401 BUG();
402 }
404 /*
405 * the boot CPU has finished the init stage and is spinning
406 * on callin_map until we finish. We are free to set up this
407 * CPU, first the APIC. (this is probably redundant on most
408 * boards)
409 */
411 Dprintk("CALLIN, before setup_local_APIC().\n");
412 smp_callin_clear_local_apic();
413 setup_local_APIC();
414 map_cpu_to_logical_apicid();
416 #if 0
417 /*
418 * Get our bogomips.
419 */
420 calibrate_delay();
421 Dprintk("Stack at about %p\n",&cpuid);
422 #endif
424 /*
425 * Save our processor parameters
426 */
427 smp_store_cpu_info(cpuid);
429 disable_APIC_timer();
431 /*
432 * Allow the master to continue.
433 */
434 cpu_set(cpuid, cpu_callin_map);
436 /*
437 * Synchronize the TSC with the BP
438 */
439 if (cpu_has_tsc && cpu_khz && !tsc_sync_disabled)
440 synchronize_tsc_ap();
441 calibrate_tsc_ap();
442 }
444 static int cpucount, booting_cpu;
446 /* representing cpus for which sibling maps can be computed */
447 static cpumask_t cpu_sibling_setup_map;
449 static inline void
450 set_cpu_sibling_map(int cpu)
451 {
452 int i;
453 struct cpuinfo_x86 *c = cpu_data;
455 cpu_set(cpu, cpu_sibling_setup_map);
457 if (smp_num_siblings > 1) {
458 for_each_cpu_mask(i, cpu_sibling_setup_map) {
459 if (phys_proc_id[cpu] == phys_proc_id[i] &&
460 cpu_core_id[cpu] == cpu_core_id[i]) {
461 cpu_set(i, cpu_sibling_map[cpu]);
462 cpu_set(cpu, cpu_sibling_map[i]);
463 cpu_set(i, cpu_core_map[cpu]);
464 cpu_set(cpu, cpu_core_map[i]);
465 }
466 }
467 } else {
468 cpu_set(cpu, cpu_sibling_map[cpu]);
469 }
471 if (current_cpu_data.x86_max_cores == 1) {
472 cpu_core_map[cpu] = cpu_sibling_map[cpu];
473 c[cpu].booted_cores = 1;
474 return;
475 }
477 for_each_cpu_mask(i, cpu_sibling_setup_map) {
478 if (phys_proc_id[cpu] == phys_proc_id[i]) {
479 cpu_set(i, cpu_core_map[cpu]);
480 cpu_set(cpu, cpu_core_map[i]);
481 /*
482 * Does this new cpu bringup a new core?
483 */
484 if (cpus_weight(cpu_sibling_map[cpu]) == 1) {
485 /*
486 * for each core in package, increment
487 * the booted_cores for this new cpu
488 */
489 if (first_cpu(cpu_sibling_map[i]) == i)
490 c[cpu].booted_cores++;
491 /*
492 * increment the core count for all
493 * the other cpus in this package
494 */
495 if (i != cpu)
496 c[i].booted_cores++;
497 } else if (i != cpu && !c[cpu].booted_cores)
498 c[cpu].booted_cores = c[i].booted_cores;
499 }
500 }
501 }
503 #ifdef CONFIG_X86_32
504 static void construct_percpu_idt(unsigned int cpu)
505 {
506 unsigned char idt_load[10];
508 idt_tables[cpu] = xmalloc_array(idt_entry_t, IDT_ENTRIES);
509 memcpy(idt_tables[cpu], idt_table, IDT_ENTRIES*sizeof(idt_entry_t));
511 *(unsigned short *)(&idt_load[0]) = (IDT_ENTRIES*sizeof(idt_entry_t))-1;
512 *(unsigned long *)(&idt_load[2]) = (unsigned long)idt_tables[cpu];
513 __asm__ __volatile__ ( "lidt %0" : "=m" (idt_load) );
514 }
515 #endif
517 /*
518 * Activate a secondary processor.
519 */
520 void __devinit start_secondary(void *unused)
521 {
522 /*
523 * Dont put anything before smp_callin(), SMP
524 * booting is too fragile that we want to limit the
525 * things done here to the most necessary things.
526 */
527 unsigned int cpu = booting_cpu;
529 extern void percpu_traps_init(void);
531 set_processor_id(cpu);
532 set_current(idle_vcpu[cpu]);
533 set_current_execstate(idle_vcpu[cpu]);
535 percpu_traps_init();
537 cpu_init();
538 /*preempt_disable();*/
539 smp_callin();
540 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
541 rep_nop();
543 #ifdef CONFIG_X86_32
544 /*
545 * At this point, boot CPU has fully initialised the IDT. It is
546 * now safe to make ourselves a private copy.
547 */
548 construct_percpu_idt(cpu);
549 #endif
551 setup_secondary_APIC_clock();
552 enable_APIC_timer();
553 /*
554 * low-memory mappings have been cleared, flush them from
555 * the local TLBs too.
556 */
557 local_flush_tlb();
559 /* This must be done before setting cpu_online_map */
560 set_cpu_sibling_map(raw_smp_processor_id());
561 wmb();
563 /*
564 * We need to hold call_lock, so there is no inconsistency
565 * between the time smp_call_function() determines number of
566 * IPI receipients, and the time when the determination is made
567 * for which cpus receive the IPI. Holding this
568 * lock helps us to not include this cpu in a currently in progress
569 * smp_call_function().
570 */
571 /*lock_ipi_call_lock();*/
572 cpu_set(smp_processor_id(), cpu_online_map);
573 /*unlock_ipi_call_lock();*/
574 /*per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;*/
576 /* We can take interrupts now: we're officially "up". */
577 local_irq_enable();
579 init_percpu_time();
581 wmb();
582 startup_cpu_idle_loop();
583 }
585 extern struct {
586 void * esp;
587 unsigned short ss;
588 } stack_start;
590 #ifdef CONFIG_NUMA
592 /* which logical CPUs are on which nodes */
593 cpumask_t node_2_cpu_mask[MAX_NUMNODES] __read_mostly =
594 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE };
595 /* which node each logical CPU is on */
596 int cpu_2_node[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 };
597 EXPORT_SYMBOL(cpu_2_node);
599 /* set up a mapping between cpu and node. */
600 static inline void map_cpu_to_node(int cpu, int node)
601 {
602 printk("Mapping cpu %d to node %d\n", cpu, node);
603 cpu_set(cpu, node_2_cpu_mask[node]);
604 cpu_2_node[cpu] = node;
605 }
607 /* undo a mapping between cpu and node. */
608 static inline void unmap_cpu_to_node(int cpu)
609 {
610 int node;
612 printk("Unmapping cpu %d from all nodes\n", cpu);
613 for (node = 0; node < MAX_NUMNODES; node ++)
614 cpu_clear(cpu, node_2_cpu_mask[node]);
615 cpu_2_node[cpu] = 0;
616 }
617 #else /* !CONFIG_NUMA */
619 #define map_cpu_to_node(cpu, node) ({})
620 #define unmap_cpu_to_node(cpu) ({})
622 #endif /* CONFIG_NUMA */
624 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = BAD_APICID };
626 static void map_cpu_to_logical_apicid(void)
627 {
628 int cpu = smp_processor_id();
629 int apicid = logical_smp_processor_id();
631 cpu_2_logical_apicid[cpu] = apicid;
632 map_cpu_to_node(cpu, apicid_to_node(apicid));
633 }
635 static void unmap_cpu_to_logical_apicid(int cpu)
636 {
637 cpu_2_logical_apicid[cpu] = BAD_APICID;
638 unmap_cpu_to_node(cpu);
639 }
641 #if APIC_DEBUG
642 static inline void __inquire_remote_apic(int apicid)
643 {
644 int i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
645 char *names[] = { "ID", "VERSION", "SPIV" };
646 int timeout, status;
648 printk("Inquiring remote APIC #%d...\n", apicid);
650 for (i = 0; i < ARRAY_SIZE(regs); i++) {
651 printk("... APIC #%d %s: ", apicid, names[i]);
653 /*
654 * Wait for idle.
655 */
656 apic_wait_icr_idle();
658 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
659 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
661 timeout = 0;
662 do {
663 udelay(100);
664 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
665 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
667 switch (status) {
668 case APIC_ICR_RR_VALID:
669 status = apic_read(APIC_RRR);
670 printk("%08x\n", status);
671 break;
672 default:
673 printk("failed\n");
674 }
675 }
676 }
677 #endif
679 #ifdef WAKE_SECONDARY_VIA_NMI
680 /*
681 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
682 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
683 * won't ... remember to clear down the APIC, etc later.
684 */
685 static int __devinit
686 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
687 {
688 unsigned long send_status = 0, accept_status = 0;
689 int timeout, maxlvt;
691 /* Target chip */
692 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(logical_apicid));
694 /* Boot on the stack */
695 /* Kick the second */
696 apic_write_around(APIC_ICR, APIC_DM_NMI | APIC_DEST_LOGICAL);
698 Dprintk("Waiting for send to finish...\n");
699 timeout = 0;
700 do {
701 Dprintk("+");
702 udelay(100);
703 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
704 } while (send_status && (timeout++ < 1000));
706 /*
707 * Give the other CPU some time to accept the IPI.
708 */
709 udelay(200);
710 /*
711 * Due to the Pentium erratum 3AP.
712 */
713 maxlvt = get_maxlvt();
714 if (maxlvt > 3) {
715 apic_read_around(APIC_SPIV);
716 apic_write(APIC_ESR, 0);
717 }
718 accept_status = (apic_read(APIC_ESR) & 0xEF);
719 Dprintk("NMI sent.\n");
721 if (send_status)
722 printk("APIC never delivered???\n");
723 if (accept_status)
724 printk("APIC delivery error (%lx).\n", accept_status);
726 return (send_status | accept_status);
727 }
728 #endif /* WAKE_SECONDARY_VIA_NMI */
730 #ifdef WAKE_SECONDARY_VIA_INIT
731 static int __devinit
732 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
733 {
734 unsigned long send_status = 0, accept_status = 0;
735 int maxlvt, timeout, num_starts, j;
737 /*
738 * Be paranoid about clearing APIC errors.
739 */
740 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
741 apic_read_around(APIC_SPIV);
742 apic_write(APIC_ESR, 0);
743 apic_read(APIC_ESR);
744 }
746 Dprintk("Asserting INIT.\n");
748 /*
749 * Turn INIT on target chip
750 */
751 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
753 /*
754 * Send IPI
755 */
756 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
757 | APIC_DM_INIT);
759 Dprintk("Waiting for send to finish...\n");
760 timeout = 0;
761 do {
762 Dprintk("+");
763 udelay(100);
764 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
765 } while (send_status && (timeout++ < 1000));
767 mdelay(10);
769 Dprintk("Deasserting INIT.\n");
771 /* Target chip */
772 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
774 /* Send IPI */
775 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
777 Dprintk("Waiting for send to finish...\n");
778 timeout = 0;
779 do {
780 Dprintk("+");
781 udelay(100);
782 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
783 } while (send_status && (timeout++ < 1000));
785 atomic_set(&init_deasserted, 1);
787 /*
788 * Should we send STARTUP IPIs ?
789 *
790 * Determine this based on the APIC version.
791 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
792 */
793 if (APIC_INTEGRATED(apic_version[phys_apicid]))
794 num_starts = 2;
795 else
796 num_starts = 0;
798 /*
799 * Run STARTUP IPI loop.
800 */
801 Dprintk("#startup loops: %d.\n", num_starts);
803 maxlvt = get_maxlvt();
805 for (j = 1; j <= num_starts; j++) {
806 Dprintk("Sending STARTUP #%d.\n",j);
807 apic_read_around(APIC_SPIV);
808 apic_write(APIC_ESR, 0);
809 apic_read(APIC_ESR);
810 Dprintk("After apic_write.\n");
812 /*
813 * STARTUP IPI
814 */
816 /* Target chip */
817 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
819 /* Boot on the stack */
820 /* Kick the second */
821 apic_write_around(APIC_ICR, APIC_DM_STARTUP
822 | (start_eip >> 12));
824 /*
825 * Give the other CPU some time to accept the IPI.
826 */
827 udelay(300);
829 Dprintk("Startup point 1.\n");
831 Dprintk("Waiting for send to finish...\n");
832 timeout = 0;
833 do {
834 Dprintk("+");
835 udelay(100);
836 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
837 } while (send_status && (timeout++ < 1000));
839 /*
840 * Give the other CPU some time to accept the IPI.
841 */
842 udelay(200);
843 /*
844 * Due to the Pentium erratum 3AP.
845 */
846 if (maxlvt > 3) {
847 apic_read_around(APIC_SPIV);
848 apic_write(APIC_ESR, 0);
849 }
850 accept_status = (apic_read(APIC_ESR) & 0xEF);
851 if (send_status || accept_status)
852 break;
853 }
854 Dprintk("After Startup.\n");
856 if (send_status)
857 printk("APIC never delivered???\n");
858 if (accept_status)
859 printk("APIC delivery error (%lx).\n", accept_status);
861 return (send_status | accept_status);
862 }
863 #endif /* WAKE_SECONDARY_VIA_INIT */
865 extern cpumask_t cpu_initialized;
866 static inline int alloc_cpu_id(void)
867 {
868 cpumask_t tmp_map;
869 int cpu;
870 cpus_complement(tmp_map, cpu_present_map);
871 cpu = first_cpu(tmp_map);
872 if (cpu >= NR_CPUS)
873 return -ENODEV;
874 return cpu;
875 }
877 static int __devinit do_boot_cpu(int apicid, int cpu)
878 /*
879 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
880 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
881 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
882 */
883 {
884 unsigned long boot_error;
885 int timeout;
886 unsigned long start_eip;
887 unsigned short nmi_high = 0, nmi_low = 0;
888 struct domain *d;
889 struct vcpu *v;
890 int vcpu_id;
892 ++cpucount;
894 booting_cpu = cpu;
896 if ((vcpu_id = cpu % MAX_VIRT_CPUS) == 0) {
897 d = domain_create(IDLE_DOMAIN_ID, cpu);
898 BUG_ON(d == NULL);
899 v = d->vcpu[0];
900 } else {
901 d = idle_vcpu[cpu - vcpu_id]->domain;
902 BUG_ON(d == NULL);
903 v = alloc_vcpu(d, vcpu_id, cpu);
904 }
906 idle_vcpu[cpu] = v;
907 BUG_ON(v == NULL);
909 v->arch.monitor_table = mk_pagetable(__pa(idle_pg_table));
911 /* start_eip had better be page-aligned! */
912 start_eip = setup_trampoline();
914 /* So we see what's up */
915 printk("Booting processor %d/%d eip %lx\n", cpu, apicid, start_eip);
917 stack_start.esp = alloc_xenheap_pages(STACK_ORDER);
919 /* Debug build: detect stack overflow by setting up a guard page. */
920 memguard_guard_stack(stack_start.esp);
922 /*
923 * This grunge runs the startup process for
924 * the targeted processor.
925 */
927 atomic_set(&init_deasserted, 0);
929 Dprintk("Setting warm reset code and vector.\n");
931 store_NMI_vector(&nmi_high, &nmi_low);
933 smpboot_setup_warm_reset_vector(start_eip);
935 /*
936 * Starting actual IPI sequence...
937 */
938 boot_error = wakeup_secondary_cpu(apicid, start_eip);
940 if (!boot_error) {
941 /*
942 * allow APs to start initializing.
943 */
944 Dprintk("Before Callout %d.\n", cpu);
945 cpu_set(cpu, cpu_callout_map);
946 Dprintk("After Callout %d.\n", cpu);
948 /*
949 * Wait 5s total for a response
950 */
951 for (timeout = 0; timeout < 50000; timeout++) {
952 if (cpu_isset(cpu, cpu_callin_map))
953 break; /* It has booted */
954 udelay(100);
955 }
957 if (cpu_isset(cpu, cpu_callin_map)) {
958 /* number CPUs logically, starting from 1 (BSP is 0) */
959 Dprintk("OK.\n");
960 printk("CPU%d: ", cpu);
961 print_cpu_info(&cpu_data[cpu]);
962 Dprintk("CPU has booted.\n");
963 } else {
964 boot_error= 1;
965 if (*((volatile unsigned char *)trampoline_base)
966 == 0xA5)
967 /* trampoline started but...? */
968 printk("Stuck ??\n");
969 else
970 /* trampoline code not run */
971 printk("Not responding.\n");
972 inquire_remote_apic(apicid);
973 }
974 }
976 if (boot_error) {
977 /* Try to put things back the way they were before ... */
978 unmap_cpu_to_logical_apicid(cpu);
979 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
980 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */
981 cpucount--;
982 } else {
983 x86_cpu_to_apicid[cpu] = apicid;
984 cpu_set(cpu, cpu_present_map);
985 }
987 /* mark "stuck" area as not stuck */
988 *((volatile unsigned long *)trampoline_base) = 0;
990 return boot_error;
991 }
993 /*
994 * Cycle through the processors sending APIC IPIs to boot each.
995 */
997 static int boot_cpu_logical_apicid;
998 /* Where the IO area was mapped on multiquad, always 0 otherwise */
999 void *xquad_portio;
1000 #ifdef CONFIG_X86_NUMAQ
1001 EXPORT_SYMBOL(xquad_portio);
1002 #endif
1004 static void __init smp_boot_cpus(unsigned int max_cpus)
1006 int apicid, cpu, bit, kicked;
1007 #ifdef BOGOMIPS
1008 unsigned long bogosum = 0;
1009 #endif
1011 /*
1012 * Setup boot CPU information
1013 */
1014 smp_store_cpu_info(0); /* Final full version of the data */
1015 printk("CPU%d: ", 0);
1016 print_cpu_info(&cpu_data[0]);
1018 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
1019 boot_cpu_logical_apicid = logical_smp_processor_id();
1020 x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
1022 /*current_thread_info()->cpu = 0;*/
1023 /*smp_tune_scheduling();*/
1025 set_cpu_sibling_map(0);
1027 /*
1028 * If we couldn't find an SMP configuration at boot time,
1029 * get out of here now!
1030 */
1031 if (!smp_found_config && !acpi_lapic) {
1032 printk(KERN_NOTICE "SMP motherboard not detected.\n");
1033 init_uniprocessor:
1034 phys_cpu_present_map = physid_mask_of_physid(0);
1035 if (APIC_init_uniprocessor())
1036 printk(KERN_NOTICE "Local APIC not detected."
1037 " Using dummy APIC emulation.\n");
1038 map_cpu_to_logical_apicid();
1039 cpu_set(0, cpu_sibling_map[0]);
1040 cpu_set(0, cpu_core_map[0]);
1041 return;
1044 /*
1045 * Should not be necessary because the MP table should list the boot
1046 * CPU too, but we do it for the sake of robustness anyway.
1047 * Makes no sense to do this check in clustered apic mode, so skip it
1048 */
1049 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) {
1050 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1051 boot_cpu_physical_apicid);
1052 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1055 /*
1056 * If we couldn't find a local APIC, then get out of here now!
1057 */
1058 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && !cpu_has_apic) {
1059 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1060 boot_cpu_physical_apicid);
1061 goto init_uniprocessor;
1064 verify_local_APIC();
1066 /*
1067 * If SMP should be disabled, then really disable it!
1068 */
1069 if (!max_cpus)
1070 goto init_uniprocessor;
1072 connect_bsp_APIC();
1073 setup_local_APIC();
1074 map_cpu_to_logical_apicid();
1077 setup_portio_remap();
1079 /*
1080 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1082 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1083 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1084 * clustered apic ID.
1085 */
1086 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
1088 kicked = 1;
1089 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
1090 apicid = cpu_present_to_apicid(bit);
1091 /*
1092 * Don't even attempt to start the boot CPU!
1093 */
1094 if ((apicid == boot_cpu_apicid) || (apicid == BAD_APICID))
1095 continue;
1097 if (!check_apicid_present(bit))
1098 continue;
1099 if (max_cpus <= cpucount+1)
1100 continue;
1102 if (((cpu = alloc_cpu_id()) <= 0) || do_boot_cpu(apicid, cpu))
1103 printk("CPU #%d not responding - cannot use it.\n",
1104 apicid);
1105 else
1106 ++kicked;
1109 /*
1110 * Cleanup possible dangling ends...
1111 */
1112 smpboot_restore_warm_reset_vector();
1114 #ifdef BOGOMIPS
1115 /*
1116 * Allow the user to impress friends.
1117 */
1118 Dprintk("Before bogomips.\n");
1119 for (cpu = 0; cpu < NR_CPUS; cpu++)
1120 if (cpu_isset(cpu, cpu_callout_map))
1121 bogosum += cpu_data[cpu].loops_per_jiffy;
1122 printk(KERN_INFO
1123 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1124 cpucount+1,
1125 bogosum/(500000/HZ),
1126 (bogosum/(5000/HZ))%100);
1127 #else
1128 printk("Total of %d processors activated.\n", cpucount+1);
1129 #endif
1131 Dprintk("Before bogocount - setting activated=1.\n");
1133 if (smp_b_stepping)
1134 printk(KERN_WARNING "WARNING: SMP operation may be unreliable with B stepping processors.\n");
1136 /*
1137 * Don't taint if we are running SMP kernel on a single non-MP
1138 * approved Athlon
1139 */
1140 if (tainted & TAINT_UNSAFE_SMP) {
1141 if (cpucount)
1142 printk (KERN_INFO "WARNING: This combination of AMD processors is not suitable for SMP.\n");
1143 else
1144 tainted &= ~TAINT_UNSAFE_SMP;
1147 Dprintk("Boot done.\n");
1149 /*
1150 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1151 * efficiently.
1152 */
1153 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1154 cpus_clear(cpu_sibling_map[cpu]);
1155 cpus_clear(cpu_core_map[cpu]);
1158 cpu_set(0, cpu_sibling_map[0]);
1159 cpu_set(0, cpu_core_map[0]);
1161 if (nmi_watchdog == NMI_LOCAL_APIC)
1162 check_nmi_watchdog();
1164 smpboot_setup_io_apic();
1166 setup_boot_APIC_clock();
1168 /*
1169 * Synchronize the TSC with the AP
1170 */
1171 if (cpu_has_tsc && cpucount && cpu_khz)
1172 synchronize_tsc_bp();
1173 calibrate_tsc_bp();
1176 /* These are wrappers to interface to the new boot process. Someone
1177 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1178 void __init smp_prepare_cpus(unsigned int max_cpus)
1180 smp_commenced_mask = cpumask_of_cpu(0);
1181 cpu_callin_map = cpumask_of_cpu(0);
1182 mb();
1183 smp_boot_cpus(max_cpus);
1186 void __devinit smp_prepare_boot_cpu(void)
1188 cpu_set(smp_processor_id(), cpu_online_map);
1189 cpu_set(smp_processor_id(), cpu_callout_map);
1190 cpu_set(smp_processor_id(), cpu_present_map);
1191 cpu_set(smp_processor_id(), cpu_possible_map);
1192 /*per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;*/
1195 int __devinit __cpu_up(unsigned int cpu)
1197 /* In case one didn't come up */
1198 if (!cpu_isset(cpu, cpu_callin_map)) {
1199 printk(KERN_DEBUG "skipping cpu%d, didn't come online\n", cpu);
1200 local_irq_enable();
1201 return -EIO;
1204 local_irq_enable();
1205 /*per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;*/
1206 /* Unleash the CPU! */
1207 cpu_set(cpu, smp_commenced_mask);
1208 while (!cpu_isset(cpu, cpu_online_map)) {
1209 mb();
1210 if (softirq_pending(0))
1211 do_softirq();
1213 return 0;
1216 void __init smp_cpus_done(unsigned int max_cpus)
1218 #ifdef CONFIG_X86_IO_APIC
1219 setup_ioapic_dest();
1220 #endif
1221 #ifdef CONFIG_X86_64
1222 zap_low_mappings();
1223 #endif
1224 #ifndef CONFIG_HOTPLUG_CPU
1225 /*
1226 * Disable executability of the SMP trampoline:
1227 */
1228 set_kernel_exec((unsigned long)trampoline_base, trampoline_exec);
1229 #endif
1232 void __init smp_intr_init(void)
1234 /*
1235 * IRQ0 must be given a fixed assignment and initialized,
1236 * because it's used before the IO-APIC is set up.
1237 */
1238 irq_vector[0] = FIRST_DEVICE_VECTOR;
1239 vector_irq[FIRST_DEVICE_VECTOR] = 0;
1241 /* IPI for event checking. */
1242 set_intr_gate(EVENT_CHECK_VECTOR, event_check_interrupt);
1244 /* IPI for invalidation */
1245 set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt);
1247 /* IPI for generic function call */
1248 set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);