ia64/xen-unstable

view xen/include/asm-x86/hvm/vmx/vmcs.h @ 9334:56a775219c88

This patch fix HVM/VMX time resolution issue that cause IA32E complain
"loss tick" occationally and APIC time calibration issue.

Signed-off-by: Xiaowei Yang <xiaowei.yang@intel.com>
Signed-off-by: Eddie Dong <eddie.dong@intel.com>
author kaf24@firebug.cl.cam.ac.uk
date Sun Mar 19 18:52:20 2006 +0100 (2006-03-19)
parents 796ac2386a24
children f0e14b4e535c
line source
1 /*
2 * vmcs.h: VMCS related definitions
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 #ifndef __ASM_X86_HVM_VMX_VMCS_H__
20 #define __ASM_X86_HVM_VMX_VMCS_H__
22 #include <asm/config.h>
23 #include <asm/hvm/io.h>
24 #include <asm/hvm/vmx/cpu.h>
25 #include <public/hvm/vmx_assist.h>
27 extern int start_vmx(void);
28 extern void stop_vmx(void);
30 void vmx_final_setup_guest(struct vcpu *v);
32 void vmx_enter_scheduler(void);
34 enum {
35 VMX_CPU_STATE_PAE_ENABLED=0,
36 VMX_CPU_STATE_LME_ENABLED,
37 VMX_CPU_STATE_LMA_ENABLED,
38 VMX_CPU_STATE_ASSIST_ENABLED,
39 };
41 #define VMX_LONG_GUEST(ed) \
42 (test_bit(VMX_CPU_STATE_LMA_ENABLED, &ed->arch.hvm_vmx.cpu_state))
44 struct vmcs_struct {
45 u32 vmcs_revision_id;
46 unsigned char data [0]; /* vmcs size is read from MSR */
47 };
49 extern int vmcs_size;
51 enum {
52 VMX_INDEX_MSR_LSTAR = 0,
53 VMX_INDEX_MSR_STAR,
54 VMX_INDEX_MSR_CSTAR,
55 VMX_INDEX_MSR_SYSCALL_MASK,
56 VMX_INDEX_MSR_EFER,
58 VMX_MSR_COUNT,
59 };
61 struct vmx_msr_state {
62 unsigned long flags;
63 unsigned long msr_items[VMX_MSR_COUNT];
64 unsigned long shadow_gs;
65 };
67 struct arch_vmx_struct {
68 struct vmcs_struct *vmcs; /* VMCS pointer in virtual. */
69 unsigned int launch_cpu; /* VMCS is valid on this CPU. */
70 u32 exec_control; /* cache of cpu execution control */
71 unsigned long flags; /* VMCS flags */
72 unsigned long cpu_cr0; /* copy of guest CR0 */
73 unsigned long cpu_shadow_cr0; /* copy of guest read shadow CR0 */
74 unsigned long cpu_cr2; /* save CR2 */
75 unsigned long cpu_cr3;
76 unsigned long cpu_state;
77 unsigned long cpu_based_exec_control;
78 struct vmx_msr_state msr_content;
79 void *io_bitmap_a, *io_bitmap_b;
80 struct timer hlt_timer; /* hlt ins emulation wakeup timer */
81 };
83 #define vmx_schedule_tail(next) \
84 (next)->thread.arch_vmx.arch_vmx_schedule_tail((next))
86 #define ARCH_VMX_VMCS_LOADED 0 /* VMCS has been loaded and active */
87 #define ARCH_VMX_VMCS_LAUNCH 1 /* Needs VMCS launch */
88 #define ARCH_VMX_VMCS_RESUME 2 /* Needs VMCS resume */
90 void vmx_do_resume(struct vcpu *);
91 struct vmcs_struct *alloc_vmcs(void);
92 int modify_vmcs(struct arch_vmx_struct *arch_vmx,
93 struct cpu_user_regs *regs);
94 void destroy_vmcs(struct arch_vmx_struct *arch_vmx);
96 extern void vmx_request_clear_vmcs(struct vcpu *v);
98 #define VMCS_USE_HOST_ENV 1
99 #define VMCS_USE_SEPARATE_ENV 0
101 extern int vmcs_version;
103 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
104 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008
105 #define CPU_BASED_HLT_EXITING 0x00000080
106 #define CPU_BASED_INVDPG_EXITING 0x00000200
107 #define CPU_BASED_MWAIT_EXITING 0x00000400
108 #define CPU_BASED_RDPMC_EXITING 0x00000800
109 #define CPU_BASED_RDTSC_EXITING 0x00001000
110 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000
111 #define CPU_BASED_CR8_STORE_EXITING 0x00100000
112 #define CPU_BASED_TPR_SHADOW 0x00200000
113 #define CPU_BASED_MOV_DR_EXITING 0x00800000
114 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000
115 #define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000
116 #define CPU_BASED_MONITOR_EXITING 0x20000000
117 #define CPU_BASED_PAUSE_EXITING 0x40000000
118 #define PIN_BASED_EXT_INTR_MASK 0x1
119 #define PIN_BASED_NMI_EXITING 0x8
121 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
122 #define VM_EXIT_HOST_ADD_SPACE_SIZE 0x00000200
125 /* VMCS Encordings */
126 enum vmcs_field {
127 GUEST_ES_SELECTOR = 0x00000800,
128 GUEST_CS_SELECTOR = 0x00000802,
129 GUEST_SS_SELECTOR = 0x00000804,
130 GUEST_DS_SELECTOR = 0x00000806,
131 GUEST_FS_SELECTOR = 0x00000808,
132 GUEST_GS_SELECTOR = 0x0000080a,
133 GUEST_LDTR_SELECTOR = 0x0000080c,
134 GUEST_TR_SELECTOR = 0x0000080e,
135 HOST_ES_SELECTOR = 0x00000c00,
136 HOST_CS_SELECTOR = 0x00000c02,
137 HOST_SS_SELECTOR = 0x00000c04,
138 HOST_DS_SELECTOR = 0x00000c06,
139 HOST_FS_SELECTOR = 0x00000c08,
140 HOST_GS_SELECTOR = 0x00000c0a,
141 HOST_TR_SELECTOR = 0x00000c0c,
142 IO_BITMAP_A = 0x00002000,
143 IO_BITMAP_A_HIGH = 0x00002001,
144 IO_BITMAP_B = 0x00002002,
145 IO_BITMAP_B_HIGH = 0x00002003,
146 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
147 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
148 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
149 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
150 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
151 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
152 TSC_OFFSET = 0x00002010,
153 TSC_OFFSET_HIGH = 0x00002011,
154 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
155 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
156 VMCS_LINK_POINTER = 0x00002800,
157 VMCS_LINK_POINTER_HIGH = 0x00002801,
158 GUEST_IA32_DEBUGCTL = 0x00002802,
159 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
160 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
161 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
162 EXCEPTION_BITMAP = 0x00004004,
163 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
164 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
165 CR3_TARGET_COUNT = 0x0000400a,
166 VM_EXIT_CONTROLS = 0x0000400c,
167 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
168 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
169 VM_ENTRY_CONTROLS = 0x00004012,
170 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
171 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
172 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
173 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
174 TPR_THRESHOLD = 0x0000401c,
175 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
176 VM_INSTRUCTION_ERROR = 0x00004400,
177 VM_EXIT_REASON = 0x00004402,
178 VM_EXIT_INTR_INFO = 0x00004404,
179 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
180 IDT_VECTORING_INFO_FIELD = 0x00004408,
181 IDT_VECTORING_ERROR_CODE = 0x0000440a,
182 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
183 VMX_INSTRUCTION_INFO = 0x0000440e,
184 GUEST_ES_LIMIT = 0x00004800,
185 GUEST_CS_LIMIT = 0x00004802,
186 GUEST_SS_LIMIT = 0x00004804,
187 GUEST_DS_LIMIT = 0x00004806,
188 GUEST_FS_LIMIT = 0x00004808,
189 GUEST_GS_LIMIT = 0x0000480a,
190 GUEST_LDTR_LIMIT = 0x0000480c,
191 GUEST_TR_LIMIT = 0x0000480e,
192 GUEST_GDTR_LIMIT = 0x00004810,
193 GUEST_IDTR_LIMIT = 0x00004812,
194 GUEST_ES_AR_BYTES = 0x00004814,
195 GUEST_CS_AR_BYTES = 0x00004816,
196 GUEST_SS_AR_BYTES = 0x00004818,
197 GUEST_DS_AR_BYTES = 0x0000481a,
198 GUEST_FS_AR_BYTES = 0x0000481c,
199 GUEST_GS_AR_BYTES = 0x0000481e,
200 GUEST_LDTR_AR_BYTES = 0x00004820,
201 GUEST_TR_AR_BYTES = 0x00004822,
202 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
203 GUEST_SYSENTER_CS = 0x0000482A,
204 HOST_IA32_SYSENTER_CS = 0x00004c00,
205 CR0_GUEST_HOST_MASK = 0x00006000,
206 CR4_GUEST_HOST_MASK = 0x00006002,
207 CR0_READ_SHADOW = 0x00006004,
208 CR4_READ_SHADOW = 0x00006006,
209 CR3_TARGET_VALUE0 = 0x00006008,
210 CR3_TARGET_VALUE1 = 0x0000600a,
211 CR3_TARGET_VALUE2 = 0x0000600c,
212 CR3_TARGET_VALUE3 = 0x0000600e,
213 EXIT_QUALIFICATION = 0x00006400,
214 GUEST_LINEAR_ADDRESS = 0x0000640a,
215 GUEST_CR0 = 0x00006800,
216 GUEST_CR3 = 0x00006802,
217 GUEST_CR4 = 0x00006804,
218 GUEST_ES_BASE = 0x00006806,
219 GUEST_CS_BASE = 0x00006808,
220 GUEST_SS_BASE = 0x0000680a,
221 GUEST_DS_BASE = 0x0000680c,
222 GUEST_FS_BASE = 0x0000680e,
223 GUEST_GS_BASE = 0x00006810,
224 GUEST_LDTR_BASE = 0x00006812,
225 GUEST_TR_BASE = 0x00006814,
226 GUEST_GDTR_BASE = 0x00006816,
227 GUEST_IDTR_BASE = 0x00006818,
228 GUEST_DR7 = 0x0000681a,
229 GUEST_RSP = 0x0000681c,
230 GUEST_RIP = 0x0000681e,
231 GUEST_RFLAGS = 0x00006820,
232 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
233 GUEST_SYSENTER_ESP = 0x00006824,
234 GUEST_SYSENTER_EIP = 0x00006826,
235 HOST_CR0 = 0x00006c00,
236 HOST_CR3 = 0x00006c02,
237 HOST_CR4 = 0x00006c04,
238 HOST_FS_BASE = 0x00006c06,
239 HOST_GS_BASE = 0x00006c08,
240 HOST_TR_BASE = 0x00006c0a,
241 HOST_GDTR_BASE = 0x00006c0c,
242 HOST_IDTR_BASE = 0x00006c0e,
243 HOST_IA32_SYSENTER_ESP = 0x00006c10,
244 HOST_IA32_SYSENTER_EIP = 0x00006c12,
245 HOST_RSP = 0x00006c14,
246 HOST_RIP = 0x00006c16,
247 };
249 #endif /* ASM_X86_HVM_VMX_VMCS_H__ */
251 /*
252 * Local variables:
253 * mode: C
254 * c-set-style: "BSD"
255 * c-basic-offset: 4
256 * tab-width: 4
257 * indent-tabs-mode: nil
258 * End:
259 */